Questions 4 1

L-4/T-l/EEE Date: 07/03/2012
BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA

L-41T-1 B. Sc. Engineering Examinations 2010-2011
Sub: EEE 495 (Real Time Computer System)
Full Marks: 210 Time: 3 Hours

The figures in the margin indicate full marks.
USE SEP ARA TE SCRIPTS FOR EACH SECTION
SECTION -A
There are FOUR questions in this section. Answer any THREE.
1. (a) What are the differences between soft, firm and hard real time systems? Explain with
examples. (9)
(b) Draw and explain the structure of a real time system. (10)
(c) What are the advantages of RISC architecture over CISC architecture? (6)
(d) Name some traditional performance measures. Why are these measures not suitable
for evaluating the performances of real time systems? (10)
2. (a) Calculate the performability for the operation of driving a car from a place to another.
Time constraints will be neglected. The ultimate result may be one of the following: (17)
(i) Not hitting anything and reaching the destination.
(ii) Hitting something but reaching the destination.
(iii) Being hitby some other vehicle but reaching the destination.
(iv) Not reaching the destination.
(b) Briefly explain: (i) Major Minor Cycles (ii) Foreground/Background Systems. (8)
(c) What are the differences between processes and threads? Discuss thread models. (4+6=10)
3. (a) Explain the particle swarm optimization algorithm in brief. (12)

(b) Explain with example why strict alternation is not suitable for Interprocess
Communication. Write down and explain Peterson's solution for IPC. (15)
(c) How can a mutex be implemented by TSL instruction? How does it differ from the
implementation of common TSL based lock for mutual exclusion? (8)
4. (a) What are the advantages and disadvantages of Warnier-Orr notation? (8)
(b) A sequential circuit has two inputs O)} and 0)2 and an output z. Its function is to
compare the input sequences of the two inputs. If 0) I == 0)2 during any four consecutive
clock cycles, the circuit produces z = 1; otherwise, z = O. For example (27)

Contd P/2
Derive the state diagram for an FSA. Construct the state assignment table and draw a
suitable circuit that realizes the FSA using D flip-flops.
SECTION-B
5. (a) Write source code in any programming language (preferably C) to implement a ring
buffer data structure, using startytr and stop ytr pointers. Keep provision of
distinguishing empty buffer and full buffer and implement enque, deque operations. (15)
(b) Discuss necessary conditions for deadlock. Describe the Banker's algorithm with
example and explain how it can be used to avoid deadlock. (20)
6. (a) Write a real time operating system? Give four reasons why Microsoft Windows 7
should not be considered as a real time Operating system. (15)

(b) Using compiler optimization techniques Minimize the code fragments. Mention the
name of the techniques that have been employed by you. (20)

a. for (j = 0; j <= 30; j++) {
for (k = 0; k <= 30; k++)
x[j] [k] = y[j] [k] + z[j] [k]; }
b. function fact (int n) {
if (n= =1) return n;
else return n*fact (n-l); }
7. (a) Consider the following set of four tasks: (15)

Task Execution Time Period
T1 1 8
T2 2 5
T3 2 10
Comment if T 1, T 2 T 3 are RM schedulable. Comment on their RM schedulability if the
execution time for each task is doubled.

Contd P/3
.,
..
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EEE 495
Contd ... Q. No.7
(b) Describe different CPU scheduling algorithms and what are the criteria to choose one
scheduling algorithm over another? Define waiting time, tum around tome and
throughput. (20)
8. (a) Consider the following code sample: (15)

Load A, #40 load 40 in A
Move B, A copy A in B
ADD B, #20 add 20 to B
STORE Ox573, B store B into RAM
Explain how this code segment will be executed with and without instruction pipelining.
(b) Consider the following system which is scheduled by Round Robin Algorithm. (20)
Process CPU Time (ms) Arrival Time (ms)
PI 3 0
P2 2 2
P3 9 6
P4 10 9
P5 1 1
P6 6 4
Calculate the average turn-around time considering

(i) time quanta = 4 ms
(ii) time quanta = 20 ms
Comment on the tum-around time obtained from these different time quanta.
L-4/T-l/EEE Date: 07/03/2012
L-4/T-1 B. Sc. Engineering Examinations 2010-2011
Sub: EEE 455 (Compound Semiconductor and Hetero-junction Devices)
Full Marks: 210 Time: .3 Hours

SECTION -A
There are FOUR questions in this Section. Answer any THREE. .
1. (a:)Discuss the design limitations of BJT and explain how these limitations can be
minimized in HBT. (10)

(b) With the help of energy-band diagram and electric field profile, explain Kirk effect
in BJT. How Kirk effect is minimized in HBT? (17)

(c) Compare abrupt and graded junction HBTs in terms of performance parameters. (08)
2. (a) Draw the structure, energy-band diagram and doping profile of a typical (15)
(i) Delta doped (ii) Single quantum well (iii) inverted MOS HEMT ..
(b) What is the advantage of delta doping? (03)

(c) In a GaAs/AlGaAs normal HEMT, the modulation doping is performed by putting a
donor density of2 x 1018 cm-3 over 100X of AlGaAs. Assume that all donors spill their
electrons into the GaAs region. (17)

(i) Find the first two eigen energies using Airy function approximation.
(ii) If all electrons go into the first subband of the triangular quantum well,
calculate the position of the Fermi level at 300 K.
3. (a) Mention how velocity saturation effect at high electric field is accounted in the I-V
characteristics ofMESFET. (10)

(b) Compare the performance of a P-n junction with Schottky contact. (7)
(c) In a W-n Si MESFET, the doping concentration ofSi is 1018 cm-3• (18)
(i) Calculate the tunneling probability of the electrons with energies near the
conduction band using triangular potential barrier approximation.
(ii) What will be the tunneling probability if doping density is increased to
1020 cm-3?
Give that ~m = 4.55 eV, XSi = 4.01 eV
Contd P/2
=2=
EEE 455
4. (a) What is staggered, straddling and broken gap heterojunction? Give one example of
~~. ~
(b) What is uniaxial and biaxial strain? Why mobility enhancement occurs in strained Si
nMOSFETs? (14)
(c) Discuss the effect of strain on (i) UTB SOl MOSFET (ii) FinFET (iii) Ge pMOSFET
(iv) GaAs nMOSFET. (12)
SECTION -B
Question No.5 is compulsory. Answer any two questions from question no. 6 to
question no. 8. All the necessary data are given in Table 1.
5. Draw band diagram of the device in figure 5 along AA/ and BB/ directions. Work
function of gold is 5.1 eV. (45)
6. (a) How the energy gap of GaAsl-xPx is varied with mole fraction? Sketch the
corresponding E-k diagram and discuss its light emission efficiency. (12)
(b) For a particular application you need light with wave-length of 1300 nm. The
available material is GaAs, and lnAs. Design a quantum wire with GaAs- Inx Gal-xAs
material system such that the wire is perfectly lattice matched with InP substrate and the
light emitted from the wire can be used in long haul optical communication at 1300 nm. (18)
7. (a) What is charge neutrality level? Why metals are used in electronic circuits? Explain
the effect of interface states on metal-semiconductor junction. (15)

(b) What is Richardson constant? Assuming that the electrons follow the Maxwell-
Boltzmann distribution, derive current-voltage relationship of a Schottky contact. (15)
8. (a) What is effective mass? What are the differences among m*dos, m*cr, m*z, m*t, m*hh,
(10)
(b) Define amphoteric doping. What is "In-rich" and "Ga-rich" GaAs? (5)
(c) Calculate the donor and acceptor level energies in GaAs and Si. (15)
Au Zr02. Au
AI203
Gao.5~lo.47As
Intrinsic GaAs
I
B )it
Q,
~{
Figure 5
Table 1
Material a (nrn) Eg (eY) rn*c rn*hh "f(eY)

GaAs 0.56533 1.42 rn* dos=0.067rna 0.45 rna 4.07
AlAs 0.56611 2.229 rn*,=0.97 rna, 0.76 rna 3.5
rn*t=0.22 rna
InAs 0.60584 0.36 rn* dos=0.027 rna 0.4 rna 4.9
InP 0.58686 1.35 rn*dos=O.077 rna 0.64 rna
,
Si 0.5431 1.12 rn*)=0.98 rna, 0.49 rna 4.01
rn*t=0.19 rna
2r02 5 2.5
Ah03 9 1.0
L-4/T -lIEEE Date: 29/02/2012
L-4/T-l B. Sc. Engineering Examinations 2010-2011
Sub: EEE 453 (VLSI-I)

USE SEPARATE SCRIPTS FOR EACH SECTION
SECTION -A
There are FOUR questions in this Section. Answer any THREE.
1. (a) In a table show clearly the influence of scaling on L, W, tox, VDD,Vth, NA and MOS
device characteristics p, Ids, R, C, gate delay 't, clock frequency f, dynamic power
dissipation per gate P, chip area A, power density and current density. Assume that
constant field scaling is adopted. [ The symbols have their usual meanings.] (20)
(b) Assume that mobility of electrons is thrice that of holes. Show the schematic diagram
at transistor level of a unit inverter driving a similar inverter. Clearly mark the aspect
ratio of each transistor. What will be the propagation delay if the input to the first inverter
is falling? For this scenario, show the equivalent switch level RC models. Assume that C
is the gate capacitance of a unit NMOS transistor. Diffusion capacitance at source or
drain of a unit NMOS transistor is also C. The unit NMOS transistor can be assumed to
have effective resistance R. (15)
2. (a) For the following figure, calculate the diffusion parasitic capacitance of transistor 1,
Cdb1when the drain is at 0 V and at VDD= 1.8 V. Assume the substrate is grounded. The
transistor characteristics are CJ = 0.98 fF/~m2, MJ = 0.36, CJSW = 0.22 fF/~m,
CJSWG = 0.33 fF/~m, MJSW = 0.10, MJSWG = 0.12 and 'Vo = 0.75 V at room
temperature. Assume A = 50 nm. The symbols have their usual meanings. (18)
Contd P/2
...
=2=
EEE 453
Contd ... Q. NO.2
(b) Show that fall time of an inverter is given by (17)
'tf= 2eL [n-o.l +!In(19-20n)]

PnVDD(1-n) I-n 2
n=~
v:
VDD
The symbols have their usual meanings.
3. (a) Show that short circuit dissipation of an inverter is given by, (20)
where Vtr = -Vtp = Vt

trf= tr = tf
tp = pulse width
The symbols have their usual meanings.
(b) A digital system in a 1.2 V, 100 nm process has 200 million transistors, of which 25
million are in logic gates and the remainder in memory arrays. The average logic
transistor width is 1211,and the average memory transistor width is 411,.The process has
two threshold voltages and two oxide thicknesses. Subthreshold leakage for OFF devices
is 25 nA/~m for low threshold devices and 0.02 nA/~m for high threshold devices. Gate
leakage is 4 nA/~m for thin oxides and 0.002 nA/~m for thick oxides. Memories use low
leakage devices everywhere. Logic uses low leakage devices in all but 15% of the paths
that are most critical for performance. Diode leakage is negligible. Estimate the static
power consumption. How would the power consumption change if the low leakage
devices were not available? (15)
4. (a) Show the process sequence of fabricating an inverter on a NWELL CMOS process.
Clearly show the mask used and the device cross-sectional diagram after each step. (18)
(b) Show in a diagram, the origin and model of CMOS latch up in a NWELL process.
How latch up can be prevented? (17)
SECTION -B
5. (a) Design an 8-bit carry select adder such that the total propagation delay is minimized.
Assume delay of each adder cell is 4 nSec. and propagation delay of the multiplexer is
2 nSec. Derive any equation used in your calculation, and slow the schematic diagram of
the adder circuit. Compare the delay of the circuit with that of a ripple carry adder. (17)
Contd P/3
.: "
.. '.'"
=3=
EEE 453
Contd ... Q. NO.5
(b) Show the circuit diagram of the square version of a 4 x 4 bit array multiplier. Explain
the operation of the circuit. (18)
6. (a) (i) Show the circuit diagram of a 2 x 2 SRAM array which uses 6-transistor memory
cell as basic storage cell. Clearly show the row select, column select, pre-charge and
sense signal in your circuit.
(ii) Explain how the READ and WRITE operation are performed showing the second
row and first column cell as an example.
(iii) Explain how sense amplifier reduces the READ time of the cell. (20)
(b) A 4-bit datapath consists of register, ALU and a shifter. Show two possible bus
architectures of the system such that an addition operation of two operand stored in the
register and storing the result back in the register can be computed in atmost two clock
cycles. (15)
7. (a) Using a structured design approach, develop a bus arbitration logic for n-line bus such
that access is given to the highest priority line. If priority is given according to ascending
order (line N highest priority) draw the circuit and stick diagram of a basic leaf cell. (17)
(b) Draw the Schematic diagram at transistor level of a CMOS PLA to implement the
functions. (18)
- -
Zl = a.b +c.d
Z2 = a.b +c.d
8. (a) Draw and explain the operation of a (i) tri-state pad, (ii) bidirectional pad with the
help of a truth table. (20)

(b) In the figure shown below transistor 1 is stuck opens (01), Find all the two pattern test
vectors that will detect the fault. (15)
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C'
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L-4/T-lIEEE Date: 10/0112015
L-4/T -1 B. Sc. Engineering Examinations 2012-2013
Sub: EEE 453 (VLSI Design)
Full Marks : 210 Time: 3 Hours .

SECTION -A
If you feel there is any ambiguity make reasonable assumptions and state it in your solution.
1. (a) Show the process sequence of fabricating the following circuit (NMOS inverter with a
resistance load) in NEWLL CMOS process. You have the freedom to design the
resistance either from polysilicon layer or from the N+diff/P+diff layer. (20)
(b) You have to design a four line gray code to binary code converter in a structured way.
The truth table is shown in Fig. for Q. No. l(b). (15)

(i) Show the schematic diagram of the design using a suitable leaf cell.
(ii) Draw the layout diagram of the leaf cell in such a way that the VDD, GND and the
intermediate signals are automatically connected when the leaf cells are butted together.
Gray Code Binary Code

G3 G2 G1 GO A3 A2 A1 AO
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 .1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1.
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 a a
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 .1 1
Contd P/2
=2=
EEE 453
2. (a) Show transistor level NOR-NOR PLA implementation of a digital circuit which has
three output (Z1, Z2 and Z3) as follows: (15)
- - - -
Zl = abc + bc ; Zz = abc + bc ; Z3= b + abc
(b) (i) Show the circuit diagram of a 2 x 2 SRAM array which uses 6-transistor memory
cell as basic storage cell. Clearly show the row select, column select, pre-charge and
sense signal in your circuit. (20)
(ii) Explain how the READ and WRITE operations are performed showing the first row
and second column cell as an example.
(iii) Explain how sense amplifier reduces the READ time of the cell.
3. (a) Design a 8-bit Carry Select Adder such that the delay becomes minimum. Assume
that the delay through one adder cell is 500 pS and the propagation delay through the
multiplexer is 250 ps. Derive any equation used in your calculation and show the
schematic diagram of the adder circuit. Compare the delay of this adder with that of a
ripple carry adder. (18)
(b) (i) Show the schematic diagram of a 4 x 4 bit array multiplier designed in a structured
way. Identify the basic cell of the multiplier and explain the operation of the circuit.
Show the critical path of the signal which will experience the longest delay.
(ii) Design a general purpose I/O pad having ESD protection circuit. Explain the
operation of your circuit. (17)
4. (a) (i) Show the circuit diagram and device cross-sectional diagram of a one transistor
trench capacitor DRAM Cell. By showing the timing diagram explain the READ and
WRITE operation of the circuit. (20)
(ii) To fully tum on the access MOSFET, word line of the above DRAM -is driven to
VOD+Vtn, The memory bit capacitance Cmbitis 20 fF and a '1' is stored in the capacitance
by charging it to full VDD = IV. The bit line capacitance is 100 tF and before RE~D
operation the bit line is pre..:charged to VDD/2. What voltage will be obtained in the bit
line during the read operation?
(b) In the CMOS circuit shown in Fig. for Q. No. 4(b), a bridging fault occurs between
line fl and n. Explain how you will detect the fault and which test vector will you apply? (15)
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Contd P/3
"
=3=
EEE 453
SECTION-B
If you feel there is any ambiguity make reasonable assumptions and state it in your solution.
5. (a) (i) Show that the threshold voltage of a MbS transistor with body bias Vsb can be
approximated as Vt = Vto + y~Vsb , where the symbols have their usual meanings. (17)
(ii) When used as a pass transistor, explain why a PMOS transistor passes good '}' and'
bad '0'. Assume Vtp = -1 V, Voo = 5V, Yin (H) = 5V, Yin (L) = OV.
(b) (i) An NMOS inverter with NMOS enhancement load is designed such that the output
voltage becomes 0.2V when the input voltage is high (5V). Calculate the aspect ratio of
the inverter. The following data are given:' IlnCox = 30 IlAN2, Vto = IV, VDD = 5v,
y = 0.5. Assume, the body of the transistors are connected with ground. (18)
(ii) What would be the output voltage if the input voltage is 0.2V?
6. (a) Show that the dynamic power dissipation of a CMOS inverter varies directly with
square of the power supply voltage whereas the delay of the circuit varies inversely with
the power supply voltage. (15)

(b) The output of a 3 input NAND gate drives 15 similar NAND gates. Calculate .the
worst case rise time and fall time of the NAND gate. The following data for the gate are
given: IlnCox= 120 IlNV2, IlpCox = 40 IlA/V2, Vton = 1V, Vtop = -1 V, VDD= 5V, Y = 0.5, .
wn = lO!-lm, wp = 20 !-lm, Ln = Lp = I !-lm, source/drain length = 5!-lm, gate oxide

2 2
capacitance = 20 tF/!-lm , source drain diffusion capacitance = 10 fF/!-lm . Assume the
body of NMOS transistor is connected with GND and the body of PMOS transistor is
connected with Voo. (20)
7. (a) What is latch-up? A CMOS integrated circuit is designed on a PWELL process. Show
the possible latch-up circuit and explain how latch-up could be induced. Explain the
fabrication measures and the design measures that should be taken to prevent latch-up in
CMOS circuits. (15)

(b) An inv~rter buffer chain is designed in a 5V CMOS process so that each stage is four
times larger than the previous stage. The first stage of the chain is designed with a
minimum size inverter gate, which has an input (Cin) and output (Cout) capacitances of
0.1 pF and 0.2 pF, respectively. The chain drives 2000 minimum sized basic gates. Calculate
the delay through the chain. Assume r rp

n= =2
5 2
x 10- NV for the minimum size inverter.
If f = 100 MHz calculate the dynamic power consumed by the buffer chain circuit. (20)
Contd P/4
=4=
EEE 453
8. (a) A 3 : 2 priority encoder is defined as follows (20)
YI =AO; Al
(i) Sketch the transistor level schematics of the logic functions Yo and Y I, each of which
is implemented in a single CMOS complex logic gate. Assume that both true and
complementary versions of the inputs are available.
(ii) If the above logic functions are to be implemented with worst case equal rise and fall
times, determine the relative width of the PMOS transistors with respect to the NMOS
transistors for both of the logic gates. Assume Iln = 3 /lp and gate length of NMOS and
PMO~ transistors are equal to the minimum allowable in the process (Ln == Lp = Lmin).
(b) Sketch the transistor level schematic for the logic functions of Q. 8(a) in (i) pseudo
NMOS, (ii) footed dynamic CMOS, and (iii) domino CMOS. (15)
L-4/T-lIEEE Date: 15/0112015
BANGLADESH UNIYERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA
L-4fT-l B. Sc. Engineering Examinations 2012-2013
Sub :EEE 455 (Compound Semiconductor and Hetero-Junction Devices)
Full Marks : 210 Time: 3 Hours

~E~TION-A
There are FOUR questions in this section. Answe~ any THREE.
Symbols have their usual meanings.
1. (a) Why is lattice constant of semiconductor important for heterostructured device

fabrication? Discuss the effect of biaxial strain on valance band structure and conduction
mechanism. (20)
(b) Compare low field mobility of polar and non-polar semiconductors. How effective
temperature of carrier differs to that of lattice temperature? Explain differential negative
resistance in some semiconductors. (15)
/
2. (a) Discuss the effect of InAs and GaAs thin film growth on InP substrates in terms of
structure and electronic properties. Estimate the bandgap of InxGal_xAs lattice matched
to InP. Necessary data are given in Table for Q~2(a). (20) .

Materials lattice constant (A) .. Eg (eY)
\
,GaAs 5.6533 1.43

InAs 6.0584 0.36
InP 5.8686 1.35
,
(b) Why are optical absorption of amorphous, crystalline and polycrystalline

semiconductors different? Explain experimental procedure to estimate bandgap of
direct/indirect semiconductors. (15)
3. (a). What is superlattice structure? How is it possible to modifyopto~electronicproperties

in such structures? Explain with necessary diagrams. Discuss the advantages and
disadvantages of graded heterostructures. - (20)
(b) What are the assumptions made in Anderson's model? Determine L1Ec, L1Ey and Ybi
for an idealn-Gefp-GaAs heterojunction. (15)

Given that:
Electron affinity of Ge = 4.13 eY
Electron affinity of GaAs = 4.07 eY
13 3
nj = 2.5 x 10 fcrn (for Ge)
16 3
Nd,= 1.2 x 10 fcm
16 3
Na = 1 x 10 fcm
Contd Pf2
=2=
EEE 455.
4. (a) Write the conditions necessary to form rectifying contacts ill metal-semiconductor
junctions. What is. Fermi levei pinning? Explain a method to estimate doping
concentr~tion from Schottky junction. (20)
. (b) Sketch the energy-band diagram of an abrupt Alo.3Gao.7As/GaA~ heterojunction for: (15)
(i) N+ AIGaAs, intrinsic GaAs
.(ii) P+-AIGaAs, n GaAs
. 2
Assume Eg = 1.85 eV for Alo.3Gao.7As and L\Ec ="3 L\Eg
.(Make necessary assumptions-if needed).
SECTION -B
. .
5. (a) Using Gummel-Poon model, derive the equation for the electron current density in the
base of an npn transistor biased in the active mode. What is emitter Gummel number? (20)
13 13
(b) In the Ebers-Moll model, assume Up = 0.98, IEs= 10- A and Ics = 5 x 10- A at
T = 300 OK. Calculate Ic for Vcs =12 V andVSE == 0.4 V. (15)
6. (a) Draw thesm~ll-signal equivalent circuit of a JFETand derive the expression for
maximum cut-off frequency considering simplified equivalent circuit. (18)
_(b) Calculate the small signal output resistance at the drain terminal due to channel length
modulation effects. Consider an n-channel depletion mode GaAs JFET with a channel
l 15 -3'
dopmg ofNd == 3 x 10 em . Calculate tds for the case when Vos changes from Vos (1) =
Vos (sat) + 2.0 to Vos (2) = Vos (sat) + 2.5. Assume L = 10 J.lmand Ip1= 4.0 rnA. (17)
7. (a) Draw the energy band diagrams for zero, negative and positive voltage biases in a .
AIGaAs-GaAs HEMT. (Only energy band diagrams are required). , (10)
(b) With quantum well structure describe the operation ofHEMT. (10) J
'(c) In a HEMT structure, consider an abrupt

n-Alo.3Gao.7As - intrinsic GaAs
18 3
heterojunction. The n-AIGaAs is doped to Nd = 2 x 19 cm- . The Schottky barrier
weight is. 0.85 V and the heterojunction conduction band edge discontinuity is 0.22 eV.
Determine the thickness of AIGaAs layer so that Vaff = -0.3 V. The relative dielectric
constant of Alo.3Gao.7As is 12.2 and GaAs is 13.1. (15)
8. (a) What is bandgap narrowing? Discuss the effects of high emitter doping on the
characteristics of Bipolar Junction Transistor. (15)
(b) The following currents are measured in a uniformly doped npn bipolar transistor: (20)
InE = 1.20 rnA IpE = 0.10~A
InC= 1.18 rnA IR = 0.20 rnA
IG = 0.001 rnA IpCo= 0.001 rnA
Determine (i) u (ii) y (iii) aT (iv) 8 and (v) ~, where the symbols have their usu,al
meamng.
IA(I~lIEEE Date: 01/0812015
BANGLADESH UKJVER~j IY OF ENGINEERING AND TECHNOLOGY, DHAKA
L-4"T-1 B. Sc, Ellb~nc~'l"ing
ExaminatiOns 2013-2014
Sub; EEE 453 (VLSI -!)

Full Marb: 210 Time; 3 Hours
USE SEPAR" f'E SCRIPTS FOR EACH SECTION
The tlgures in the margin Indicate full marks.
SF,CTION -A
TItere are FOl'R questions in thi, ,echon, Answer any THREE.
(a) ~how the process seqUL'IlC~

offabricatmg an lllvelter on a NWELL CMOS process.
Clearly show the ma,k u,ed and the devld cro,,-,ectlonal diagram after each step. (20)
(b) Two reSIStors each haVing 4 nnn resistors arC to be matched III a layout. The sheet
re"stance "arie, llncarly os a runctLon "f position Betv,een mlerdlgitated layout and
common centroid la/nut which one will you prefer for malching? JustilY your answer
wllh numeneal valu,". (15)
(a) Sllo\\ in " dlOgram the origin and model of CMOS latch up in a PWELL proccss.
How latch up ~an be prevented? (15)

(b) COllSlderde,ignmg a control circuit that wiil swap tho contents of two regi.1e" R,
and R" "hL'Il the control sIgnal w goes to HIGH. You can use another register R) to
tempoTariIy holJ the value of ml" of lhe registers whose value 'will be ~wapped. Draw
Ihe' ,tale diagram. state table and ,tate aSSigned table of the Moore lype Flnl;e Stale
Machme (FSM) and lhe circuit diagram of the <x>ntTol1L'r (20)
3. (a) Usmg a 'trueturo:! design approach. develop a bus arbitration lOgiCfor n-line bus
,ueh lhat acces, lS giyen to the highe<t pnority line, If priority is giv~n according to
ase~l1dingoroer (line N lngh.st priority) draw the CirCUItand stLck diagram of a ba..lc
I~fcell. (29)
(h) Draw the gale level circuit for lmplem"nting the function f ~ A,B+A.B uSlIlgNOT,
A"lD and OR gates. Suppose lhat you WillItto detect sluck at I faults al alillie primary
mputs "nd the primary output Derive the corre'ponding minimum ser of test vectors, (15)
4. (a) In the FIg. for Q. 4{a}, trunsistor I is Sluck open (OL)' Fmd all the two pattern tcst
\'Cctor<that wlll derect the faull. (10)
Cont<!... , "P/2
•
=2 =
EEE 4531EEE
Contd." Q. No. 4(a)
0, ",-I 3
-, ..
(h) Show the NOR.:-IOR implementation of a PLA CirCUltwhich will provide the
followlIlg outputs 1\1CMOS 1<1~~e, (18)
£, =a.b +cd
,
Z,=ub
(e) Dr"", the ,ch~"ITI.licdiagram of a scannahle D f1ip.f1op bmlt from inverters and
CMOS lransm",ion gates (7)
SECTION -B
There are }'OUR queslions in this section Answer any THREE,
5. (a) for tlle conn~ClioDof the NMO~ fill'" Iron,i,tor shown in Fig. for Q. 5(a) find lhe
output voltage V,"", V"Q "nd V""'J. Assume V'" ~ lV, Y~ 0.5 vv, , (15)
Contd . .. PO
l:EE 453/EFE
Contd.,. Q. No. 5(a)
(b) WIth neeeS3",)' ~gures explain what happens to switohing pomts of tranSlstor
eharactemtie, cur\'e and n01se margins NML ond mfH when P,!P, is increased in a
CMOS inverter pair, As,ume that the lOgicle,eJs are selected at the unity gain points of
the DC lranster charaOlerl,tlcs eur"e to maximi~e the noise margin, (10)

(c) 1f tho dala IS completely random for 0 4 input OR gate huilt out of 2 input KOR and
2 mpul NAND gate.s, find the adivity foetor. Al,o find the dynamic powet disSlpmed in
the gate" if tlle clock frequency i, 1 GHz, thc ,upply voltage is 1.2 V and tho load
capacilance is 5 p~ (10)
G, (a) A 3 lllput CMOS NOR gar. is dnvmg h number of ,imilar gate•. Draw the ",hematic
diagram of the NOR gale at MOS tramistor leve!. A,sume that mobility of e1eetrons lS
thriec lhe mobilily of holes. Show the aspecl ratio of the transistors to achieve equal rise
and fan resi,tance 10that of a unit inv~-rterIn the wor<t case. Show the SWItchlevel RC
model of the NOR gato and calculate the nsing propagotion delay (t"o.-l, falling
propagation delay (t,,,), ond falling conlamination delay (",,). (20)
(b) Derive the exp,esswn for the short ~ircuit dissipation of a CMOS inverl~r. (15)
7 (a) A buffer challl IS 10he deSign"" for &clock signal which will drive 1500 logic gates,
'Il,e input C"I'acltance of each of the loic gates is 8 pF and the output capocitanee is 3
pl'. 111eminimum SIZedinverte, III lhc process has an input capacitance of 4 pf and
output capacilance of 2 pF &;,doutput capacltancc of 2 pF. Find the size (n) and the
number of ,tages (m) "f tJ,e requued buff., chain. You have to derive the equations
used in your calculatinn first. (20)

(b) .•..4 bit dala path consis\>;of regtster, ALU and 0 shifler Show two possible bUli
srdutectures of the 'y<tem ,such thal an addition operation of two operands ,tored in the
register and storing lhe rosult back in the register can be computed in at most two' clock
cycles. (15)
Contd ...... 1'/4

EEE 453/EEE
R (aJ (Jl Show (he ""cui! dwgram of a 2x2 SRAM array which uses 6 transistors memory
cell as b",i" ,torage cell. Clearly show {he row select. column select, pre-charge
and sense "1,'11"1

in yuur C!feult. (20)
(11) Explain how READ and WRITE operation arc p",formed showrng the first row
and secom! column cell as an c~ample_
(iii) Explam how scme amplifier reducts the READ hme of the "ell.
(b) Draw {he ,electlOn and control of a 4x4 register array that can select any register lor
READ or WRlTE, eM select two regISters slfllultancously and can READ the contents
of a single rcgi'ter to both p., and B bllies of a two bu' archItecture system, Briefly
eKpbin thc OperatlOn, (15)

L-4ff-liEEE Date: 0510812015
IlAKGLADESII UNIVERSITY OF ENGINEERNO AND TECHNOLOGY, DHAKA
L.4iT -I Il. Sc. Engmeering ExamInations 2013-2014
Sub' EEE 455 (Compound Semloonductor and Hetero-Junctlon Devices)
Full Marks; 210 Time. 3 Hours

The ligures 111the marg1ll1lldlC"tefull marks.
SECTION-A
There are FOuR questions in this ,c,<,tion.Answer any THRE};,
t. Somc pm"" on the band stmcmre of OaA., shown in Fig. for Q, No, I are reported 111
Table tor Q, No, I. Find the fo]Jowing- (35)
(a) Conducti\ ity effectivc rna'S and dcn<it)' of Slate dfective rna", for electron.
(b) He"\'}'. light .ud sp!lt-offhoie dTc,ti\'c rna,. in [1,0, OJdireclion.
(e) Hea\'y, light and spIn-off hole effectlve mass in [1, I, I) direction.
(d) fland~ar and C!lmment whether the matenalla direct or indueCl band gap materlal.
(e) Split-olfenergy(E",).
Make necc",ary ""LLmptions
2 (a) Supposc" lhin layer of G~,I,".,As,!]_,sandwich"'" between two AlAs layer forms
a Quantum Well, The structure only allows rcd hgbt (-660 nm) to P'"'s through iI, in the
\'j;;,ble spectmm. The lattice constant of unstrainoo GalnAs'P is f!lund to be 5.7313 A.
Abo, thc fiL't Eigen energy for electron 111the wdl 10 0.23 eV higher than the
conduelion hand edge and the fust "'gen energy for hole m the well is 0,1 eV lower than
tile valance band edge, Using .ddiuon.l information from table for Q, No. 2(.), fmd- (25)
(1) Valuc"fxandy
(11) CnHeal thlckness of GalnAs l' to match its I.ttlee p",mneter with the substrnle.
To estimate parameters for O"lnAs P you may use the followmg formnla-
parameter b(x, y ) ~ (I - x) y bl,,; + (I - .,Xl - Y)b {M'+ xybGm + x(I - y)bGoP
(b) Brielly discuss 'the significance of I.thee mlSIll.lch in s~cond\lcror Junctions,

Explain how i{ ean he re,olved (to)
3, (a) Dmw En"'-g)'band di"gram of the following metal ,rnticonductor junctions and
mention "hethc'r i\ i\ Ohmic or Scho!tky (20)
(i) Al (1 HI) OnlOpofn_Ga ••."
(ii) Cu(lll)ontopofn.GaA<,
(iii) Ag (Ill), on top ofp - GaAs,
(iv) Au(lOO)ontopofp-GaAs,
if Schottky, then ai,,, find th~ barrier height.
Contd. . .. P!2
\
=2=
EEE 455/EEE
Conld .., Q. No. 3(a}
,"'I, Co, Ag and Au have ,,",or!<[unction, 406 eV, 4.98 eY, 4.74 eY and 5.47 eV
re'pc,li,dy. GaAs has electrOn affinity of 4.07 eV and bandgap of 1.519 eV.
(b) Fig for Q, No, 3(b) show, ille cross section of. HEMT. Draw the approxunate band
dlagram of the structure along the direcllon AA' using Anderwn', rule. For necessary
pardmclcr> see Table tor Q. No, 2(0) and apply Vegard's Law whenever nec""sary. (15)
4 Write rulsWers10thc short quesllOns below; (35)

(a) Whm huppL'nsto emitter injection efficiency if there IS a spike in the energy band
di"gram in thc emitter-base junctIOn,
(b) Suggest a solutIOnto prevent dopant dJffuswn from base for HBT.
(c) :VlcnlionOlleadvanlage and one di,advantage ofbalhslic injection in HBT.
(d) ]Jaw base lesi,tancc and base tranSlI llme in reduced in HBP What lS the problem
or the 'methods,
(el \Vhat i, avalanohe hreak down'! How Canil be reduced?
(I) Ho,,",smuration offset is nllnimized 10HB1'~
(g) \\'11a!plOblem a widc hand gap collector can p",e in HBP Whst is the solution?
S}:CTlON -B
There are FOUR question, ,n Ih" sectIOn.Answer any THREE.
5 (a) Prove thaI. for a JFET, the dram current ISgiven by, (23)
I-krc, lhe symbols h;,vetheir u,ual moanings

(b) The n+p JunctiOll of a umfonnly doped ,,;licon p'charmel JFET at T~ 300 'K has a
doping concentrmiOD of N,i~ 5 x to" CIlI-, and N, = 5 x' 10" cm-', The mclollurgical
<h.nnd thickness lS a = 0,50 "'Ill, Delormine the intemal pinch-off voltage and the
]Jll1,h-off,()ll~ge of lhe JFET. (12)
6, (aJ Wnat is HUMP Prove lhat, for an nP hetcrojuncl1on, the expression of total
,kplolion width LS given by, (20)
, W.,'j2Eo"p('Vdn+N,pYV,,)S"--
dV"N,p("" NJ"+Ep Nap)
Here, the symh~)h havc (heir usualll1~aning,

Contd ... " .... , Pi3
~3~
EEE 455!EEE
(;onld ... Q. No.6
(b) Consider an N-Alo ,Ga., ,As - intrinsic GaAs abrupt heterojunelion struclure which
can bc n,ed as HEMf. Assume that the AlGaAs is doped w;lh Nd - 3' 10" em-' and
h", a thickness of 35011.. LeI ~B = 0.89V.,';Ec = 0,24 eV, Eh = 12,2 iSo' Determine the
\ alue ofthrc,hold voltage al 300 K t~..-nperature. (15)
7, (a) DLSeu," lhe etfect of high lllJeclion and bandgap narrowing on lhe charaeleristics of
bipolar Junctinn lransiwlT. (18)

(h) Consider a sllicon npn tlansislOr at T = 300 K has the fonowing parameters gi'eI1 in
t"b1c for Q. No 7(b), C"lculale the emtlter-to-collector transit !tme and the cmtoff
frequency of" bipLllar tran,i.tDr. (17)

Table for Q. r;"o. 7(b)
[ IE-lmA Cj, I pF [
X"~0.5]lm D, ~ 25 em',.-s
4-24]l11l r,~20n
C,~O,tpF c,~O,lpF
IJ-IOO v,~ 10' emiS
J
8. ConSld~T an N-AI"Gao,As and p-GaA:> heteroJuncnon witb N'N ~ 2 x 10" i;m- and
N," - 6 x 10" em _l has the follOWing parameters given in table fur Q. NO.8, (35)
(a) Sketch tJ,e band d,agram "11th proper dlm~'l\.;on.

(b) 1I0w much does thc eonductl<ln band spike eXlend abovc the conduction band edge
m the qllilsi-neutl1l1 region on the p-Sldc (i.e. where x>.' p)?
(c) How large a reverse bia, must be applLed to this jllllction to move the spike below
the conduetion band edge in th~ qua',i-neutrol re"rJon on the p-side?
(d) Gcade the intc"rraee o~ 'ih'c N_,ide over the mmimum ",:idth needed to ehmmate the
spike in tbe cOnduetlOn band. Over what distance do you bave to grade the
compo,it;Lln? Let tbe gtadi~g g~ from E,N to E".

Table for Q. No.8
Parameter; Al"GaooAs GoA,
Electron Affinily (eV)

c
3.63 ,m
;-.nergy gop (eV) 1.92 1.42
J
ConduetlOn band density of states, N, (cm- ) 5 x JO" 4.7"10"
Vdence band denSLly ofstales. N" (em ') 8xlO'" 7xlO"
Relatlvc dielectric comtanl.', 11,6 12,9
-_._-_ ....--------_ .._-_ ...-----_ ..

'00 ,
<l~O> <111>
W~'<l''<l',l1lr
fIo"y n.l••
lightho~
Split.,ff band
!,,,,,,,,(,V) E",cg}'('V)
(1 •.1: ",) '""M('V) ~-""" ('V)
(om' 1)
,.,
)Cood",",n (Htav; hoi,
~
.{UJl975Jl
(Ugl>t ,010 """d)
.0 H7D17
(SpH' ",,::,,
hoi,,,,,,,,
.046J!:!J
U-!332 0 3m,1I.)!]' I 6195J
1.'1)65 .0.DGlm154 .0 050116 -<l114549
".'9]60 101"" '9'"
.j'~13~"10 .5,'9139>lD -<)116526
"u u 1.'''4]6
1 49314 .""133111 -<lO'691<5i _u l6G1S5
" )7<lI.O,O
163116 ~, OI4G1J' -"173193 _0.4J95')
(OJ41,00)
fm, ,.."", "'''00 dec"''''' DOS ,If",""" mm - V 9'm,m~

i,~~(f,-2f,+t,J/(h) '
.,
f, = (1,-21,+f,1I(h)
'
C"du,ti,i., ,If"""" (' 'r'
on=; - J ;;;; +;.;
, S)'mool, ";0 """ "".1 "".rung,

I,"' (1,-2f, +1.)/(h )
..,
lobI, lw p, ~" 1
G.A, AlA, ,~ G.'

, .,.A 'i.65325
j 519
5 6611
3.099
5.8697
1.4236
6.0583
0.417
5.4505
2.26
e ~,
., m, 0.15 0.0795 0.026 0.37
4.07
" '" " H
Tabl. forO. No. 2(a}
IA
,
A'
TO TO
Itt lno...,GI0"7As n+ Ino.s3G""...,As
••••
lno.pAla, •• A. Ao
Ao
lno.1OGao.>oA.
,
1no.!.lAh.7As
••••
1 A'
Figur. ror O. No. 31b)
L-4/T-lIEEE Date: 26107/2016
Sub: EEE 455 (Compound Semiconductor and Hetero-Junction Devices)

SECTION -A
Symbols have their usual meanings. Make necessary assumptions.
1. (a) Draw enegy band structure of Si and GaAs semiconductors and show optical
transitions in such semiconductors. Explain differential negative mobility in GaAs from
E-K diagram. How certain elements acts as amphoteric dopants in compound
semiconductors? (20)
(b) Discuss the significance of critical thickness in epitaxial growth. Show variation of
critical thickness with InxGal_xAs composition for epitaxy of InGaAs on GaAs substrate.
Describe hole band dispersions for biaxial tensile and compressive strain in GaAs. (15)
2. (a) Compare J-V characteristics of pn junction diode and Schottky barrier diode. Sketch
energy-band diagram of a metal-semiconductor junction with an interfacial layer and
interface states. Show that Fermi level becomes 'pinned' for high surface state density. (20)
(b) For a Schottky diode, following parameters are given: (15)
~m = 5.2 V, ~n = 0.10 V, ~o = 0.60 V
Eg = 1.43 eV, 8 = 25 A, Ej = EO
Es = (l3.1)Eo, X = 4.07 V
16 -3 13 -I -2
N d = 10 cm , Djt = 10 eV cm
Determine
(i) barrier height without interface states,
(ii) barrier height with interface states.
3. (a) Sketch basic Ebers-Moll equivalent circuit and define the parameters used in the
model. Elaborate that nonideal effects aretaken into account in the Gummel-Poon model.
What is Gummel number? (20)
(b) For an npn Si BJT following parameters are given at 300 K: (15)
IE = 0.5 rnA, Cje = 0.8 pF, Xs = 0.7 /lm, Xdc = 2.0 /lm,
2
Cs = CI-l = 0.08 pF, rc = 30 n, p= 60, Dn = 30 cm Is
Calculate
(i) the transit time factors
(ii) the cutoff frequency and
(iii) the beta cutoff frequency
Contd P12
=2=
EEE 455
4. (a) Explain why polysilicon emitter is used in Si BJT. With necessary diagrams, discuss that
collector current and current gain are improved ifGe is incorporated in the base ofSi BJT. (20)
(b) Compare Kirk effect to that of base width modulation in BJT. How performance
degradation due to Auger recombination and Kirk effect are reduced in HBTS? With neat
sketch, describe basic operation mechanism ofTEBT. (15)
SECTION -B
5. (a) A narrow bandgap n-type and a wide bandgap p-type material are used to form a
heterojunction. The band diagram of the system before the materials are brought into
contact is shown in Fig. 5(a). Draw the energy band diagram of the heterojunction at
thermal equilibrium. With necessary assumptions, derive expression for: (18)
(i) Electric field in both regions
(ii) Electrostatic potential along the junction
(iii) Space charge width in both regions
I
-,--,'-l---r-' Vacuum level
exp
if
,
1,
ec{1sn
ex"
Fig. 5(a)
(b) Suppose, a thin layer of intrinsic GaAs IS sandwiched between a layer of
n-Alo.3GaO.7As and p-Gao.49Ino.51P as shown in Fig. 5(b). The middle GaAs layer is 50
f..llTI thick. The top and bottom layers each have thickness of 100 /lm. The doping density
16 3 17
at AlGaAs and GaInP regions are 10 cm- and 10 cm-3, respectively. The material
parameters at each layer is given in the following table: (17)
Parameters Material
GaxInl-xP GaAs AlxGal_xAs
Bandgap (eV) 1.34+0.92x 1.424 1.424+ 1.24 7x eV(x<0.45
Dielectric Constant 12.5-1.4x 12.9 12.90-2.84x
Electron Affinity (eV) 4.38-G.58x 4.07 4.07-1. Ix (x < 0.45)
Conduction Band 1.8x1 019 (0.03I7+0.9683x) 4.7x1017 2.5x1019 (0.063+0.083x)3/2
Density of States (cm-3)
Valance Band 1.9x 1019 (0.5689+0.4311x) 9x10lS 2.5x 1019 (0.51 +0.25x)3/2
Density of States (cm-3)
Draw the thermal equilibrium energy band diagram of the system.
Contd P/3
=3=
EEE 455
Contd ... Q. No. 5(b)
n-AIGaAs
GaAs
p-GalnP
Fig.5(b)
6. (a) Draw the energy band diagrams of metal-semiconductor non-rectifying junctions

under ideal conditions at thermal equilibrium. Draw diagrams for both n-type and p-type
semiconductors. (10)
(b) Draw the small signal equilibrium circuit of a p +n JFET. What are the frequency
limiting factors of such devices? With necessary assumptions, show that the maximum
cutoff frequency,fT,max of such a device can be given by the following expression:. (18)
gm,max
IT,max = -2-C---
7[ G, min
where,
gm,max = Maximum transconductance
CG,min = Minimum gate capacitance

(c) An n-channel silicon JFET is operating with a maximum cutoff frequency of 3.5 GHz.
16 3
Assume that, n-type doping density is 10 cm- , gate length is 5 /lm and channel
thickness is 0.6 /lm. Determine the device width. The relative permittivity of silicon is
11.7. Use the information given in Fig. 6(c) . (7)
. 0,2
~2:5 ,2- h5 ,1 o
Gate vottage;.vG~ (V)
Fig.6(c)
Contd P/4
:1'
=4=
EEE 455
7. (a) Draw the channel space charge region profiles of a single gate n-channel JFET for the
following operating regions: (10)
(i) Vg> Vp and Vd = OV
(ii) Vg> Vp and Vd < Vd,sat

(iii) Vg> Vp and Vd:::; Vd,sat
(iv) Vg> Vp and Vd> Vd,sat

where, Vg = Applied gate voltage
Vp = Pinchoffvoltage
Vd = Drain voltage
Vd,sat = Drain voltage at the onset of saturation

(b) Write short notes on any three of the following topics: (15)
(i) 2 DEG
(ii) Velocity saturation in JFET
(iii) Subthreshold conduction in JFET
(iv) HEMT
(c) An AI/Alo.3sGao.6sAs/GaAs HEMT is fabricated with Alo.3sGao.6sAs layer doped n-
type to 10 cm-3 and having a thickness of 500 A. Assume the undoped spacer layer to
18
be negligible and GaAs layer is undoped. The barrier height at AI/AlxGal_xAs junction is
given in the Fig 7(a). Determine the carrier density per unit area in the HEMT channel at
Vg = 0.1 V. If necessary, use the information given in the energy band diagram of a
AIGaAs/GaAs HEMT at threshold voltage in Fig. 7(b). The AlxGal_xAs system has the
following parameters: (10)

Material Parameters
Bandgap (eV) 1.424+ 1.247x eV (x<0.45)
Dielectric Constant 12.90-2.84x
Electron Affinity (eV) 4.07-1.1x (x<0.45)
Ec
Ev
6.
o 0.10;2'0.3 . 0.4
AI mole'iraction, Xi.
Fig.7(a) Fig. 7(b)

Contd P/5
=5=
EEE 455
8. (a) Show that, for a single gate JFET, the DC current in saturation region can be '
expressed by the following expression: (23)
where,
f1n = mobility of the channel material Vbi = Junction built-in voltage
Nd = channel doping density Vpo = Internal pinch-off voltage
W = device width VGS = Gate voltage
a = channel thickness
L = gate length
&s = dielectric constant
(b) For a silicon p +n JFET, the following parameters are given: (12)
Relative permittivity 11.7 Channel mobility 1000 cmL/v/s
Channel thickness 0.75 J.!m Doping in p + region lOll.! cm-3
Channel width 30 f.lm Doping in n region 1010 cm-j
Gate length 10 J.!m Intrinsic carrier density 1.5x 1oj U cm-j
Calculate the following quantities:

(i) The maximum drain current in the device.
(ii) Internal pinch-off voltage
(iii) Drain current at V GS = -0.2 V
,D 1.
(' I " '
1/ > ' Important Equations

Students may'use the:following equations ofpnjunction electrostatics if necessary:
. ~ . .
, ,: '{:l' '. . [N ],[ ,

x;z - 2Es Vbl -E."" -'--- ,I' ]}1/2
. " ,e: Ne1 Na+ Nd
p n
---------------------r--
W'Xn+Xp
W' {2EsCVbi + V~) ,[No + ,Nd]}1/2 '

, e , NaNd '
Vb; = ,kT In (NJVd) = VI In '(' NJVd)
e 2 n I
, , n~ I
Here, symbols have their usual meaning.

--------_-.:-_---'------~-----------""'~-=-='~='~.
----------'
L-4/T-1/EEE Date: 31/07/2016
Sub: EEE 453 (VLSI I)

SECTION-A
1. (a) Derive an expression showing the influence of the source-body voltage on the
threshold voltage of a NMOS transistor. (9+3x3)
For the following NMOS pass transistor circuit find the output voltage Vout], Vout2 and
Vout3. Assume VtO= 1 V, Y = 0.5 and neglect ~f
5V 4V
~ l
5+J];- Vout1
•
Fig. for Q. No 1(a)
...• - .-.~-~----'-~,.-~.
(b) A pseudo NMOS inverter is designed such that the output voltage becomes 0.25 V
2
when the input voltage is 5 V. The following data are given: /lnCox = 120 /lAN ,
2
/lpCox = 50 /lA/V , Vton = 1 V, Vtop = -1 V, Voo = 5 V, Y =0.5. Assume that the body
of the NMOS transistor is connected with the ground and the body of the PMOS
transistor is connected with Voo. (2+8+7)
(i) Draw the circuit diagram ofthe inverter.
(ii) Calculate the inverter ratio i.e., the ratio of driver transistor (W/L) to the load
transistor (W/L).
(iii) What will be the output voltage if the input voltage is held at 0.25 V? Explain
your answer.
2. (a) A 3 input NAND gate is driving 15 similar NAND gates. The following data are
2
given: Gate oxide capacitance = 35 fF//lm . Source/Drain capacitance = 15 fF//lm2,
NMOS aspect ratio (W/L)n = 10 /lm/1 /lm, PMOS aspect ration (W/L)p = 25 /lm/l /lm,
2 2
Drain/source length for both NMOS = 15 /lm, /lnCox = 120 /lAN , /lpCox = 50 /lAN ,
Voo= 5 V. (6x3)
Contd P/2
=2=
EEE 453
Contd ... Q. No. 2(a)
(i) Derive expression for rise time, fall time and dynamic power dissipation of the
NAND gate in the worst case in terms of device and circuit parameters.
(ii) Calculate the rise time and fall time of the NAND gate in the worst case.
(iii) What is the maximum operating frequency of the gate in the worst case and what
is the dynamic power dissipation of the gate at this frequency?
(b) A clock signal from the PLL is routed by a minimum size inverter to 1500 locations
in an IC where the clock is received by the same size inverter in each location. The
following data are given: Gate oxide capacitance = 25 fF/~m2, Source/Drain capacitance
= 20 fF/~m2, NMOS aspect ratio of minimum sized inverter (W/L)n = 10 ~rnll ~m,
PMOS aspect ratio of minimum sized inverter (W/L)p = 25 ~m/1 ~m, Drain/source
length for both NMOS and PMOS of minimum sized inverter = 10 ~m, ~nCox = 120
2 2
~AN , ~pCox = 50 ~NV , VDD = 5 V. (5+12)
(i) Calculate the average propagation delay ofthe driving inverter.
(ii) Design a buffer chain such that the delay of the signal through the buffer chain
becomes minimum. What is the value of n (factor by which aspect ratio of each gate
in the chain is larger than that of the preceding gate) and m (number of stages in the
chain) of the buffer chain? What isthe average propagation delay of the buffer chain?
3. (a) Show the process sequence of fabricating the following circuit in a PWELL NMOS
process technology. Clearly show the mask used and the device cross-sectional diagram
after each step. (25)
(
I
o )
.0
>
-r--~.
Fig. for Q. No. 3(a)
~~--,.----_.~~---_ .. .. _. _._-.-.~._---_.- ..-.-
- ..-./'"-
(b) Explain briefly the necessity of the following design rules: (10)
(i) Poly overlap diffusion = 2A
(ii) Floating NWELL not allowed
(iii) Metall width = 3A
(iv) N-difusion to P-diffusion spacing = 6A
(v) Maximum metall area = 1200 ~m2.
Contd P/3
•
=3=
EEE 453
4. (a) A process use aluminum conductor for which electromigration related maximum
2
current density is 2 mA//lm . How many NMOS 8: 1 inverter can be driven by a
minimum size conductor assuming A-based rule and 180 nrn process technology? The
following data are given: conductor width = 3A, conductor thickness = 1 /lm, VDD= 1.8V
and on-resistance of the 8:1 pull down transistor is 10 kn. (10)

(b) A 4-input NOR gate is designed such that the gate has equal rise and fall time in the
best case. If mobility of electron is 2.5 times that of hole, calculate the width of the
PMOS transistor in terms of the width of the NMOS transistor. Assume that both NMOS
and PMOS transistor has the same gate length. (10)

(c) A room has three doors with a switch beside each door and a light bulb at the center
of the room. You have to design a control circuit such that anyone entering into the room
from any of the door can turn the light ON or OFF. Write the truth table, the Boolean
equation of the control circuit and show the implementation of the circuit in (i) NMOS,
(ii) PseudoNMOS, (iii) Static CMOS and (iv) Footed dynamic CMOS technology. (15)
SECTION -B
If any question has missing data, make a reasonable assumption and state it in your solution.
5. (a) What is the significance of 'design for testability' for a VLSI system? Discuss the
different criteria which are used for fault classification in a VLSI system. Mention the
differences between stuck-open and stuck-on faults. (17)

(b) A two input static CMOS NAND gate is presented in Fig. for Q. 5(b). Determine a
test vector or a two-pattern test for the system for the following fault conditions: (18)
(i) a stuck-at! fault on the line fed by input X2,
(ii) a stuck -open fault in transistor 1,

(iii) a stuck-on fault in transistor 4 assuming that current monitoring is done.
Contd P/4
•
=4=
EEE 453
6. (a) Explain the operation of a four bit dynamic shift resister with the help of clear
diagrams. The stick diagrams for shift resister cells need to be presented. (18)
(b) A priority encoder is a combinational circuit in which each input is assigned a priority
with respect to the other inputs and the output generated at any time depends on the
highest priority input then present. If such a structure is described in the Fig. for Q. No.
6(b), design a stick diagram to realize the structure. (17)
C'- ~-;p- - .- -- ~ -"-e;
..-r'"YV\ +-1,,,"c:. b 1 .g, (

~?- ~ I 'ji, " P I Po
C)"---<::3--e --e--oc---:
Go p..,..; <rV' ; +-::J o 01 I,'
=-£:~~- -o-t 0 --1- 0
o I I I CJ
,
1
\
0
01
D
C)
0'
0\
-CJ \
______________________ \ ,l.-c-.O 1
f-~~_. ~ -8:>/ 6 Cb/.
7. (a) Explain the operation of a 4x4 barrel shifter. Mention its practical applications.
Devise the stick diagram for such a barrel shifter. (18)

(b) Write and explain the verilog code for a Mealy type finite state machine with the help
of state diagrams. (17)
8. (a) Discuss the differences between NMOS and CMOS realizations of a parity generator
with the help of stick diagrams. Explain why buffer sections could be required during the
realization of bus arbitration logic circuits. (20)

(b) Design the layout of a four way n-switch based multiplexer showing the position of
the standard cells. (15)

,.
/
L-4/T-l/EEE Date: 25/0112017

Sub: EEE 455 (Compound Semiconductors and Heterojunction Devices)

USE SEP ARA TE SCRlPTS FOR EACH SECTION
Assume reasonable value for any missing data
Symbols have their usual meanings
SECTION -A
1. (a) Derive the expressions of emitter injection efficiency factor and base transport factor in
a BIT. Explain the rationale for keeping base width as low as possible from your derived
result. Assume excess. minority carrier concentration in the base and emitter to be
respectively, (20)
on.(x)~ :: {[exp( e;;, )-iJXB -X)-X} and
o PE(X')=~; [exp( e;;E )-iJXE -x')

(b) Consider an npn Silicon BIT with the following parameters: (15)
DB = 25 cm Is DE = 10 cm Is
7
rho = 1O- s rEO =5 x 10-8 s
NB=10 xE=0.5 m
The recombination factor, a = 0.998.

Common emitter current gain, j3 = 120
Base transport factor and emitter injection efficiency factor are equal. Calculate the
maximum base width XB and minimum emitter doping NE to achieve these specifications.
2. (a) What are the reasons behind early effect and current crowding in a BIT? Explain with
necessary figures. (17)
(b) Derive the electron current density in the base region of an npn BIT in terms of base
Gummel number. (18)
Explain how Gummel-Poon model can account for various non-idealities in a BIT.
3. (a) Explain'how 2D electron gas is formed in an AlxGa'_xAs-GaAs heterojunction.

Discuss how mobility is affected in this structure. (10)
(b) Explain transistor performance of a "normal" AIGaAs:"'GaAs MODFET in depletion
mode. Draw its energy band diagram in ON and OFF state. (12)
(c) Consider an N Alo.4Gao.6As-i GaAs abrupt heterojunction. Assume that the AIGaAs is
doped with a concentration ofNd = 3 x 1018 cm') and has a thickness of 300 A. Let 0BN
= 0.9 V and ilEc = 0.24eV. Relative dielectric constant is 12.7. (13)
Calculate (i) Voffand (ii) lls for V g = 0 V.
Contd P/2
-2-
- -
EEE 455
4. (a) Derive the formula of internal pinch-offvoltagein an n-channel JFET. (10)

(b) Prove that the base transit time in an npn BJT is proportional to the square of base
width. (10)
(c) What is Kirk effect? Explain how it reduces transistor gain when high collector current
.is drawn. (15)
SECTION-B
There are FOUR questions in this section. Answer any THREE
5. (a) For an experimental setup an epitaxial pseudomorphic layer of InxGal-xAsySbl-y is

grown on InP substrate. If a light of wavelength less than 1243 nm passes through the
epitaxial layer then it is absorbed in the film, otherwise it transmits through the layer. The
lattice parameter of the un strained InGaAsSb is 5.93A. By using data from Figure for Q.
NO.5 (a), find x and y. Also determine the critical thickness for this system. (25)
(b) Describe the possibility of the existence of the random alloys with the help of phase
diagram of quaternary compound Ax B1-x Cy Dl-y. (10)
6. (a) Define mono crystalline, polycrystalline and amorphous materials. (6)

(b) Why is lattice constant of semiconductor important for heterostructured devices?
Discuss the effect of biaxial compression on opto-electronic devices. (17)
(c) Explain differential negative resistance in GaAs and velocity saturation in Si. (12)
7. (a) What is effective mass? Explain a method with mathematical verification to determine
effective mass from E-K diagram. (7)
(b) Explain complete ionization of the acceptor atoms and freeze-out of donor atoms.
Derive the equation of charge neutrality for the condition of complete ionization. .(16)
(c) A silicon device with n-type material is to be operated at T = 550 K. At this
temperature, the intrinsic carrier concentration must contribute no more than 5 percent of
the total electron concentration. Determine the minimum donor concentration required to
meet this specification. (12)
8. (a) Define staggered, straddling and brokel} gap heterojunctions. Give one example of each
type. (9)
19 l
(b) Consider an n- Ino.8Gao.2As and P-Gap heterojunction with NDN = 0.3 x 10 cm- and
NAP = 0.1 x 1020cm-3 has following parameters given in table for Q. NO.8 (b). (26)
(i) Draw the thermal equilibrium energy band diagram of the system with proper
dimension.
(ii) Determine !:i Ee, !:i Ey, V hi, xn and xp for this system and show them in the energy
band diagram.
"
""I'
II
0.4. :lnAs_ "

II
:6.4 6S.
Figure for Q. No. Sea)
~
I
Table for Q. No. 8(b)
Parameter Ino.8Gao.2As GaP

Electron Affinity( eV) 4.0 2.04
Bandgap( eV) 0.55 2.26
Conduction Band Density of .0.137x1018 0.186x102o
States, Nc (cm-3)
Valance Band Density of 0.659x1019 0.123x102o
,~.;
States, Nv (cm-3)
Dielectric Constant 15.15 11.1
----_._._---
.,
L-4/T-1IEEE Date: 30/0112017

Sub: EEE 453 (VLSI I)

SECTION -A
1. (a) Explain the meaning of the following MOS model parameters: (10)
(i) Kp (ii) GAMMA (iii) cjsw (iv) mjsw (v) uo
(b) Show the device cross-sectional diagram of the NMOS and PMOS transistor of a
Pseudo NMOS inverter fabricated on an-type Si wafer. Clearly indicate the source,
drain, body contacts, interconnects and the bias connection of the back-gate. Explain
why the back-gate of the transistors are not kept floating? (15)
(c) Show that the resistance of a square sheet of interconnect material IS same
irrespective to the area of the sheet. (10)
2. (a) A CMOS inverter is designed such that the current carrying capacity of NMOS and
PMOS transistor is equal i.e. (Pn = Pp). Assume that the supply voltage is 5 V and Vtn =
1V and Vtp = -1V. Draw the transfer curve of the CMOS inverter and show the
inversion voltage. From the transfer curve show the equation of high level noise
margin and low level noise margin. Explain each parameter used in your equation
graphically. What will happen to the low level noise margin and high level noise
margin ifPn» Pp? (15)
(b) Draw the approximate wave shape of Vout. Ip, In,Ie,Pn (In X VouD,Pp (Ip X (V DD -
Voutt)), Pe (Ie X Vout)and PVoo (Ip X VDD) for both the circuit shown in Fig. for Q 2b_l
and Fig. for Q 2b_2. (20)
Voo'
Vin~
...-4
oU ~ Vln
00.1 .0.3 0.6 0.8 1
. t inns
~
v,;J. .~','olr' . C
L
~~
'ir CL
. ,
GND .
GND .... .'
'. . _, __.!I.l,I. f~r~~b_J Fig. forQ2b..;2,
--'-'"
3. (a) Describe all the steps of photolithography to pattern a gate polysilicon layer in a
CMOS inverter. (10)
(b) An ESD protection circuit shown below needs a resistor, diode and MOS
transistors. All of these devices have to be built in standard CMOS process. Show the
Contd P/2
=2=
EEE 453
Contd ... Q. NO.3 (b)
possible fabrication sequence of the circuit on a p-type CaMS process. In each step
show the mask and the cross-section of the circuit up to that step. For clarification you
have to draw the composite layout first. The pad in the figure can be built from any
metal layer. (25)
,~.-- ':c-~>-Dio.de-c----
~t Iimilinggate
'resistor .. oxides
Fig. fbrQ3(b)
4. (a) What are the function of F and G in the following diagram? Just write down the
logic function without the need oflogic minimization. (10)
(b) You have to design a car alarm system in which the alrm will ring (Y= 1) if anyone
of the following condition is satisfied. (i) {The key is in (K= 1), the Seat belt is fasten
(B=l) and the door is open (D=O)} or (ii) {The key is in, Door is closed and Seat belt is
not fasten}. Write the Truth table, the Boolean equations and show the implementation
of the circuit in (i) static CMOS, (ii) NMOS, (iii) Pseudo NMOS, (iv) Footed dynamic
CMOS and (v) Un-footed dynamic CMOS. (10)
(c) Draw the schematic diagram of the circuit shown below. Calculate the rise time, fall
time and power dissipation of the driver circuit. The following data are given: (15)
Gate oxide capacitance = 35 fF/llm2• Source/Drain bottom Junction capacitance = 15
fF/llm2, Source/Drain side wall junction capacitance = 10 fF/llm, Poly-substrate
2
capacitance = 5 fF/llm2, metal-substrate capacitance = 3 fF/llm2, llnCox=120 llA/V ,
llpCox=50 llA/V2, VDD=5V and.f=20 MHz. Assume 100 nm process and all gate lengths
are of 2').".
Contd P/3
=3=
EEE 453
Contd ... Q. NO.4 (c)
~----------~._--
NWELL
P-Diffusion
Polysilicon
Vin=O .. Contact
. .
N-Diffusion
SECTION-B
5. (a) Show the construction of a 4/1 mux using NMOS pass transistor. How would you
connect the input ifthe mux is to be used as a 2 input XOR gate? (10)
(b) What are the advantages of using 2-phase non-overlapping clock in a synchronous
digital system? Show a suitable circuit which can be generated such a clock from a
single source of master clock. (10)
(c) The following diagram shows the truth table of a 3-bit Gray to Binary Converter.
You have to design the hardware of the converter in. a structured modular expandable
way such that number of bits can easily be increased. Show the design of the unit cell
and the connection of the 3-bit cell. Draw the layout of the unit cell in such a way that
the cells can be easily connected together. (15)
Gray Code Binary code
G2 Gl GO A2 Al AO
0 0 0 0 0 0
0 0 1 0 0 1
0 1 1 0 1 0
0 1 0 0 1 1
1 1 0 1 0 0
1 1 1 1 0 1
1 0 1 1 1 0
1 0 0 1 1 1
Table for Q. 5(c)
Contd P/4
•
=4=
EEE 453
6. (a) Draw the circuit diagram of a 2 x 2 bit Six transistor Static Random Access
Memory array. Show clearly the row select, column select, Precharge, Sense amplifiers
and the I/O signal lines. Explain how a read and a write operation is done by assuming
that the second row and second column cell is the target cell to write and read from. (15)
(b) Draw the circuit diagram of the 1T DRAM cell and explain how read and write
operation is performed in this cell. Draw a cross- sectional diagram of the memory cell
and explain how the cell saves silicon area. (10)
, (c) A metal line of 100 j.!m long and 100 nm wide is used as a bit line. Capacitance
from metal line to substrate is 100 aF/um2, and a memory cell is connected in every
400 nm. Each memory cell is connected through an NMOS device to the bit line
having a source or drain implant capacitance of 0.4 IF, and a typical value for the
memory bit capacitance, Cmbit is 20 IF and V 00 is 1 V. If the bit line was pre-charged
to V00/2, calculate the change in bit line voltage when accessing the memory cell.
(Note: a = 10-18, /= 10-15) (10)
7. A sequence detector produces a '1' for each occurrence of the input sequence' 1001' at
its input.
(a) (i) Draw the state-transition diagram of the FSM realizing the sequence detector.
(ii) Obtain state table from the state transition diagram. (20)
(iii) Realize the FSM using D FFs and combinational logic.
(b) Show the complete design of a modulo-8 counter using Finite State Machine
approach and show the implementation of the circuit using D FFs and combinational
logic. (15)
8. (a) A three input CMOS NAND gate is shown in figure below. The circuit has three
faults St, S2, and 01 as shown in the figure. Considering one fault at a time find
appropriate test vector(s) to detect each of the faults. (15)
Fig. for Q8(a)
Contd P/5
=5=
EEE 453
Contd ... Q. NO.8
(b) A pseudo random sequence generator (PRSG) is built with the linear feedback shift
register shown below. Assuming the circuit reset to 111, find the pseudo random
sequence generated by the circuit. (10)
; CL
Fig. for Q. 8(b)
(c) What is built-in Logic Block Observer (BILBO)? Show how a BILBO circuit can
be constructed from a PRSG and signature analyzer to check the functionality of a
logic block and explain how the circuit works. (10)

~' .#
//
L-3/T2/EEE Date: 30/07/2011
Sub: EEE 309 (Communication Theory)

SECTION-A
There are FOUR questions in this Section. Answer any THREE. .
Answer in brief and to the point
1. (a) Mention the fundamental limitations of a telecommunication system. Explain in how

many ways a communication channel can distort a signal, as it travels through the
channel. Mention the two conditions for distortionless transmission of a signal. (15)
(b) Write down the equation for thermal noise in an electrical circuit and from there
derive an expression for the maximum noise power that may be transferred to a resistive
termination. (12)
(c) Calculate the maximum thermal noise (in watt) that a resistive termination in a
standard band-limited telephone channel (300 Hz- 3400 Hz) will produce at an ambient
temperature of 17°C. Also, express it in dBm. (6+2=8)
2. (a) Mention the purposes of performing modulation. Define amplitude modulation (AM)
and modulation index for AM. Discuss the method of generating a DSB-SC signal. (11)
(b) Suppose that an AM signal is represented by (12)

set) = 100 cos (2n x 104t)
+ 50 sin (2n x103t) x cos (2n x 104t).
Draw the spectrum of the AM signal and determine

(i) modulation index
(ii) power in side-bands and
(iii) total power in the AM signal.
(c) Why is DSB - FC signal transmitted in AM although it is less efficient? Draw a
complete envelope - detector circuit for demodulating an AM signal and explain its
operation with necessary signals at each point. (12)
Will it work for an over-modulated signal?
3. (a) Define frequency modulation (FM). With necessary equations, distinguish between
FM and PM. Suppose that you have an FM modulator. How can you use it to achieve
PM? (10)
(b) An FM transmitter is radiating 20 KW at a carrier frequency of 88 MHz with a carrier
amplitude of Ac and modulation index ~ = 0.85. Determine (12)
(i) the carrier power
(ii) power in the side-bands
Contd P12
=2=
EEE309
Contd ... Q. No. 3(b)
(iii) bandwidth of the FM signal using Carson's rule.

(c) What is a frequency discriminator? Draw the block diagram of a balanced frequency
discriminator and explain its operation in brief. (13)
4. (a) Mention the main purpose of sampling an analog signal. For a sin wave input, show
the gating pulse train and output of a sampler. (12)
Why is the sampled version called a PAM signal?
(b) Write drown the equation for the output xs(t) of a sampler, for an analog input signal
x(t) and a periodic gating pulse train get), with a duty cycle d = 2:.. and unity pulse
T
amplitude. (12)
Using this equation, explain, how one can reconstruct the original analog signal x(t) from
the sampled version ofthe signal xs(t).
(c) Compute the frequency components that will appear at the output of the two filters
shown in Fig. for Q. No. 4(c) for the input signal (11)
x(t) = 5 cos (1500 nt) - 0.4 sin (5000 nt) + 0.12 cos (10000 nt).
SECTION -B
The Symbols have their usual meanings
5. (a) Draw the block diagram of a PCM encoder. Derive the expression of signal-to-
quantization noise ratio (SQNR). Explain the purpose of companding. (15)

(b) 1 volt (rms) sinusoidal message signal of frequency 10 KHz is given input to a PCM
encoder. The required SQNR is 30 dB. Determine (10)

(i) How many bits are needed to encode each sample?
(ii) The output bit rate.
(c) Explain the purpose ofDPCM with its functional block diagram. Compare DPCM and
DM. Calculate the bit rate of a single channel DM that uses the standard band-limited
telephone channel. (10)
6. (a) For an OOK signal, with a general block diagram, show the output of the synchronous
detector if the locally generated Carrier is (i) not at the same frequency (ii) not
I
synchronized in phase with the transmitted carrier. It is possible to detect a PSK signal by
an envelope detector? Justify your answer. (15)

(b) With neat sketches, compare MSK and BPSK in terms of phase and power spectral
density (PSD). (8)

Contd P/3
•
=3=
EEE309
Contd ... Q. No.6
(c) Write down Nyquist's maximum capacity theorem and Shannon's maximum capacity
theorem. Using these theorems, compute the number of amplitude levels that can be
correctly detected if one wants to send a signal through a standard band-limited telephone
channel. Assume an SNR of 1023. Is such a choice of number of amplitude levels
realizable in practice? Justify your answer. (12)
7. (a) With specific examples and figures, show that in a digital communication system, bit
rate is doubled if 4-level modulation is adopted instead of2-level (Binary) modulation. (7)
(b) With general block diagram and sketches, derive the outputs of 4-PSK modulator and
that of demodulator. What are the phase states of the carrier when the bit stream
1001011100 is applied to the 4-PSK modulator? If the recovered carrier at the
demodulator is out of phase by 1t radians, what will be the output when the above 4-PSK
carrier is applied to the demodulator? (18)

(c) Draw the block diagram of a differential BPSK modulator. Summarize the encoder
logic and rule of a differential BPSK. With a sketch of the phase states, explain 16
quadrature amplitude modulation (QAM). How the presence of amplitude modulation in
QAM can be understood? (10)
8. (a) With an appropriate voltage-time diagram, derive the equations for information
content (1) and system capacity (C) (l0)

(b) A 10-channel PCM system multiplexes 10-band-limited voice channels. The sampling
rate is 8000 samples/sec. The encoder has 8 levels at the input and gives a 3-bit encoded
digital pulse. Calculate the band width required at the output of the encoder. If an 8-bit
encoder is used instead of the 3-bit encoder, and if the available channel bandwidth at the
output of the encoder is 150 MHz, calculate how many voice channels can be
multiplexed? (15)
(c) Write short notes on any one of the following: (10)
(i) 30 Channel and 24 channel PCM systems
(ii) Modem and data multiplexers.
(iii) TDMA and FDMA
Sampler
..!s'= 8000 samplesls

Bandpass £=?
Filter /'
Fig. for ~. No. 4fV

L-3/T-2/EEE Date: 06/08/2011
Sub :EEE 315 (Microprocessor and Interfacing)

SECTION -A
1. (a) (i) A memory location has a physical address 4A37H. If the segment number is
40FFH,. compute the offset address and if the offset address is 123BH compute the
segment number. (6)
(ii) Determine the physical address of a memory location given by OASI :CD90H. (3)
(iii) Define (with example) any four of the following: (12)
(I) Immediate Addressing Mode
(II) Bus Interface Unit
(III) Paragraph Boundary
(IV) Single-flag Jump
(V) Divide Overflow
(b) Suppose A is an MxN byte array arranged in row major order. Write an assembly
code to compute the transpose of the matrix A. Store the answer in an NxM byte array B
arranged in row major order. For example, (14)
if A =
I
2
378
I 3
8
So A will be given as
419
then B =l~ 8 731
2
9 8
A DB 1,3,4,2,8,9,3, 7, 8
The resulting B will be stored as
B DB 1,2,3,3,8, 7,4,9,8
2. (a) In the code segment given in table, there are some syntax as well as logical errors.
Find the errors and correct them with proper explanation. Provide the corrections in a
tabular form given as
Line No. Correct Instruction Explanation
Answer to Answer to
be written be written
Here here
Contd ..... P/2

=2=
EEE 315
1 CODE SEGMENT
2 ASSUME CS:CODE, DS: CODE
3 LEADX,3N
4 MOV AL, [DX]
5 REPEAT: CALL SQR
6 ADD S&P, [S&P + BX]
7 DECAL
8 JNZREPEAT
9 HLT
10 SQR: PUSH AL
11 XORAH,AH
12 MULAL
13 MOV BX, 4
14 MOV [S&P + BX], AX
15 POP AL
16 RET
17
18 3N DB 7
19 S&P DB ?
20
This code also computes the summation of a series. Write the series in mathematical
form. (18)
(b) For the following declaration and instructions given mention the addressing modes of
both the source and destination operand. If the instruction is illegal explain why it is
illegal. (10)
WRD 1 DW OF38CH, 1259H, 3986H
BTE 1 DB OF3H, 53H, IFH
(i) MOV AX, 32H
(ii) XCHG BTEI + 2, WRD I
(iii) MOV CX, WRDI + 3
(iv) LEA SI, BTE 1 + 2
MOV DX, [ST] - 2
(v) ADD DH, [SI] 3
(vi) MOV [SI], OF8H
(vii) INC WRDI [BX] [BP]
(viii) PUSH 3618H
(ix) XCHG [BX], [DI]
(x) ADD BTEl, AX
Contd ..... P/3

..
=3=
EEE 315
eouid ... Q. No.2
(c) What will be the value of CF, SF, ZF, OF after executing each of the following
instructions. (7)
(i) MOV AL, 80H
MOVBL,OFFH
IMULBL
(ii) MOV AL, - 15
MOVCL,4
SHLAL,CL
(iii) MOV AX, OEF36H
MOV CX, 01CF8H
ADDAX,CX
RCLAX
ANDAX,CX
NOTCX.
CMP CL, 03FH
3. (a) Design an 8086 system with two 2Kx8 RAM, one 1Kx8 RAM, two 2Kx8 ROM and 8
I/O devices with each having 4 internal addresses. For the two 2Kx8 RAM the address
range will be 1C800H - 1CFFFH and 1D400H - 1DBFFH. For the one 1Kx8 RAM the
address range will be 1DOOOH-1D3FFH. For the two 2Kx8 ROM the address range will
be OF800H - 107FFH. For the I/O devices provision for a dedicated 1K memory mapped
I/O should be kept in the range 01001H-01400H. 8 I/O devices must be shown each
having 4 internal addresses in the address range 011 OOH- 0111 FH. All the odd addressed
data must be connected to the upper byte of the data bus and even addressed data must be
connected to the lower byte of the data bus. Provide a neat connection diagram with
proper labeling. (25)
(b) Sketch the timing diagram of the write cycle of 8086. (10)
4. (a) Suppose, a string is given in the memory. Write an assembly program that will change
the case of the string. Use string instructions for accessing string elements. For example if
the given string is 'BaNGLadeSH', the resulting string will be 'bAnglADEsh'. (15)
(b) Suppose, complex numbers are defined as
CMPLX LABEL WORD
REAL DB 35
IMG DB 23
Where, the declaration means 35 + 23*j.
(j = imaginary unit). Write an assembly program that will multiply two complex
numbers. (15)
Contd ..... P/4
=4=
EEE 315
Contd ... Q. No.4
(c) In the instruction

RET pop-value
What is the significance of 'pop-value'? (5)
SECTION -B
5. (a) The owner of a newly established mOVIe theatre has decided to employ a
microprocessor based automatic door-control system in two gates. A feature of this
system is to count the number of persons entering the theatre through the gates. For
GATE 1, the maximum count is 1200 and for GATE 2, the maximum count is 1500. If
the counts reach maximum for a gate, it should be closed. The system should run on an
interrupt basis because the 8086 microprocessor has some more work to do.
(i) Draw the schematic of the system, with address decoding, using an interrupt controller
(8259 IC), a timer (8254 IC) and decoder ICs (74LS138). The internal addresses for the
interrupt controller and the timer should be FF20H, FF40H and F120H, F320H, F520H
and F720H respectively. Assume that only the IR4 and IRS inputs of the 8259 are
available for use. (16)

(ii) In which mode should you RUN the 8254? What should be the initial values? Let the
interrupt types of the IR4 and IRS inputs be type 44 and 45 respectively. Write a code in
assembly language to initialize both the 8259 and 8254. Also write an ISR for IR4 at
memory location 0000: 1200H and for IRS at memory location 000: 1300H so that if
interrupt occurs the timer would be stopped and two variables FLAG 1 and FLAG 2 will
be set for GATEI and GATE 2 respectively. (19)

8259 Control Words:
Ao D7 D6 Ds D4 D3 D2 D1 Do
ICWl 0 A7 A6 As 1 LTIM ADI SNGL IC4
ICW2 1 A1S/T7 A)4/T6 A13/Ts A12/T4 AI)/T3 AIO A9 As
ICW3 1 S7 S6 Ss S4 S3 S2 S) So
ICW4 1 0 0 0 SFNM BUF MIS AEOI JlPM
OCWl 1 M7 M6 Ms M4 M3 M2 M1 Mo
OCW2 0 R SL EOI 0 0 L2 L) La
8254 Control Words:
I SCI I SCO I RWI I RWO I M2 I Ml I MO I BCD I

Contd ..... PIS
•
=.5 =
EEE315
6. (a) Draw the connection diagram for connecting four seven segment displays in cascaded
form with port A and port B of an 8255A-PPI (using proper buffering) so that the
addresses of PORTA, PORTB, PORTC and the CWR are F008H, FOOAH, FOOCH and
FOOEH. It is given that the data and the address bus are already separated by means of
latches and transceivers. Also connect two switches at PCO and PCI pins of 8255A. (13)
DO""D7 PA7""PAO a Seven

b Segment
AO PB7"'PBO
c
8
Al PC7"'PCO d
e
f
'S255A g
h
GND (common)
WR
i
;
!
J ~.t--~
I . . - •
;-.-.J=i~a,j8-25S"7J~amct ~~~-l3lcTJ;;;.:
.__... '"_--,I r . -------~--..

(b) Initialize Ports A and B of 8255A as output and Port C as input by writing proper
assembly codes. (10)
~.':I'~f
\
\
p.
(c) Ifthe switch at PCO is pressed, the four seven segment displays should sho~ \
I ,
. \..1_"_' -'. J '-
and if PC I is pressed, it Would show ,,-,','
,',- - -. - ,. .
/,'-" _ .'. If no switch is pressed it

- - _II
. - I /
f" ).
I,
would simply show - - - - / . Write an assembly code segment for
detecting a switch press using polling and for showing these outputs at the seven segment
combinations. (12)
Contd ..... P/6

I/' '
=6=
EEE 315
7. (a) Assume that an 8251 is connected at FF08H and FFOA addresses. Now write the
initialization sequence in assembly language for the 8251 considering: baud rate factor of
64, 7bits/ character, even parity, 1 stop bit, transmit and receive interrupts enabled, DTR
and RTS asserted, error flag reset. (10)
(b) Show the sequence of instructions that can be used to poll this 8251 A to determine
when the receiver buffer has a character ready to read? How can you determine whether a
character received by 8251 contains parity error? (7+5=12)
(c) What frequency of transmit and receive clock will these 8251A require in order to
send data at 2400 Bd? What other ways besides polling does the 8251A provide for
determining when a character can be sent to the device for transmission? Describe the
additional hardware connections required for this method. (5+8=13)
Table: MW CW and SW for 8251A IC.
MW S2 Sl EP PEN L2 Ll B2 Bl
CW EH IR RTS ER SBRK RxE DTR TxEN
SW DSR SYNDET FE OE PE TXE RXRDY TXRDY
8. (a) What are the major differences between SAPI and SAP2 architecture? Explain the
idea of Bidirectional Registers employed in SAP2. (10)

(b) What is the function ofpresettable counter in SAP! architecture? (5)
(c) What instruction can be used to disable the INTR input of 8086? What is the
significance of ICW3 for master and slave 8259 devices? Why is the INTR input
automatically disabled as a part of the response to an INTR interrupt? (2+4+6=12)

(d) Describe the double handshake data transfer with the help of simple timing
diagram. (8)
~ ,~- ••••.• >'
',,' t
, ,.r::'
/.
L-3/T-2/EEE Date: 19/1112012

The figures in the. margin indicate full marks .
._~~~ "._.~ _ _~",,,.._. """"""''''''''''''_''....... __ ._ __ _ _ __ _~..~__ "~__ _ __ _.._,,,.., .~~_.h._ ,~ _ _..__ ~_ " _._ _.............----- ~.."., _-- -.
SECTION -A
1. (a) Discuss the limitations of a communication channel and their effects on the
performance ofa communication link. (10)

(b) Distinguish between baseband transmission and .bandpass .transmission .. Draw the
block diagraril of a baseband transmission system and explain how the distortion occurs
in such a system. Why are repeaters used in such a system? (15)

(c) Derive the Nyquist condition for distortionless transmission through a baseband
transmission system and explain briefly. (10)
2. (a) What is meant by multiplexing? State the purpose of multiplexing. Briefly discuss
the principles of FDM and TDM. Distinguish between asynchronous, plesiochronous
and synchronous TDM. .~ (10)

(b) With necessary schematic diagram, discuss the CCITT recommended FDM schemes
for generation of FDM groups, Super groups and Master groups. (10)
(c) 16 T1 (DS1) channels are time multiplexed with 8 EI channels and a data channel as
shown in the followin~ diagram. Bandwidth available for transmission over the channel
is 100 MHz. Determine the allowable bit rate Rb l of the data channel, R",I Rb 1 and
output bit rate, Ro. Assume channel spectral efficiency of 1 bit/sec-Hz. (15)
...,
........-.. ~..... _~-_._...._. ..•.. '_ .._"_ .....,., ..• '.'
,
••••••.••. , •••• ", ..••••• :, •••••.•_ ••.••• ~, •.•••••.. _.M'"
Contd P12
=2.=
EEE309
3. (a) Define amplitude modulation (AM) and the index of AM. Wrfte an expression of the
AM signal for a single sinusoid as the modulating signal and find
. .
the expression of the
. spectrum ofthe AM signal. (10)

(b) The modulating signal input to a square-law modulator is given by
Pm (t) = lOsin(21Tx lO:!t)+5cos(21TX l04t)+ 3 COS(41Txl04t). The carrier is a sinusoid
with frequency 1 MHz and peak amplitude 24 Volt. The output of the square-law
modulator is passed through a BPF to generate DSB signal. Draw the spectrum of the'
signal at the input and output of the BPF and determine: (15)
(i) ,bandwidth of the BPF filter;
(ii) the overall modulation index;
(iii) power in the sidebands;
(iv) total power in the USB signal.
(c) What are meant by heterodyne and coherent detection? Draw the block diagram of a .
superheterodyne AM envelope detection receiver and show the waveforms at different
output stages. . (10)
4. (a) What is meant by angle modulation and what are its different forms? Write
expressions for FM and PM signals and show how an FM signal CaIl be generated using
a PM modulator. (10)
(b) Distinguish between narrowband and wideband FM. With necessaryhlock diagram
discuss the Armstrong'method of generating a WB-FM signal starting with a NB:-phase
modulator. (10)
(c) An FM radio channel is operating at a carrier frequency of 96.2 MHz with a channel
bandwidth of 0.2 MHz. The bandwidth of the modulating signal is 15 kHz. The peak
frequency deviation is 60 kHz. The carrier amplitude is 100 V rms. (15)

Determine:
(i) the modulation index;
(ii) bandwidth of the FM signal using Carson's rule.
(iii) number of sidebands available within the channel bandwidth;
(iv) power in the sidebands
(v), total output'power of the FM transmitter.
Use Bessel Function table.
Contd P/3
=3=
EEE309
SECTION-B
There are FOUR questions in this section. AnsWer any THREE.
Answer in brief and to the point.
5. Answer the following short questions:

(a) What was the basic purpose. of sampling an analog signal that results in a PAM
signal? With neat sketches, define natural and flat-topped sampling. (5)
(b) State the famous sampling theorem.' Determine the Nyquist's sampling frequency
for the message signal x(t) represented by (4)

.
x(t) = '-2.5sin(10007it)+ 0.7cos(6800m)+ 1.3cos(2000m)
(c) Mention how you can reconstruct the original analog signal from its sampled
version. (4)
(d) Draw the basic block diagram of a PCM transmitter. What is the function of a
sampler in PCM? What type of sampler is used here and why? (6)
(e) Draw the binary-encoded digital pulse-train (voltage vs. time) corresponding to the
bit-stream 10110011 at the output of the PCM transmitter. Also, draw the
approximate waveshapes of the same pulse train at a distance of 2 kms from the
transmitter. (Assume Cu-wire subject to noise and attenuation as the medium).
Explain the causes for the change in shapes of the pulse train. (8)
(f) Explain how the effect of white noise can be totally eliminated in a PCM system. (4)
(g) Define quantization noise in PCM and state its effect on the quality of the received
signal. How can we minimize quantization noise? (4)
6. (a) Calculate the bit-rate ofa baseband digital signal in a single channel PCM system
that uses the standard band-limited telephone channel. What is the equivalent bandwidth
of this signal? Can we ideally pass this signal through an analog band-limited telephone
channel (300 Hz-3400 Hz)? If not, why? (12)

How can we modify the encoded digital signal so that it can be passed through the same
band-limited channel with minimum signal distortion?
(b) Defme the basic digital modulation schemes with neat sketches and examples.
Mention their relative merits and'demerits. (12)

(c) Draw the synchronous detection circuit that can detect a PSK signal. Justify its
proper operation using an appropriate example and mathematical relation. Can it be used
for detecting an OOK signal? If so, explain how. (11)

Contd P/4
=4=
EEE 309
7. (a) Comment on the bandwidth of human speech signals. In PCM, why do we still band-
limit the speech signal between 300 Hz- 3400 Hz (an analog FDM band for a
subscriber)? (11)
Calculate the bit-rate of a 30-channel PCM system (EI). Mention the purpose of source
coding in digital communication.
(b) What is multi-level modulation and whatwas the basic purpose of its introduction? (12)
Draw the block diagram of a QPSK modulator circuit using two BPSK modulators.
Comment on the tasks of each of the two level shifters used. What are the phase states
of the carrier when the bit-stream 10110001 is applied to the QPSK modulator?
(c) Draw the block diagram of a QPSK demodulator. With proper mathematical
equations and tables show that the signal extracted atthe output of the demodulator will
be exactly 10110001 as transmitted from the QPSK modulatorin part (b). (12)
8. (a) Draw the block diagram of the SImplest delta-modulator and demodulator, and
explain their operations in brief. Mention the relative merit of delta modulation over
PCM. On what type. of signal. can we apply delta modulation? What IS
granular/quantization noise in delta modulation? How can we minimize this noise? (12)
(b) Define information and information capacity. Name and explain the two factors that
limit the rate of information transmission through a communication channel. (11)

A message consists bfthe letters A, B, C and D. Suppose that each letter is coded into a
sequence of two binary (on-off) pulses. The letter Ais represented by 00, B by 01, C by
10 and D by 11. Each individual pulse interval is .s ms. Calculate the average rate of
information transmission if the different letters are equally likely to occur. (11)
(c) Mention the essential properties of the set of orthogonal Pseudo-Noise (PN) codes to
be used in DS-SS multiple access technique. Verify whether the following two sets of
PN codes are orthogonal: (12)

x = [-1.ill 1] and
y=[-1 EDI -1].

Draw the block diagram of a 2-channel DS-SS CDMA scheme. Mention the function of
each block using brief statements.
, ..:fII'
/ / /
..•.•..
/' .. ,
EE.~' 30'1' ~)v,..~.~~.1~ .

....•. c•... ~.".-, ••• _- "_ •• ,.,,..-;.._,.,~, .•••. e ._._ ••_ .•• __ .• ~-~_ .. , .• _"._._._-~_ .. ,..•...•....... ::J...~.__.,.. _ ••• _,,~_ ••.••• ~ __ •.•__ .• _0"
.1 TABLE A6~5 Table of Besselfunctions

a
In(X)
8 10 12
3 4- .6
2
nue 0.5 . 1
-0.2459 0.0477
:-0.3971 0.1506 0.1717
0.7652 0.2239 -0.2601 -0.22.34
\) 0.9385 -"0.{)660 -0.2767 0.2346 0.0435
0:4401, 0.5767 .03391 -0.084,9
1. 0.2423 -0.2429 -,0.1130 0.2546
0.3528 0.4861 0.3641
2 0.0306 . 6'.1149 :-0.2911. 0,0584 0.1951
0.3091 0.4302 0.1148
3 0.0026 0.0196 0.1289 -0.2196 0.1825
0.2811 0.3576 -0.1054
0.0025 0.0340 0.1320 -0.0735
4 0.0002 . 0.3621 0.1858 -0.2341
0~OO70 0.0'430 0.1321
5 0.0002 0.3376 -0.0145 -0.2437.
0.0114 0.0491 ,0.2458
6 0.0012 0.2167 -0.1703
0~0152 . 0.1296 . 0.3206
0.0002 0.0025 0.0451
7 . 0.0565 0.2235 0.3179
0.0005 0.0040
8 .
.. . - .... .•.. 0:0001'«'&' 6.(JOO~'~'""'''\).0212.-'0;1263 -'--'" 0.2919 ......_..0.2304
...
d'
9 0.0608 0;2075 0.3005

0.0002 0.0070
10 0.0256 0.1231 0.2704 .
0,0020
11 0.0096 . 0.0634 0.1953
0.0005
12 0.0033 0.0290 0.1201 .
0.0001
13 0.0010 0.0120 0.0650
14
.. "For more extensive tables of Bessel functions, see Watson (i966, pp. 666-697), and Abramowitz and Stegun (1965, pp.
~S8~06). .
.<'
..•_._. ...".i ..
L-3/T-2/EEE Date: 24/12/2012
Sub: EEE 315 (Microprocessor and Interfacing)

SECTION~A
1. (a) Design an 8086 system with four 4k x 8 ROMs (address starting from 1F800H), eight
2k x 4 RAMS (address starting right after the last address of the ROMs) and one 8251A
USART (base address 7800 H, 7801 H). Implement the even - odd addressing. Show the
memory map and the connection schematic. (23)
(b) Sketch and explain the timing diagram of the read cycle of 8086. (12)
2. (a) Interface an 8086 microprocessor to a 8 level paper tape reader through the PORT A
of an 8255A PPI in such a way that whenever data is read from the tape the 8255 A sends
an interrupt to the IR6 pin of an 8259 PIC. If the base addresses of the 8255A are F009H,
FOOBH, FOODH and FOOFH while the base addresses of the 8259 PIC are FOOAH ad
FOOEH, respectively, draw the connection diagram of the system using DECODERS
(IC74LS138) only .. (15)

(b)Write assembly codes to initialize the 8259 PIC andthe 8255A-PPI properly so that
there is a type 38 interrupt request when a data is read by the 8255A-PPI. Initialize the
rest of the ports of the 8255A in mode O. (15)

(c) Write a code snippet for the function called during the interrupt so that data is read
from the tape connected to the PORT A of the 8255A. , (5)
8259 Control Words
........ .'.
.•.
,..•.1)6.•...•• '.D4'
...
Dj.'" Dz. ., D1 ..' Do .'.
.;\S . ,J\o.
".
;' ,,cO}),'" •.,1
'1)5,;" ,. , ~
.: ,.- . . . .. .....
,'.
,tQwl? '() A7 A6 As 1 LTIM ADI SNOL IC4

,lCW2 .... 1 AIS/T7 A141T6 Al3lTs A}2!T4 AII/T3 AlO A9 As
Ss S4 S3 S2 S] So
i']CW~, 1 S7 S6
0 0 0 SFNM BUF MIS AEOI IlPM
:<'ICW4'~ 1
Ms M3 M2 M] Mo
'iQOW.1'" 1 M7 M6 ~
OtW2' 0 R SL EOI 0 0 L2 L1 Lo
3. (a) Describe the functions of the DSR, DTR, RTS, CTS, TxD and RxD signals
exchanged between a terminal and a modem. . (10)

(b) Write down the instructions of transmitting and receiving data through 8251A' using
polling method if the control register and data register addresses of the 8251 are FFF2H
and FFFOH, respectively. (10)

Contd P/2
=2=
EEE315
Contd .•• Q. No. 3(b)
8251 Control Words
82 S1 EP PEN L2 L1 82 81
EH IR RTS ER SBRK RxE DTR TxEN
DSR SYNDET FE OE PE TXE RXRDY TXRDY
(c) Why must you use an lRET instruction rather than the regular RET .instruction at the
end of an interrupt services routine? (5)
(d) What response will an 8086 microprocessor show if it receives a divide-by-zero
interrupt exactly at the same time when an NMI occurs? Why? (5)
(e) What is the purpose of interrupt vector table? What.is its range in the SDK Board?
How many interrupts can it accommodate? (5)
4. (a) Draw a circuit diagram using timer 0 of an 8254 timer/counter IC that can be used"to
determine power line failure for an 8086 system considering the internal addresses of the
8254 to be FFOOH, FFOIH, FFI0H and FFllH, respectively. If the power line signal is
220 V, 50Hz and the 8254 is connected to a 1 MHz clock, what can be a possible count
value loaded to the counter and why? In which mode will you operate the counter? Write
an assembly code to initialize the counter . (20)
. 8254 Control Words
I SC1 I SCD I HW1 I RWO I M2 M1 . MO BCD I'

(b) Describe all the methods of reading the count value from the 8254 counter. (15)
SECTION-B
5. (a) Design a system with 28 x 8 LED matrix, shown in figure for Q 5(a), and a
micro controller, so that the system can display a 8x 16 image. Also, write a program for
that microcontroller system that can display an 8 x 16 image stored in the memory in the
following manner: Each 8 LED row is represented by an 8 bit unsigned inte~er, where
each bit of the integer represents the ON or OFF state, total 16 integers are given in an
array A, representing each row. Use appropriate delays in your code, and in comment,
explain why the particular delay values were used.
Char A[] = {OxAB OxBC ... } i/ image array
(you do not need to declare A, assume it is already defined in code. Also, do not redraw
the LED matrix, and use bubbles to show connections) (15)
,"
Contd P/3
=3=
'/ ERE 315
Contd •.. Q. No. 5(a)
- ""0' _ ...-= _ _ W" _
!;
Figure for Question Sea)

(b) For the given H-bridge motor driver, design a microcontroller system, that has 2
switches. Pressing switchno 1 will toggle the On/Off state of the motor. Pressing switch
no 2 will reverse the direction of rotation of the motor. For your design, use the pI, p2, p3
and p4 bubbles, and do not redraw the H-bridge. Write appropriate code for the system. (15)
R1 R3
p1 p3
lk 1k
R2 R4
p2 p4
1k lk
Figure for Question S(b)

(c) What are the differences between a microprocessor and a microcontroller? (5)
6. (a)The following statements are part of a continuous program. Fill up the values of the
appropriate flags after sequential execution of each instruction. (15)

(i) ADD AX, ex
(li) ADD BX, AX
"
,
,
(iii) SUB BX, Ih
(iv) INC BL
(v)NEGDX
(vi}DIV CX
(vii) TEST DX, DX
Contd P/4
=4=
EEE 315
Contd ••• Q. No. 6(a)
--
ZF SF CF OF PF AX BX CX DX
Initial 0 0 0 0 0 OOOOh FFFFh 800th OOOOh
i.
.
ii.
.
iii.
iv.
v.
vi.,
vii.
.
(b) A DB r, t is a complex number given in polar fonn (r L t). r and t are arbitrary
constants in decimal form, t given in degree. Write an assembly program that will,
multiply two such complex numbers A and B and put the result in M and divide A by B
and put the result inD, whereB, M and D are also polar form complex number defined in
the same manner as A. (10)

(c) The address C82F: 1000 contains an instruction. (i) What should be the value of IP for
a program to execute that instruction, if value of C8 for that pr~gram is COOOh?(ii) What
can be the minimum value of CS of a particular program, for which the instruction
C82F: 1000 can be executed by that program, without help of any jump commands. (10)'
7. (a) For each of the following statements state the addressing mode of the source and
destination operand. If the instructions are executed sequentially, write the content of the
memory after execution of all the instructions. (10)
Memorv Offset . Content

1000h 12h
lOO1h 45h
1002h 34h
lOO3h 67h
lOO4h 78h
100Sh 17h
lOO6h 23h
Instructions:
(i) MaV BX, I b03h
(ii) MaV AX, [BX]
(iii) MaV 81, 1004h
(iv) MaV DI, 81
(v) XCHG [81], [DI]
(vi) MaV [81], [1005]
Contd PIS
~(-./.
!;.
";'
=5=
EEE315 -
Contd eo. Q. No.7
(b) Consider the following code. What will-be the value of R after execution of the code?
The code performs a function. State what is that function. (10)

MOV AL, 1
MOVBL,N
CALL Proc1
MOVAL,R f'/1 0 V ~,AL
HLT
Proc1:
- -TEST BL, OFFh
Jb; rett: IJ 1- ~:i
MULBL
DECBL
CALLProc1
retl-: RET
NDB5
RDB?
HLT
. (c) Define with examples: (any three) (15)

_(i) Immediate Addressing
--(ii) Unconditional Jump
(iii) Register Indirect Addressing
(iv) Divide Overflow
8. (a) A palindrome is a word or phrase that may be read the same way in either direction.
(Example "MADAM 1M ADAM"). Write an assembly program that will test a string
whether it is a palindrome. (spaces are ignored while testing for palindrome) (15)
(b) In the assembly code given in table, there are some syntax as well as logical -errors.
Find the errors and correct them with proper explanation. Note that the first of the two
erroneous statements is always correct, and all other consecutive statements must be
corrected if necessary. Provide the corrections in a tabular form given in the Figure for
Question 8(b). (15)
Contd P/6
=6=
EEE315.
Contd ••• Q. No. S(b)
Line No Correct Instruction Ex lanation
Answer to be written Answer to be written

inside the table in inside the table in
answer script answer script
Figure for Question 8(b)
ALPHA SEGMENT
ASSUME CS : CODE, DS : CODE
MOVDX,AH
MOV AX, 12
MOVBX, [AX]
MOV AL, [BL]
ADD AL, [SI]
ADD ex, [DI]
PUSHAL
PUSHF
ALPHA ENDS
(c) Write two separate assembly codes each of which would generate infinite loop in an
8086. (5)
, .- ~.do'\1>,
L-3/T-,2/EEE
, Date: 09/06/2014

, The figures in the margin indicate full marks.
SECTION-A
"
1. (a) Consider the message signal, m(t) = lOcos2000JZt + 1Ocos4000JZt . The message
signal is sampled and then passed through a flat-top filter having impulse response
h(t ) ~ rr(~) to obtain a PAM signal, where , is the width of ~ pulse. What is the
minimum sampling rate to recover the message signal from the PAM signal? Assuming
the sampling'rate of the message signal is 8000 Hz, draw the frequency spectra of the
PAM signal for (i) 't = 0.5 ms, (ii) 't = O.l' ms and (iii) 't = 0.05 ms. If there is no
equalizer at the receiver then which value of 't will you choose for Jransmission and
reception of the message signal using PAM technique? Write down the expressions of
the transfer functions of the equalizers for three valuys of't. Which flaHop filter and
equalizer will you choose and why? (18)
(b) What are the differences between multiplexing and ~ultiple access? Twenty voice
source need to be multiplexed using TDM. The bandwidth of each source is 4 kHz.
What should be the sampling rate of the commutator of the TDM circuit? What is the
.
bandwidth of, the TDM signal if instantaneous sampling' with pulse width r ~ 0 is
considered? How the bandwidth of the TDM signal can be reduced? What is the
required bandwidth ifFDM is used instead ofTDM? (10)
(c) Compare among the unipolar NRZ, polar NRZ, unipolar RZ, AMI and Manchester
line coding techniques in terms of their merits and demerits. (7)
2. (a) What are the limitations of delta modulation? How the limitations can be minimized? , (7)
(b) A communication system with delta modulation can support maximum data rate of 5
'kbps. The message signal to be transmitted is shown in Fig. for Q. 2(b). Determine the
value of the' level height I:i for which both the slope-overloading and granular noises are
I
minimized and the system have the maximum data rate. (10)
o
-10
Contd P/2
=2=
EEE 309
Contd ... Q. NO.2
(c) The message signal m(t)=IOcos2000m is sampled at 300% higher rate than the
Nyquist rate for DPCM. The maximum value of the error signal of DPCM is found to be
2. Determine the bit rate of DPCM to achieve signal to quantization noise ratio (SQNR)
of30 dB. What will be the SQNR ifPCM is used instead ofDPCM with the same no. of
levels in quantization? (18)
3. (a) Draw the block diagrams of QPSK modulator and demodulator. Draw the typical
waveshapes of all the signals that exist at different points of mod,ulCl:torand demodulator
for an input data stream x = [10011100]. (20)

(b) The symbol duration and the received energy per ~ymbol of ASK,. BPSK and QPSK
modulation and demodulation (coherent) schemes are taken to be 1 Jls and 1O-18J. The
energy of noise per bit is 10-19J. Determine the data transmission rate and bit error rate
(BER) for each of the modulati<?n schemes. If the duration of symbols are doubled for
QPSK modulation keeping the same received power, what will be the data transmission
rate and BER for this modulation? The Q-function can be approximated as . (15)
1 ( 0.7) e _x;{
Q(x ) ~ & 1- -2 2: Also comment on the results. "
. x 27£ X
4. (a) Compare among the TD¥A, FDMA and CDMA systems in terms of their merits
and demerits. (12)

(b) There are two transmitter-receiver pairs in a DS-CDMA system. The transmitters
and receivers use 4 chip Walsh Codes. For bit sequences Xl = {101} and x2 = {110} of
the transmitters, draw the waveshapes of the transmitted signal of each transmitter and "
the received signal, decoded signal and decoded bit sequence at each receiver. (18)
(c) Write down the advantages and disadvantagesofDSSS and FHSS techniques." (5)
SECTION-B
5. (a) Define modulation index for an AM signal. Comment on the limitations of DSB-SC
modulation and the ways to overcome them. Draw- an AM waveform for tone
modulation when fc = 10KHz, fro= 100 Hz, carrier amplitude is 3 V, arid Jl = 1.1. Here,
the symbols denote their usual meaning. The figure must be clearly labeled and drawn
approximately in scale. How can you recover the modulating signal from this waveform
using envelope detection? (20)

, ..... Contd P/3
..•
• -" to
=3=
EEE 309
Contd ... Q. No.5
(b) A general communication channel supports 60 users, is able to allocate a bandwidth

of 4 KHz to each user, and has a channel SNR of 9 dB. If suddenly the number of users
is quadrupled, and as a result, chann~l noise power is tripled, how cariyou keep the
channel capacity from beiqg affected? Assume that signal power for the scheme can not
be changed. (15)
6. (a) What are the benefits of using switching modulators in an AM system? Explain the
differences between diode-bridge and ring modulators with diagrams. (14)
(b) Give real-life examples of different types channel (media) available to a general
communication system. (6)
(c) Explain the role of and the relationship between vestigial and equalizer filters in
VSB modulation. For a VSB modulator, the vestigial filter Hj(ro) has a transfer function
which is shown in the figure below. The baseband signal bandwidth is 4 KHz and
carrier frequency is 10KHz. Find the corresponding transfer function of the equalizer
filter Ho(ro) needed in a VSB receiver for distortionless reception. The figures must be
clearly labeled and drawn in scale. (15)
- -- -- -- .- -_ .. _._.-
.1-.".....
._v _ ~.... ~ .. ~ ~ 'oH, "l- 14''''.''L6
p.. , e. -90 --r tQ. b (~.)
7. (a) Derive the expression of a narrowband FM signal and compare it with the expression
of an AM signal. Discuss how a narrowband FM signal can be generated with AM
transmitter components. ..Also, explain why the concept of 'complex envelope' is
necessary to define a wideband FM system. (18)
(b) A carrier wave of frequency 100 MHz is frequency-modulated by a sinusoidal wave
of amplitude 20 V and frequency 100 KHz. The frequency sensitivity of the modulator
is 25 KHz per volt. (17)
(i) Determine the approximate bandwidth of the FM signal using Carson's rule.
(ii) Determine the bandwidth -by transmitting only those side frequencies whose
amplitudes exceed 1 percent of unmodulated carrier amplitude.
Contd P/4
,,
.',
=4=
EEE 309
Contd •.• Q. No. 7(b)
(iii) Is there any other way to estimate the FM signal bandwidth?

(iv) Repeat the calculations if modulating signal amplitude is doubled.
(v). Repeat the calculations if modulation freq!1ency is doubled.
Necessary curves for this question is attached.
8. (a) Explain the operation of a Foster-Seeley detector with circuit and phasor diagrams. (12)
(b) (i) A sinusoidal signal, with an amplitude of 3.25 V,. is applied to a uniform
quantizer of the midtread type whose output takes on the values of 0, :tI, ::t2,::t3
volts. Sketch the waveform of the resulting quantizer output for one complete
. cycle of the input. If other parameters are needed, assume suitable values for
them. (9)
(ii) Repeat the evaluation when the quantizer output takes on. the values of ::to.5,
:t1.5, :t2.5, ::t3.5 volts. What will be the type of this form of uniform quantizer?
(c) The signal m(t) = 6 sin(27lt) volts is transmitted using a 4-bit binary PCM system. It .
. .
uses a midrise quantizer with I volt step size. Sketch the resulting PCM wave for one
complete cycle of the input. Assume a sampling rate of four samples per second, with
samples taken at t = ::tl/g,::t3/g,::ts/g, seconds. (14)

(/j.
40
20
2 ----~--------------------~-------~---.--
O .... J - 1 , t I .1 I i I I I ; J-1 ,f 1 I
0.1 _ 0.2 0:4 .6.8 1.0 2 4 6 8 10 20 40
~,:j-Cb) .
~,
-,
I.
.<."
L-3ff -2/EEE Date: 19/05/2014


___ ..__ _H_. ._ _ ..__ - ..-.- ---- ..--.- ---.--.-.-------
SECTION-A
Assume reasonable data if necessary. Symbols used have their usual meanings.
Provide necessary comments in assembly language codes.
1. (a) Explain how does an 8086 microprocessor read data from or write data to an odd
addressed m~mory location. Provide suitable examples. (10)

(b) Design an 8086 based system to implement interrupts of type 47 and 93. Choose
suitable base address(es) from the range FEFOH - FEFFH. Show the system connection.
Design the address decoder using basic logic gates. Write an appropriate assembly code
snippet for initialization of this system. (20)

(c) Why is it necessary to send an End ofInterrupt (EOI) command to an 8259A at some
time in an interrupt-service routine? (5)
2. (a) Design a display board containing 8 common cathode (CC) seven segment displays
(SSD), which are to be operated using multiplexing technique. Use only PORTB of an
825.5 A PPI (with base address 9A59H) for multiplexing and transmitting data from an
8086 microprocessor based system to the display board. Assume that each segment
consumes 25 rnA at 1.5 V. Show the connection between the board and PORTB of the
8255A. (15)
(b) Write an interrupt service routine in 8086 assembly hmguage which will refresh the
display board. Assume that the procedure will be called every 2 ms by an interrupt
- signal to IR3 of an 8259A. Also assume that data to be displayed is taken from an 8
element byte array named DISPLA Y_DATA. (10)

(c) Describe the procedure that an 8086 microprocessor will follow when it responds to
an interrupt. (l0)
3. (a) Suppose that an 8254A timer/counter IC is to be connected and programmed in such

a way that it produces an interrupt in every 20 ms. This interrupt signal has interrupt
type 47 and is to be connected to one of the IR inputs of an 8259A PIC. Assume the
base address for the 8254A is FEFIH and that for 8259A is FEFOH. The input clock
frequency for 8254A is 4.9152 MHz. (20)

Contd P/2
=2=
EEE315
Contd ••• Q. No. 3(a)
(i) Show the system connection between 8254A and 8259A with appropriate
address decoding for both.
(ii) Which IR input of 8259A is to be connected with this interrupt signal?
(iii) Write an assembly code snippet to initialize the 8254A IC for this desired
operation.
(b) Explain why it is necessary to initialize an 8251A USART with a worst-case
initialization sequence. (8)

(c) How can you step through the instructjons of an interrupt seryiceroutine? Explain. (7)
4. Suppose that two computers are to be connected to each other through two 8251A
USARTs. The base address for the USART of system-I is FOEOH and that for system-II
is FCFOH. The input clock frequency for both USARTs is 614.4 kHz.
(a) Show the connection diagram between 8086 microprocessor-buses and USART for
both systems (Address decoder circuit is not required) and between the USARTs.(12)
(b) A serial communication is to be established with 9600 bauds ,per sec~nd, 7 bit'
character length, one stop bit, even parity, enabled error reset, disabled hunt mode
and no break character. Choose other options as the situation demands. Construct
the mode and command words that must be sent for the USART of system-I. (8)
(c) Write an assembly language procedure for system-II to receive a ten character
string from system-I using polling method. Keep provision for checking parity,
framing and overrun error (assume that another procedure RESEND_DATA will
be called if any error occurs; you need not write this procedure, just use it
whenever it is necessary.) (10)
(d) Assume that an 8254 IC is to be used to generate the desired USART clock
frequency from a source clock frequency of 1-1.0592 MHz. Write an assembly
language code snippet to initialize the 8254 for this purpose. Assume the 8254 has
the base address FBOOH. (5)
SECTION-B
-
5. (a) "8086 is a 16-bit microprocessor" - Explain. (10)
(b) Explain using example, how 20-bit physical address is accessed by 16 bit registers. (10)
(c) Determine the values of CF, Sf, ZF, PF and OF for the following instructions.
Assume that the flags are initially 0 for each part. (15)
Contd P/3
'" .
•
=3=
EEE315
eouid ... Q. No. S(c)
(i) NEG AX; where AX contains 8000H

(ii) SUB AX, BX; where AX contains 800H and BX contains OOOlH
(iii) RCR AX, 1: where AX contains A055H
(iv) MUL BL; where AL contains 80h and BL contains FFH
. (v) TEST AX, OFFFFH; where AX contains OOOOH.
6. (a) Point out the errors in the following code segment and explain the reasons: (10)
MOV AL,05H
MOVBX,AL
MUL 10
MOV [BXJ, 1
MOVSI,OFH
ADD AX; 2[SIJ
PUSHAL
DONE?: SHL AL, 2
TEST AL,AL
JZDONE?
HLT.
(b) Write an assembly code to test whether the number stored in AX is a perfect square
or not. If it is a perfect square, put 1 in DX, otherwise make it O. (10)

(c) Write an assembly code, that will insert STRING2 into STRINGl at a point
specified by CX. For example, STRING 1 = PRAM, STRING2 = RaG, CX = 1. After
execution, STRING 1 = PROGRAM. (15)
7. (a) Determine the addressing modes of each operand of the following instruction. (5)
(i) MOV BX, [BX]
(ii) ADD AX, 5
(iii) MOV AX, 2 + [SI]
(iv) MOV AX, W + [BX]; W is a word variable
(v) ADD AX, 5 [W+BX + SI]; W is a word variable
(b) Assume that CT is a byte type array which contains 4 class test numbers of a student.
Write an assembly code to find the average number of the best three class tests, which
will be stored in AL. If the average is a fraction numb€r, then the result should be
rounded version of the average. (15)

Contd P/4
=4~
EEE315
Contd •••Q. No.7
(c) Assume that A and B are two word type array which contain two 2x2 matrices.
Write an assembly code to check whether B is inverse matrix of A. If yes, make ex = 1
and 0, otherwise. Remember that, AA-1 = I, where I is an identity matrix of same order. (15)
8. (a) What are the differences between a microprocessor and a microcontroller? (5)
(b) Assume, we have a microcontroller (e.g. ATMega 32) and four sevt:n segments and
two push buttons. We want to design a manual car counter display for a parking lot. The
seven segment displays will show the number of cars in the parking lot. If the operator
presses button "one", the display will show increase in the number of car. If any car
leaves, the operator will press button "two" and the display will be changed accordingly.
If the count reaches 1000, which is the limit for parked car, the display will show
'FULL'.
(i) Draw the connection diagram to implement the design. (10)
(ii) Write the algorithm which you want to use. (10)
.(iii) Write a e code which will perform the desired operation. (10)
8259A PIC Control Words:

AO D7 D6 D5 D4 D3 D2 D1 DO
leWl 0 A7 A6 AS 1 LTIM ADI 8NGL IC4
ICW2 1 AISff7 A14ff6 A13ffS A12ff4 Allff3 AlO A9 A8
ICW3
1 87 • 86 8S 84 83
Master S2 SI SO
ICW3
I 0 0 0 0 0 ID2
Slave IDI IDO
ICW4 1 0 0 0 SFNM BUF
l. MIS AEOI ~PM
OCWl 1 M7 M6 MS M4 M3/ M2 Ml MO
\
OCW2 0 R SL EOI 0 0
{
L2 Ll LO
OCW3 0 0 ESMM SMM 0 1 P RR RIS
8255A PPI Mode Set Control Word-

D7 D6 D5 D4
-
/ D3 D2 D1 DO
Mode set PORTA MODE PORTA PORTC PORTB PORTB PORTC
Flag I/O . (U) I/O MODE I/O (L) I/O
L,:,3/T-2/EEE Date: 08/12/2014
BANGLADESH ,UNIVERSr~y OF ENGINEERING AND TECHNOLOGY, DHAKA
Sub: EEE 309 (Communication
i
Theory)
_ .. _._ __ ..__
USE
.. _
SEPARATE
__ R_.
SCRIPTS FOR EACH SECTION
._ ._. __ __ M._ _
. SECTION-A
Answer in brief and to the point. Symbols have their usual meanings. Fig. attached for Q.
4(a)
1. (a) Name the two major fundamental limitations of a communication system. Define
information, I, carried by a multi-level information-bearing signal with equally spaced
interval in a time span of T seconds and derive the expression for system capacity, C.
Comment on what poses the limit to the information transmission and how they are
related to the fundamental limitations you have mentioned above. (12)
(b) What is the function of a communication channel? Name the two types of distribution
or impairment a communication channel can cause to an intelligence signal. Calculate the
attenuation and delay for each frequency component of the input signal
x(t) = 0.6 cos(2400 m) + 0.5 cos(3000 m), + 0.8 cos (3600 1tt), as it passes throp~h a
communication channel with the following propagation characteristic:
'p 6001r
y=a+j=-.-+j
W
'(0 .05w+--,w
.
10,-5
21r
J 2
Can the .channel pass the signal, x(t), to the destination without distortion? (13)
(c) Explain, with suitable sketches, how the signal distortions caused by a communication
channel are mitigated in a practical communication system.' (10)
2. (a) What is noise? Distinguish between noise and interference. Calculate the maximum
available thermal noise power (N, in watt) that a resistive.termination in a standard band-
limited telephone channel (300 Hz - 3400 Hz) will produce at 27°r;. (Boltzman
constants, k = 1.38 x 10-23 lIOK) . (15)

Define signal to noise power. ratio (SNR) in dB. What is the acceptable level of SNR in
dB for analog speech signals in a telecommunication channel? Compute the signal power,
. S, in watt, required to achieve the acceptable SNR for the noise power, N, obtained as
above.
(b) Mention the most major limitation of an analog communication system. With
appropriate attenuation characteristics of lossy and lossless communication channels as a
function of distance, explain in brief, the said drawback and possible suggestions for
improving the performance using amplifier(s). Which suggestion is adopted in a practical
analog communication system and why? (15)

Contd P 12
=2=
EEE 309
Contd ••• Q. No.2
(c) Using Shanon's maximum capacity theorem, explain how in 1939, A. H. Reeves of
Bell Laboratories did suggest the basic principle of overcoming the majorlimitation cited
in part of Q NO.2. (5)
3. (a) What is modulation? Mention the major purposes of modulation in brief. Calculate the
size of the antenna for transmitting an analog baseband signal of 20 kHz frequency in
.
wireless communication. Compute the same for a 3 MHz signal frequency and comment
on which antenna is suitable for practical use. (5+5)
(b) For a single-tone modulation, met) = Amcos(2nfmt), carrier wave,
c(t) = Ac cos(2nfct); write down the equation for the amplitude modulated wave and
derive the expression for the efficiency (11= sideband power Itotal power) of a standard
amplitude modulator in terms of the modulation index rna. If an AM wave is represented
by set) = Ac(l +0.3 cos(2nf1t) + 0.4 cos (2nf2t) + 0.5 cos(2nf3t)]. cos(2nfct)].
Calculate the overall modulation index, rna, and determine the efficiency of the amplitude
modulator. (7+8)
(c) Write down the equation of an SSB-SC signal for a modulating signal met). De:::~.;be
the corresponding coherent detection technique and the problem of synchronization.
"Although the standard amplitude modulation is both wasteful of power and bandwidth
compared to SSB-SC modulation" - Why is the former used in practical AM
broadcasting? (8+2)
4. (a) Define FM and PM with appropriate equations. Sketch FM and PM waves produced
by the sawtooth wave as shown in Fig. For Q. No. 4(a). (Assume A = I V and T = I
second.) n1(1) (4+6)
F:a' ~ IJ-. NO. 4(~.J

With appropriate equations and.block diagram, explain how you,can achieve FM using an
available phase modulator.
_ (b) Describe, in brief, the direct method of generating FM. (10)
(c) Derive the Fourier series representation of the singletone FM wave for an arbitrary 13.
Simplify the equation for a narrow band approximation. / (8+4+3)

Contd P/3
=3=
EEE309
Contd eo. Q. No. 4(c) . "
Compute the bandwidth of an FM wave for an intelligence signal met) that has a
frequency' band of 300 Hz - 3400 Hz from the simplified equation derived above. Also, j ,
compare the two major advantages of FM over AM.
SECTION-B
5. (a) A PCM system generates a bit sequence [10011011], which is to be transmitted using
DPSK modulation. Assume that the encoding scheme uses the princ~ple of '9' me~s
transition and the reference bit is 1. (15)
(i) Draw the block diagram of the transmitter and the receiver of the DPSK system. ,
(ii) Determine the encoded bit sequence, phase of each encoded bit and the detected
bit sequence.
(b) An ASK based digital communication system transmits Ao cos wet ad Al cos wet for
bit 0 and bit 1, respectively. Draw the block diagram of the tr~smitter and the receiver of
the system. Write the expressions of the signals at each point of the transmitter ar<1the
receIver. (14)
(c) Compare ASK, FSKand PSK in terms of bandwidth requirement and noise
performan~e. (6)
6. (a) A DS-CDMA system with 4-trasmitter-receiver pairs uses.PN,sequences,of 128 Cl.tips

long. If each of the transmitter-receiver pairs has a bit rate equal to
., 64 ,kbps .requiring
32 kHz bandwidth for direct bit transmission, (12)

(i) Calculate the bit rate and the chip rate of the system?
(ii) What is the bandwidth requirement for the DS-CDMA system? What woul~ have
been the required bandwidth if TDMA were used?
(b) With necessary diagram, explain why an FH-CDMA system is called spread-spectrum
system. Why is an FH-CDMA system difficult to jam? (8)
(c) The detected bit sequence by receiver 1 of a 2-user DS-CDMA 'system is [1 0 1].
Let the signals in the channel corresponding to the 3-bits are presented as [+ 2 0 - 2 0],
[- 2 :- 2 0 - 2] and [- 2 + 2 0 + 2], respectively. The two PN sequences used by the
system are [1 0 0 1] and [0 1 1 0]. Detemline the PN sequence used by the receiver 1.
If the receiver 1 uses the other PN sequence, what will be the detected bit sequence and
how many bits will be erroneously detected? (15)
, Contd P/4
=4=
EEE309
7. (a) For an uniform symmetric L-level quantizer, derive the expression of
signal-to-quantization-noise-ratio (SQNR) in terms of signal power P and step size /1. (10)
(b) A DPCM system with a symmetric message signal met) of amplitude Am generates
error signal (comparator output) e(t) in the range of + Em to - Em. LetPm and Pe denote
the power ofm(t) and e(t), respectively. (18)

(i) Assuming equal number of quantization levels for both PCM and DPCM systems,
show that the SNR improvement in DPCM over PCM system is proportional to Pm/Pe•
(ii) For keeping the SNR of DPCM system equal to that of PCM system, show that
the reduction in the number of quantization levels in DPCM is proportional to EmlAm.
(c) Consider anFDM system with a channel bandwidth equal to 200 kHz. If the system
requires guardbands equal to 500 Hz and each source has a baseband spectrum at
300 -3400 Hz, calculate the number of sources that can be multiplexed over the system. (7)
8. (a) State four desirable properties of line coding schemes. For each of these properties,
identify one suitable line coding schemes and explain the reason of suitability. (8)
(b) A 3-bit PCM system with input met) = 4sin 4nft uses Il-law non-uniform quantization.
The compressor uses Il = 255, whereas the quantizer is of mid-rise type with a ste. ,:!ze
equal to 1 volt. (15)

Calculate the quantized output at the sampling instances t = O,:t 1/8, :t 2/8, :t 3/8 seconds.
Compare these values with the outputs if uniform quantization were used.
(c) A digital audio system records audio signals digitally by using binary coded PCM
system. Assume that the audio signal bandwidth equals 20 kHz. (12)
(i) If the signal is sampled at a frequency twice that of Nyquist rate and the samples
are uniformly quantized into L = 65,536 levels, calculate the bit rate for the system.
(ii) If the audio signal has average power of 0.1 watt and peak voltage of 1 volt, find
the resulting SQNR of the system.
(iii) Calculate the required bit rate of the system for achieving an SQNR 20dB higher
than the one calculated in part (ii).
----------------------------------------
'.
L-3/T -2/EEE Date: 06/01/2015
BANGLADESIi. UNIVERSI:ry OF ENGINEERING AND TECHNOLOGY, DHAKA
L-3/T-2 RSc. Engineering Examinations 2012-2013
. Sub :EEE 315 (Microprocessor and Interfacing)
,_,,,~ '''''H. M''''''''' ''''''''' __ '''''''''''' . -_ ••••••••
_ ••••_ ••••__ ._-_ •••••••••••
__ ._-_ ••••_._-_ •._ •••••••••..•••••••••.•.•..••••••••••
SECTION-A
Control words for peripheral devices are attached.
1. (a) What are the functional components of 8255 programmable peripheral interface
device? (5)
(b) A permanent rn:agnet dc motor is controlled through PBO, PB1 of 8255 having a base
address of 80 H. Write an assembly program that would scan command inputs from port .
A at PAO, PAl and operate the motor according to the following function table. (30)
PAO PAl PBO PBI
Run Clockwise 0 1 1 0
Run anti Clockwise 1 0 0 1
Stop running 1 1 0 0
Devise a scheme for the inputs and control circuit of the DC motor using appropriate
devices and circuit components.
2. (a) With a neat diagram explain the functional blocks of8251 USART. (10)
(b) An 8086 microprocessor board has onboard 8254 (programmable Timer) and an 8251
. (US ART), and is connected to a PC thorough RS-232 serial port. The serial
communication requires a band rate of 1200 for both TXC and RXC, 7-bit character
length, I-stop bit and even parity. The baud rate is supplied from counter 0 of 8254
having a clock input of 1.0 MHz. Consider 16-bit addresses for both 8254 and 8251. (25)
(i) Write an assembly program to configure both 8254 and 8261 making the system
ready for transmission and reception of data through the USSART.

(ii) Write an assembly program so that on reception of data (command code) from PC
the microprocessor will
(l) configure counter 1 for programmable clock out at a rate of 100 kHz if
received word is decimal 1,

(2) Configure counter 1 for programmable clock out at a rate of 20 kHz if
received word is decimal 2.
(3) Halt the processor if received word is O.
3. (a) A system utilization an 8259 (Priority Interrupt Controller) in an 8086 microprocessor

board to generate interrupts 43,44 and 45 assigned to suitable 8259 interrupt inputs. The
hardware interrupts in tum produces software interrupts of INT 100, !NT 200 and !NT
250. (25)
Contd P/2
=2=
EEE315
Contd ••. Q. No. 3(a)
Write an assembly program to serve the interrupts and interrupt service routines so that
INT 100 resets the 8086 processor, INT 200 pushes the flag-register into the stack and
INT 250 POPS stack data into AX register.
(b) What are the special features of DSP processors over general purpose
microprocessors? Under what circumstance do you recommend DSP processor for an
application? (10)
4. (a) With neat diagram explain the memory organization of AT89C52 microcontroller. (10)
(b) Design a system using AT89C52 microcontroller to blink "EEE" on three 7 segment
LED displays connected to PO, PI and P2. Draw the system schematic along with
necessary interface devices, and write a program with C-Ianguage consisting SFR
deflections available in AT 8952-h file. (25)
SECTION-B
Assume reasonable any missing data. Symbols carry have their usual meaning.
5. (a) Draw the internal architecture of the Intel 8086 microprocessor. Also mention the
components of the execution unit and discuss their roles. (30)
(b) How can we endure an even address for a word variable in assembly language?
Explain why it is necessary to do so in light of the memory banking system of an 8086
microprocessor. (5)
6. (a) Explain the roles of ALE, MilO, READY and BHE signals in the execution of a basic
instruction of an 8086 microprocessor. (10)
(b) Write an .assembly language code which will take the length of three sides of a
triangle AB, BC and CA as inputs and will check whether the triangle is a right-angle
triangle or not. If it is a right-angle triangle then the program will set carry flag or it will
clear carry flag. Assume the lengths are word variables and their products will fit in 16
bits. (15)
(c) What are the difference between 'near' and 'far' procedures in 8086? Write a procedure
which will toggle the cases of a character array. (10)
7. (a) What is 'memory segmentation'? Explain why a logical address is not unique? (10)
(b) The purpose of the following code snippet is to calculate the sum of the following
series: 1 + 1 + 1 + 1 + ... + 1
'N' is the number of terms to be added. What will be value of AX ifN is set to zero. What
can be done to avoid such output? Rewrite the corrected code. (10)
Contd P/3
=3=
EEE 315
Contd •.• Q. No. 7(b)
NEQU5
CODE SEGMENT
ASSUME CS:CODE, DS:CODE
MOVAX,CS
MOVDS,AX
MOV ex, N
MOVAX,O
LOOPl: ADD AX, 1
LOOP LOOPI
HLT
CODE ENDS
END
(c) Determine the value of AX ifMUL BL is executed when AL contains OABH and BL
contains lOH. Also determine the values of CF and OF after the execution of this
instruction. , (5)
(d) Determine whether the following instructions are correct or wrong? If wrong, give
explanation and correct the instruction if possible. (10)
(i) PUSH OA2F4H

(ii) ROL AL, 5
(iii) DIV 02H
(iv) MOV AX, [DX]
(v) RET 5
. 8. (a) Design an 8086 microprocessor based system with eight 4Kbytes ROMs, two
16Kbytes ROMs and two 32Kbytes RAMs. Starting address of RAMs is OOOOOH.It is.
required to have 32Kbytes of ROM right after RAMs. The rest of the ROMs can have
any suitable starting address considering the operation of 8086 microprocessor.
Implement even-odd addressing. Show the memory map and the connection schematic.
Use ligic gates (of arbitrary number of inputs) to implement the address decoders. (25)
(b) Suppose SUB AX, BX is executed. For each of the following cases, give the resulting
.value of AX and tell whether there is an overflow or not. If there is an overflow then
explain whether it is a signed or unsigned overflow. (10)

(i) AX has 2143H and BX has 1986H
(ii) AX has 8BCDH and BX has 7lABH
ji;""
8255A Mode Set Control Word
D7 D6 I D5 D4 D3 D2 Dl DO
Mode Set PortA'Mode PortA I/O PortC (U) Port B PortB I/O PortC (L)
Fla!! I/O Mode I/O
8251 Mode Instruction (Asynchronous Mode)

I D7
S2 I ~: I?: I~~ I ~i I ~; I ~~ I ~~
8251 Command Word
D7 D6 D5 D4 D3 D2 Dl DO
ED m RTS ER SBRK RxE DTR TxEN
8251 Status Word

DSR SYNDET FE OE PE TxE RxRDY TxRDY
8254 Control Word

D7 D6 D5 D3 D2 Dl DO
SCI SCO RWI M2 Ml MO BCD
8259 PIC Control Words

AO D7 D6 D5 D4 D3 D2 Dl DO
ICWI 0 A7 A6 A5 1 LTIM ADI SNGL IC4
ICW2 1 A15rr7 A14rr6 A 13rr5 A12rr4 Allrr3 AI0 A9 A8
ICW3 I S7 S6 S5 S4 S3 S2 SI SO
Master
IC3 1 0 0 0 0 0 ID2 IDl IDO
Slave
ICW4 1 0 0 0 SFNM BUF MIS AEOI J,lPM
OCWI 1 M7 M6 M5 M4 M3 M2 Ml MO
OCW2 0 R SL EOI 0 0 L2 Ll LO
OCW3 0 0 ESMM SMM 0 1 P RR RIS
L-3/T -2/EEE Date: 23/01/2016

SECTION -A
Make reasonable assumptions on any missing data. Answer in brief and to the point.
1. (a) Why is line coding essential in digital communication systems? Name three line
coding schemes with self-clocking feature and discuss their relative merits and demerits. (4+7)
(b) The message signal met) of a 3-bit PCM system with ,u-law (,u = 100) based non-
uniform quantization is shown in Fig. for Q. NO.1. The quantizer is symmetric mid-rise
type and uses rounding operation. The sampling frequency is 2.5 kHz and the first sample
is taken at t = 0.2 ms. Calculate- (14)

(i) the quantization errors for the first 4 samples,
(ii) the quantization errors if uniform quantization were used and compare them with
those in part (i).
met)
(volts)
Fig. for NO.1 Q.

_._~~~-_._---------~-,-_._--
(c) What are the basic differences between DPCM and DM? A DM system with a
message signal m(t) as shown in Fig. for Q. NO.1 uses a sampling frequency equal to 10
kHz. Calculate- (4+6)

(i) the bit rate of the system,
(ii) the minimum step size for avoiding slope overload noise.
2. (a) Consider a PCM system with a sinusoidal message signal met) having values in the
range [-4, 4] volts and power equal to lOW. Message bandwidth is 4 kHz and the
sampling frequency is 150% higher than the Nyquist rate. The system uses uniform mid-
rise types symmetric quantization, (13)

Contd P12
•
==2=
EEE 309
(i) Calculate the required bit rate to achiever an SQNR equal to 20 dB,
(ii) If the sampling frequency is doubled, calculate the new SQNR,
(iii) If DPCM is used with the same bit rate as in part (i) and the DPCM error signal
lies in the range [-0.5, 0.5] volts, calculate the SQNR in dB.
(b) Draw the block diagram of a flat-topped PAM transmitter and receiver showing the
amplitude spectrum of the signals at each output of system, blocks. Explain why an
equalizer is necessary in a PAM receiver. (8+4)

(c) Consider a BPSK system with phase nl4 for bit '1' and n/2 for bit '0'. Deign and
draw the block diagram of the BPSK transmitter and the receiver. The answer should
include the decision criteria at the receiver. (10)
3. (a) Write short notes on- (10)

(i) T-carrier system
(ii) FH-CDMA system
(b) Consider a joint TDM-FDM system as shown in Fig. for Q. No. 3(b). The Bandwidth
of each source is 4 kHz and the sampling frequency is twice that of Nyquist frequency.
Source signals are digitized using 8-bit PCM system with A-law compression (A = 100). (17)
(i) Calculate the bit rate at the marked points PI to P6.
(ii) Calculate the TDMA frame durations and frame rates at point P3 and Ps.
(iii) If the bandwidth requirement at point P4 is 512 kHz, calculate the bandwidth
requirement at point P 6 assuming a guard band equal to 20 kHz.
, p - "--~-l
.1 Source I ~
i
I Source 2 ~ !
!
I Source 3 ~
"I Source 4 ~
:1 SourceS ~
TDM System FDM System
~ -'_ ~---------~~--------_._-----_.
•...........•..
(c) With necessary diagram, explain the multiple access interference (MAl) in a multi-
user DS-CDMA system. (8)
4. (a) Discuss the impact of increasing the order of digital modulations on the data rates,
bandwidth, bit error rate (BER) and power requirement of a digital communication
system. (10)
Contd P13
•
=3=
.EEE 309
(b) A bit sequence [1 a a 1 1 a 1 0] is to be transmitted using DPSK modulation with the

encoding principle 'Bit 1 means a transition'. Assume the encoded reference bit is '0',
phase '0' for bit' l' and phase '11:'for bit '0'. (12)
(i) Design and draw the block diagram ofthe DPSK transmitter and the receiver.
(ii) Show the phase sequence of the transmitted DPSK signal.
(iii) If for some reasons, the received phase sequence is [ 11:11:a a 11:11:a 0], Determine
how many bits will be erroneously detected.
(c) Consider a DS-CDMA system with 3 transmitter-receiver pairs having PN sequence
Cl = [0 a a 0], C2 = [1 1 1 1] and C3 = [1 a 1 0] respectively. Each Transmitter has a data
rate of 1 Mbps. (13)

(i) Determine whether the PN sequences are orthogonal to each other.
(ii) If the signal in the channel is [+1 -3 -3 -1 + 3 -1 -3 +1], determine the bit
sequence detected by receiver 3.
(iii) Calculate the data rate and the chip rate of the DS-CDMA system.
(iv) If 2 bits can be transmitted using 1 Hz, calculate the bandwidth requirement of
each transmitter and the complete DS-CDMA system.
SECTION-B
5. (a) What are the three major impairments in a communication channel? With appropriate
sketches, explain how distortionless transmission can be achieved in a communication
system ideally. Also mention how these impairments can be mitigated practically. (13)
(b) What are the sources of noise and interference in a communication system?
Characterize the thermal noise and intermodulation noise.
The input x(t) and the output yet) of a certain nonlinear channel is related as y(t) = x(t) +
0.0025x2(t). If m(t) = 2cos(1000m) + cos(200011:t), find the bandwidth of the output
signal. Also determine the intrermodulation products. (12)

(c) The signal power at the input of an amplifier is 55 ~W. The amplifier has a gain of
50, internal noise power is 5 ~W and external noise power is 1 ~W. Calculate the noise
figure in dB and the noise temperature of the amplifier. The room temperature is 27°C.
Also find the application of the terms 'noise figure' and 'noise temperature' in
communication systems. (10)
Contd P/4
=4=
EEE 309
6. (a) Characterize the following communication channels and state their particular
applicatons: STP cable and Fiber-optic cable. (10)

(b) Using DSB-SC modulator as a major component, generate SSB and VSB modulated
signals for a message signal of met). (12)

(c) An intelligence signal is met) = 1.2cos(400nt) + cos(IOOO1tt), if carrier signal is
C(t) = 2.4cos(200001tt), derive the expression of DSB-SC signal showing the sidebands
and determine the sideband power. Sketch the amplitude spectrum of DSB-SC signal and
after suppressing the LSB spectrum, show the USB spectrum and find its expression in .
time domain. (13)
7. (a) (a) Write the differences between (10)

(i) coherent and non-coherent demodulation processes and
(ii) homo dyne and heterodyne detection processes.
(b) In case of coherent detection, if the phase or frequency of local oscillator output
signal is different from input carrier's phase or frequency, what problems will occur? (12)
(c) Why non-coherent detection can not be used for DSB-SC signal? 'SSB modulation is
suitable for voice communication however VSB modulation is suitable for TV signals',
Explain.
Mathematically show that SSB + C can be detected non-coherently for a large carrier
signal. (13)
8. (a) What are the merits and demerits of an angle modulated signal compared to an
amplitude modulated signal. Show that phase and frequency modulations are inseparable.
For a message signal met) = 4cos(100m) + 20cos(2000m), write the expression of FM
and PM signals when the carrier is given as c(t)= 1Ocos(2nx 106t), frequency sensitivity kf
= 2000 and phase sensitivity kp = 2n. Also estimate the bandwidth of FM and PM signals.
(15)
(b) For a sinusoidal single-tone modulation, show that the bandwidth of the angle
modulated signal is infinite. (10)

(c) With block diagrams briefly explain the operation on an FM transmitter and a
superheterodyne FM radio receiver. (10)

L-3/T-2/EEE Date: 31/01/2016

SECTION -A
Assume reasonable data if necessary. Symbols used have their usual meanings.
Provide necessary comments "inassembly language codes.
1. (a) Explain in details how an 8086 microprocessor manages to read data from or write
data to a memory with a single read/write cycle. At which condition, does it fail to do
so? What can a programmer do to circumvent that condition? (25)

(b) Why does an 8086 microprocessor behave in a different way when an interrupt
occurs at its INTR input? Explain its response with suitable diagram(s). (10)
Provide suitable examples. (20)
3. Consider an 8086 microprocessor based system in which eight LEDs are connected to
PORTB of an 8255A PPI with base address 28B. Nothing else is connected with this
PPI. The odd LEDs and the even LEDs are to be turned on alternatively. (35)
(a) Write an assembly language code to perform the task.
(b) Also write a C language code for the same task.
(c) Based on the experiences gained from writing codes for the given task, discuss
advantages and disadvantages for both assembly language and high level language.
4. (a) Describe the asynchronous bit format used for serial data communication. (5)
(b) Explain simplex, half-duplex and duplex serial data system with suitable examples. (5)
(c) Suppose that you are asked to design an 8086 microprocessor based system, which
will serve as a real time clock (RTC). Draw the schematic with necessary components
(you do not need to show in detail how 8086 buses are obtained.) For display purpose,
use CA type SSDs. Write a procedure named INIT_ICS which will initialize the ICs
Contd P/2
=2=
EEE 315
Contd ... Q. No. 4(c)
required. Also write an ISR named RTC_INT which will update the second, minute and
hour variables ofthe RTC. Choose base addresses from the range FFOOH-FFFFH. (25)
8259A PIC Control Words:

AO D7 D6 D5 D4 D3 D2 Dl DO
ICWl 0 A7 A6 A5 1 LTIM ADI SNGL IC4
ICW2 1 A15/T7 A 14/T6 A 13/T5 A12/T4 A111T3 A10 A9 A8
ICW3
1 S7 S6 S5 S4 S3 S2 Sl SO
Master
ICW3
1 0 0 0 0 0 ID2 ID1 IDa
Slave
ICW4 1 0 0 0 SFNM BUF M/S AEOI IlPM
OCWl 1 M7 M6 M5 M4 M3 M2 M1 MO
OCW2 0 R SL EO! 0 0 L2 Ll LO
8255A PPI Mode Set Control Word:

Mode set PORTA MODE PORTA PORTC PORTB PORTB PORTC
Fla I/O U I/O MODE I/O L I/O
SECTION -B
5. (a) Write an assembly program to count the number of vowels in a 20 byte long string. (15)
(b) What is the significance of a high overflow flag after an IMUL operation? What will
be the content of AX, DX and OF after the execution of following code snippet? (10)
MOY AX, I
MOY BX,-3
IMUL BX
(c) Explain why a certain physical address in 8086 can have multiple segment
addresses. A memory location has a physical address 80FD2H. In what segment does it
have offset 95A2H? (10)
Contd P/3
=3=
EEE 315
6. (a) Write an assembly program which most efficiently transposes a 3 x3 matrix. A is the
transpose of B if the rows of A are Columns in B. Declare both these matrices in row-
major format. (20)

(b) Execute the following code snippet line by line and after executing each line,
determine the states of the status flags (excluding AF). (10)

MOY AX,ODDDDH
MOY BX,OEEEEH
ADD AX,BX
ROR AX
NEG BX
(c) Why is it important to latch the contents of 8086 address bus? (5)
7. (a) The byte type coordinates of two points on the Cartesian plane is saved in two
arrays. Write an assembly program to calculate the distance between them. You only
need to find the integer part ofthe result. For (2,0) and (5,-3), result should be 4. (18)
(b) Determine the function of the following code snippet. Replace it with a faster
alternative code. (12)

MOY CX,11
MOY AH,200
XOR AL,AL
CMP AH,CL
JL EXIT
Loopl:SUB AH,CL
INC AL
CMP AH,CL
JL EXIT
Loop Loop 1
EXIT :HLT
(c) What are the basic elements of a computer system? (5)
8. (a) Briefly describe the write cycle in an 8086 based microcomputer. (15)
(b) Rewrite the following code snippet replacing 'Loop' with conditional jump. (7)
MOY CX,10
LOOPADD:
ADD AX,CX
LOOP LOOP ADD
Contd P/4
•
=4=
EEE 315
Contd ... Q. No.8
(c) Determine the syntax errors in the following assembly program. Rewrite it correctly. (13)
CODE SEGMENT
ASSUME CS: CODE, DS: CODE
MOV AX,CS
MOV DS,AX
MOV AX, ABCDH
PUSH AX
MOV A,B
ADD A, AX
POP AL
MOV CL,B
LOOP.?:
SUB AX, CL
LOOP LOOP.?
HLT
...•
L-3/T-2/EEE Date: 17/07/2016


USE SEP AM TE SCRIPTS FOR EACH SECTION
SECTION -A
Answer in brief and to the point. Symbols have their usual meanings. Make reasonable
assumptions on any missing information.
1. (a) Name the techniques for countering noise in communication systems. With necessary
diagram, explain the technique that uses amplifiers along the transmission path. (8)
2 2
(b) Propagation constant of a transmission media is given as y = (co/1 On + co /50n ) + j( 6n
+ 10-6 co2) per km. Two message signals to be transmitted are m I (t) = 10cos(12nt) +
6cos(20nt), and m2(t) = 8cos(20nt). (6+6)

" (i) Detennine whether ml(t) and m2(t) can be received without any distortion.
(ii) If the length of the cable is 2 km, find the expression of the received signal for
ml(t).
;J..
(c) For the cascaded system shown in Fig. for Q. No. l(c), noise power at the output of ,{\',C.
\
Amplifier 1 is - 85 dBm. Calculate the (i) NF of the overall system, (ii) SNR at the input
and the output of Amplifier 2, and (iii) noise temperature of the two amplifiers. (15)
"
Pin::;
30dBm 8 km transmission line

Signal attenuation: 2dB/km,
Noise gain: O.5dBlkm
Fig. for Q. NO.1 (e)

---_.----------
2. (a) Explain the operation of a double-balanced DSB-SC AM modulator. Why is the
modulator called 'double-balanced'?

(b) Consider a DSB+C AM based communication system with message
m(t) = 8cos(10000 nt) + 6cos(20000nt) and carrier e(t) = 5cos(2n x 106)t.

(i) Calculate the minimum carrier amplitude required for using envelope detector?
(ii) Calculate the modulation index, total transmitted power and the power efficiency.
(iii) What kind of detection should be used in the receiver? Justify your answer.
(iv) Draw the amplitude spectrum of the AM signal.
(v) For the given met) and e(t), determine the bandwidth of DSB+C and SSB+C
signals.
(vi) Ifthe carrier frequency is now doubled, repeat part (v).
Contd P12
=2=
EEE 309
Contd ... Q. No.2
(c) With necessary diagrams, explain the weaver method for generating SSB AM signal.
(7)
3. (a) Derive the generalized time-domain expressIOn of FM signal for a single-tone

message. Then show that the bandwidth of NBFM signal is equal to that of DSB AM
(10+4)
signal.
(b) Consider an FM system with a single-tone message with amplitude Am=2 volt and
frequency Im=4 kHz. The carrier has an amplitude Ac=4 volt and frequency
fc = 1 MHz. The system uses a modulation index fJ for which the carrier in the FM signal
has 30% of the total transmitted power. Now using the attached Bessel function plot in
(14)
Fig. for Q. No. 3(b). answer the following questions.
(i) What is the modulation index ~ of the system?

(ii) Determine the bandwidth using the Carson's rule.
(iii) Draw the FM amplitude spectrum.
(iv) Calculate the percentage of power contained within the bandwidth found in part
(ii).
(v) Calculate the bandwidth of the FM signal using the 1% rule.
6
(c) For a message signal m(t) = 8t + 4cos(4000nt) and carrier e(t) = 2cos(2nx10 )t, derive
the expressions of PM and FM signals. Given, frequency sensitivity kj = 1000 HzN and
phase sensitivity kp = 4n radN. Also find the power of the modulated signal.
(7)
4. (a) Draw the block diagram of a QAM system. Derive the expression of reconstructed in-
phase channel (I-channel) signal if both the frequency and the phase of the receiver
(4+6)
carrier are different than those of transmitter side carrier.
(b) Derive the mathematical relationship between vestigial shaping filter at the
transmitter and the LPF at the receiver in a VSB based communication systems. Also
explain why VSB+C is preferred for TV signal transmission. (8+5)
(c) Define pulse modulation. With necessary diagrams, discuss in detail the impact of
pulse width and the sampling frequency on the bandwidth of the flat-topped PAM signal. (2+ 10)
SECTION-B
5. The maximum and the minimum values of the message signal, m(t) = 10 cos(2000 nt) +
6cos( 6000 nt) are 16 and -16, respectively. The message signal is sampled at 50% higher
than the Nyquist rate, quantized with mid-rise type quantizer and then encoded to obtain
(5+ 15+ 15=35)
PCM signal.
Contd P/3
.-~
\'
1
=3=
EEE 309
Contd ... Q. No.5
(i) Draw the amplitude spectrum of the sampled signal.
(ii) Determine the minimum number of quantization levels and the corresponding
data rate to achieve the minimum signal to quantization noise ratio (SQNR) of 18 dB
if a unifonn quantizer is used. Also detennine the data bits for time duration t = 0 to
0.5 ms ifthe first sample starts at t = O.
(iii) Determine the data bits for time duration t = 0 to 0.5 ms if a non-unifonn
quantization is performed with Jl-Iaw(Jl = 255) and the no. of levels is used as in (ii).
Also detennine the SQNR for this non-unifonn quantization.
6. (a) Draw the block diagrams of DPCM transmitter and receIver. Show that the
reconstruction error in DPCM is equal to the quantization error. (17)
(b) A message signal, met) = 4sin(2000 rrt) + 2sin(6000 1tt) is sampled at 300% higher
than the Nyquest rate for ii-modulation. (18)
(i) Determine the step size of the ii-modulator to minimize the slope overloading
error.
(ii) Determine the data rate of the ii-modulated signal.
(iii) Detennine the quantization noise and data bits for 6 samples if the first sample
starts at t = 0.001 ms.
7. (a) Draw the block diagrams ofBFSK modulator and (coherent) demodulator. Also write
down the expressions of the signals at the input and output of each of the blocks of BFSK
modulator and demodulator for data bits "I" and "0". (17)
(b) For the Q-PSK modulator shown in Fig. for Q. 7(b), (18)
(i) Plot the typical signals bet), al(t), a2(t), CI(t), C2(t) and Set) for bit sequence'
"00101101 ".
(ii) Draw the constellation diagram of the modulator.
(iii) Draw the block diagram of Q-PSK demodulator and explain how the demodulator
works for the
r-modlJla,ted.2.ignal '.
S(!L.__. -"'--~----'~~f .
",,", -0_"-
5en:o.l
to .
N~-cb~) pMtiU-
leve.-! . Cnn\.4'l.' .
. ~t'lCokt- telL
0.'1(3;) c;L*)
,,----,,--~_---J'
__ .- .h~. ~ ~. 1- U~) I Contd P/4 .
=4=
EEE 309
8. (a) Assume that currently the number of required telephone lines in BUET is 2000. The
number of lines increases 50 per year. Design TDM Systems for BUET with 20 years
plan using (i) T-carrier and (ii) E-carrier. (12)

(b) Write down. the comparative advantages and disadvantages between random and
channelization medium access protocols. (5)

(c) Consider the PN sequences for a 3-user DS-CDMA system are C1 = [1, -1,1, -1, 1,
-1, -1], C2 = [1,1, -1, -1,1,1, -1], C3 = [-1,1, -1, -1,1, -1,1], respectively. The data
bit sequences for the users are bl = "10", b2 = "01", and b3 = "11", respectively. (18)
(i) Draw the transmitted baseband signal for each of the users.
(ii) Draw the received baseband signal with
(a) Zero interference
(b) Wideband interference, n = [0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,]
(c) Narrow band interference, n = [0.5, 0.5, 0.5, 0.5, 0.5, 0.5, 0.5, 0.5, 0.5, 0.5,
0.5, 0.5, 0.5, 0.5]
in the channel.
(iii) Draw the decoded baseband signal by the receiver of user 2 for each of the
received signal in (ii).
(iv) Determine the output bit sequence at the receiver of user 2 for each of the
received signals in (ii) and comment on the result.
...•..
(1,,-- -r- - ~; ?
~-
~f
i --'"'7" ~._~ .••.- '---- -.- •.••.•.•••• _~ -,;; "-'! "_01
.~r-'
r
1,
~~ L .••. -~ .. ~ - _.~....---...~..• _-------------------~_ ..
.~~
- ------_. - ..""-- _. - -- .•...-.---- ----- - - - ------ .-,, _.-- - ..-. --_.~ -_

, ,," , , I ,
----- ..•., - -- --- - -- ,.. ------- _ ..-

.- -- --,._.- .--- - - ---- --- -- --- -- --- - .. _. ---_. _. - - - - ---
.. - --- -- - ._
, ,," • I I ,
_
0.95 ,
0.9 ----...'----------"--------
,
.&------ - ------_.--.... ----1-- --... ---~~---------;---

.
""
. --- _._-~------- -- __
, ,
A ---- -- --_: •• _-- -- _':. -- -- ---- --_ ••
.
~-- -------~--------
,
,
--~-
,
,
_. --- -- --~-
,
----- -- - ••• - •• - -- -.------ -~-_.- -----
e -
• I • , • , , ,
• " • I I , • , , ,
r"....-r-..---'r ....'-'-r--- ------ -.. --.- -. -- .--- .. - -.... --... -----'" r'" -"-r"-....r.-....'r--'-." .-.-.----------.--.--.----..
- L. •• •• _ _ • __ ~_ - __ - _~~_ ••• .~ _. __ '- L. - • __ - _ •• - •• - • __ - - • __ •• .~_ - •••__ • - .-' •• __ - - _L. ••• ~-~ -- - -- - - -- -- - .--.---- •• ---- -----
0.85 I
,
•
"
... ----r.- ---.... i.... -.-- --r .---

•
,
.'
"
I
.. - .. -... - ... -.- .. ---

I
I'
.'
"
I I
I
I
I
•
,
I
,
,
•
•
,
,
,
,
,
,
,
,
,
,
,
,
,
a- J1(~)
0.8
0.75
0.7 T::::::r::::: --------
-_::::--:r:L::I::T::::::::::::::: :::-:::::
:-::::L:IIT::::::::::::::::::: y-- J2(P)
0.65
:::::::t::::::: :L::::::T:::::::: ::::::::::::::::::r..:::-:T:::::::::::::::::::t::: :::::: ::::::::: ::::::::: ::::::::: ::::: :::T::::::T:: ::::T: :::::::[:::::::::::::::::::::::::::::::::::::
*- J3(~)
0.6
.--- ---r--' ---.-.f
, ,
--[.-..-..--
•
.---. - ~... -.-----T
•
'
,
I
I
"','". -
I
I
.
f-.----
,
,
--.--- --------..--.----.- ~ J4(~)
0.55
0.5 -:
- -- - - - -:- --- ~-- -- -: ----- -- - - - - ----- - --- --- - -- .- - - - --- - -;- - - - -- - - - -'- - -- - -- - - -'_ .. _. -- - - -;- - -- ~---- - - - - -- - - - - - - --- -- -- ~- - - - -----
,
------ -,... - --- - - - -.,., ----- - - -- ~ - ------ -- --_.- ---- _. ---
$- J5(~)
0.45 "
"
,
,
"., ,,
0.4
0.35
::::::r::::::r::::::r::::": :::..:::::::::::::F:.." ::::l:::::::: :~:::..::-r-.....-...----'
, "
~ J6(~)
\\ --
c::l.
0.3
0.25
::;-7: :::---:-:
:::T:I:_::---t-----
~ ....,c 0.2 ----- --- .---- -- --- --------- -------- ~..---- ---
\\ 0.15
0.1
0.05
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
.g- -0.45 I : ------r---------t------- -- ---------~----------~----------\--------.+------
c:<) -0.5
o 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5
wW Modulation index (~) Fig. for Q. No. 3(b)
ill
L-3/T-2/EEE Date: 23/07/2016
Sub: EEE 315 (Micr~processor and Interfacing)
SECTION-A
1. (a) The address 0010H:5000H contains an instruction. What should be the value of IP
for a program to execute that instruction, if CS is OOOOH? What is the advantage of
this overlapping nature of memory segments? (8) :1, it,.
'~'If'~ I
(b) Write a code snippet to copy the contents of the first two words in the stack without
changing the stack pointer. (7)
(c) What is the. effect of XOR AX, AX instruction on the register AX? Why is it
preferred over alternative ways of achieving the same result? (7)
(d) Write an assembly language program to calculate the sum of first N Fibonacci
numbers. You must calculate the Nth Fibonacci number using a recursive procedure. (13)
2. (a) What is the difference between SHR and SAR instructions? Explain why such
. distinction is not required for SHL and SAL. (8) .' .
~.;'
(b) For each of the following statements, state the addressing modes of the source and
destination operands. (10)
(i) MOV BX, 1000H
(ii) MO ALPHA, AX ; where ALPHA is a word
; variable
(iii) ADD AX, [BX]
(iv) SUB CX, -2[BX]
(v) MOV [BX] + ALPHA, CX
(c) Write an assembly language program to calculate the median of an array ofN words.
Median is the middle value of a data set, after it is arranged in ascending or descending
order. For even number of data, median is the mean of two middle values. (17)
3. (a) Write an assembly language program to count the number of times the string 'eee' is
repeated in a longer lower case array. (15)
(b) Find the values of status flags and all concerned registers after executing each of the
following instruction sequentially. Assume that the initial contents of AL and BL are .
80H and FFH respectively. (12)
(i) NEG AL
(ii) IMUL BL
(iii) ADD AL, BL
(iv) RCR AL, 1
(v) INC BL
(c) Write two alternate ways of executing an infinite loop in assembly language. (8)
Contd P12
()
=2=
EEE 315
4. (a) Design an 8086 based system with two 2kx8 RAMs and four 1kx8 ROMs. The
RAMs are placed in the memory space from 1B800H to 1C3FFH and from 1DCOOH to
1DFFFH. The ROMs are placed from the starting address of 1E800H onwards.
Implement even-odd banking. Show the memory map and connection schematic
including address decoders. (25)

(b) What problems may arise if you replace the BHE signal in the above design with
AO? (5)
(c) Why is it important to latch the contents of address bus in an 8086 based system? (5)
~.~
SECTION -B a..r
.
,'~or.
lij~

Assume reasonable data if necessary.
5. (a) Consider an 8086 microprocessor based system in which a 4x3 keypad (figure for
question No. 5(a)) is connected to the PORTA and PORTC, and a seven segment
display is connected to the PORTB of an 8255A PPI with base address 28H. Design the
schematic ofthe system so that it will take a BCD input from the keypad and display the . ,,
BCD number to the seven segment display. Assume that each segment consumes 25 mA
at 1.5 V. (12)
(b) 8086 microprocessor has the clock speed of 5 MHz. You have to write an assembly
language code for the above mentioned system considering the following facts: (23) .
(i) 8255A PPI has to be initialized as per the design requirements.
(ii) A delay of20 ms has to be used to avoid debouncing of keypress.
(iii) It takes 50 ms to detennine a BCD value from the keypad. So the seven
segment has to be refreshed after every 50 ms .
. 1
i
Figure for question NO.5 (a)
I
I
--------.;.1
~~_n. ~ '.
Contd P/3
=3=
EEE 315
~-
6. A freshman of BUET needs a pre-settable alarm system to attend his/her classes

punctually. You have an 8254 timer (with base address 38 H) and an 8255 A PPI (with
base address 29H) along with 8086 microprocessor to design the system for this
fresI:unan. The system will accept 4 digit BCD value in seconds to set the alarm through
PORTA and PORTB of 8255 A. Each BCD digit requires four input lines, so PORTA
and PORTB of 8255A wiII be sufficient to take the 4 digit BCD input. Connect the
buzzer of the alarm to the PCO pin of 8255 A. An external clock of 10kHz is available.
Alann should last for 4 seconds.
(a) Design the schematic ofthe system and briefly explain your design. (17)
(b) Write an assembly language code for your design. (18)
7. In an 8086 microprocessor based system two 8259A priority interrupt controller ICs are
configured as master and slave. The INTR of slave is routed through IR7 of the master
8259A to the 8086. Let the slave is interrupted at IR5. The interrupt type of IR7 of
master is 47 H and IR5 of the slave is 65H. The internal addresses of master are B8H
and BAH while the internal addresses of slave are 138 Hand 13A H.
(a) Draw the schematic of the system with address decoding.
(b) Briefly describe how the master and slave devices work together in the cascaded
configuration.
(c) Write assembly language codes to initialize both master and slave considering the
following facts:
(i) Master and slave are both level triggered.
(ii) Buffers are not used.
8. A microcomputer is connected to an 8251A USART (with base address FFOOH). A

.,.1
priority interrupt controller 8259A (with base address FOFOH) is also available for '.r
transmitting or receiving serial data. The input clock frequency for the USART is 614.4
kHz.
(a) Draw the schematic ofthe system. (8)
(b) A serial communication is to be established with baud rate of 9600 Bd, 8 bit
character length, one stop bit, even parity, enabled error reset, disabled hunt mode
and no break character. Construct the mode and command word that must be sent
for the USART. (8)
(c) Write assembly language codes for worst case initialization of 8251A so that it can
be used either as transmitter or receiver. (lO)
(d) Write an interrupt service routine to transmit and receive the serial data using
interrupt method. (You don't have to write the instructions to initialize 8259A). (9)
,~-----
;'
! ./
I '
8255A PPI Mode Set Control Word:
I '/ D2 Dl DO
/ D7 D6 I D5 D4 D3
I ,PORTA PORTC PORTB PORTB PORTC
I Mode Set PORTA Mode
I '
I/O (U) I/O Mode I/O (q I/O
Flag
/
I,
I,
v" 8254 Control Word:
II,
,
r I 8259A Control Words:
D5 D4 D3 D2 Dl DO
AO D7 D6
A5 1 LTIM ADI SNGL IC4
ICWI 0 A7 A6
A13/T5 A 12/T4 All/T3 AlO A9 A8
ICW2 1 A15/T7 Al4/T6
S5 S4 S3 S2 S1 SO
ICW3 1 S7 S6
Master ID1 IDO
0 0 0 0 ID2
ICW3 1 0
Slave M/S AEOI ~PM
1 a a a SFNM BUF
ICW4 M1 Ma
M6 MS M4 M3 M2
OCWI 1 M7
a a L2 Ll La
OCW2 a R SL EOI
8251A Mode Word:
8251A Command Word:
8251A Status Word:
~ .- - _. __ . -~
....... '---
--'--~-- .,,'. ~-

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L-4/T-l/EEE Date: 07/03/2012

BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA

Sub: EEE 495 (Real Time Computer System)

Full Marks: 210 Time: 3 Hours

for evaluating the performances of real time systems? (10)

3. (a) Explain the particle swarm optimization algorithm in brief. (12)

implementation of common TSL based lock for mutual exclusion? (8)

clock cycles, the circuit produces z = 1; otherwise, z = O. For example (27)

example and explain how it can be used to avoid deadlock. (20)

should not be considered as a real time Operating system. (15)

name of the techniques that have been employed by you. (20)

7. (a) Consider the following set of four tasks: (15)

Comment if T 1, T 2 T 3 are RM schedulable. Comment on their RM schedulability if the

execution time for each task is doubled.

8. (a) Consider the following code sample: (15)

Calculate the average turn-around time considering

Sub: EEE 455 (Compound Semiconductor and Hetero-junction Devices)

Full Marks: 210 Time: .3 Hours

minimized in HBT. (10)

in BJT. How Kirk effect is minimized in HBT? (17)

(b) What is the advantage of delta doping? (03)

electrons into the GaAs region. (17)

characteristics ofMESFET. (10)

Give that ~m = 4.55 eV, XSi = 4.01 eV

(iv) GaAs nMOSFET. (12)

function of gold is 5.1 eV. (45)

the effect of interface states on metal-semiconductor junction. (15)

Boltzmann distribution, derive current-voltage relationship of a Schottky contact. (15)

Material a (nrn) Eg (eY) rn*c rn*hh "f(eY)

Sub: EEE 453 (VLSI-I)

Full Marks: 210 Time: 3 Hours

have effective resistance R. (15)

(b) Show that fall time of an inverter is given by (17)

'tf= 2eL [n-o.l +!In(19-20n)]

The symbols have their usual meanings.

where Vtr = -Vtp = Vt

devices were not available? (15)

How latch up can be prevented? (17)

the operation of the circuit. (18)

help of a truth table. (20)

vectors that will detect the fault. (15)

Sub: EEE 453 (VLSI Design)

Full Marks : 210 Time: 3 Hours .

The truth table is shown in Fig. for Q. No. l(b). (15)

Gray Code Binary Code

the power supply voltage. (15)

wn = lO!-lm, wp = 20 !-lm, Ln = Lp = I !-lm, source/drain length = 5!-lm, gate oxide

connected with Voo. (20)

CMOS circuits. (15)

the delay through the chain. Assume r rp

8. (a) A 3 : 2 priority encoder is defined as follows (20)

Full Marks : 210 Time: 3 Hours

1. (a) Why is lattice constant of semiconductor important for heterostructured device

to InP. Necessary data are given in Table for Q~2(a). (20) .

,GaAs 5.6533 1.43

(b) Why are optical absorption of amorphous, crystalline and polycrystalline

direct/indirect semiconductors. (15)

3. (a). What is superlattice structure? How is it possible to modifyopto~electronicproperties

for an idealn-Gefp-GaAs heterojunction. (15)

Material a (nrn) Eg (eY) rnc rnhh "f(eY)