DA
DA
DA
VB1 = 1 VB2 = 0
vid=(vB1- vB2)
Different Voltage of about 4VT (100 mV) is sufficient to switch the current almost
entirely to one side of the pair, allowing it to be used as fast current switch
Currents and Voltages in DA, when a small differential input signal vid is applied
EE225 Analog Electronics II 11
Collector Currents when differential voltage is applied
From EQ1 and EQ2, collector currents can be expressed as
Points to note:
When Vid=0 , the bias current I divides equally between the 2 transistors.
When a small signal is applied at Vid , ic1 increases by an increment ic and ic2
decreases by an increment ic, where the increment ic is given by:
..(Eq 3)
where
If the output is taken differentially (between the 2 collectors), then the small signal (ac
signal) differential gain will be
For the differential amplifier with resistances the differential gain (between the 2
collectors) is
See previous
figure
Differential
signal in a
complementary
(balanced)
manner
Due to
symmetry
In this case, emitter voltage is not zero, so the resistance REE will have effect on
operation
If REE large , say REE >> re , Vid will still divide equally between the two junctions!
EE225 Analog Electronics II 21
vc2 = - vc1, the 2 transistors yield similar results, thus only side one is needed to
analyze the differential small-signal operation of the differential amplifier.
Differential half-circuit, low frequency equivalent model:
r = VT/IB
(a) The differential half-circuit and (b) its equivalent circuit model.
The model parameters r , gm and r0 are evaluated at the biased current I/2.
The differential voltage gain (between the 2 collectors) of the half circuit is
Input differential resistance of the differential amplifier is twice that of the half-
circuit that is 2 r
Common-mode half-circuits
From (b), Q1 and Q2 are biased at I/2 and have a resistance 2REE
EE225 Analog Electronics II 23
The common-mode output voltage is
1
Differential gain at one end is Ad ,1 g m RC ; and so the common-mode rejection
2
ratio (CMRR) is
The above analysis assumes that the circuit is perfectly matched. In practice
circuits are not perfectly symmetrical, with the result that the common-mode gain
will not be zero even if the output is taken differentially!
EE225 Analog Electronics II 24
Let us see the this point in detail. Let the circuit is perfect symmetrical except for a
mismatch RC (i.e. let the resistance at Q1 be RC and the resistance at Q2 be (RC +
RC )
The voltages at the collector are:
The common mode gain due to the mismatch is much smaller than (Eq. A). So,
the input differential stage of an op amp is always a balanced one, with the
output taken differentially.
EE225 Analog Electronics II 25
Note: The op-amp will have a low common-mode gain or
equivalently, a high CMRR
The output voltage can be expressed as
r
r0
Since REE is typically of the order of r0, Ricm will be very large
Give the circuit configuration and specify the values of all its
components.
Vin1=Vin2 = -2V
VE = -2.7V
I = (10-2.7)/20K = 0.365 mA
Ic1 = Ic2 =I/2 = 0.182 mA
35
Practice example 5
Given DA in Figure (Next slide), all four transistors
are matched. Take =200
a. Choose the value of R to give a source current
I = 0.5 mA. Next, take this value of R, what is
the output voltage of the circuit when Vin1=Vin2
and all transistors are active?
b. Show that, 10
Vout ( 40Vid )
;Vid Vin1 Vin 2
1 e
VB 3 9.3V
for I 0.5 mA,
0 VB 3
I
R
so, R 18.6 k
Now Vin1 Vin 2
I c1 I c 2 I / 2 0.25 mA
Vout 10 I c 2 * 20 K 5V
EE225 Analog Electronics II 37
Next let us prove that
Cont. example 4
10
Vout ( 40Vid )
;Vid Vin1 Vin 2
1 e
From large signal eqns. for Q1 and Q2 are (Refer PPT Notes):
Vin1 VE IRc
I c1 I s exp Vout Vcc I c 2 Rc Vcc
.....a Vid
VT 1 e VT
At ,Vid 0,
Av 100
Differential Input resistance is