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    Why Boundary Scan Needed?

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    srikanth
    The document describes boundary scan and JTAG testing. Boundary scan allows testing of board-level interconnects and I/O pins by stitching them into a scan chain. JTAG defines the Test Access Port interface and registers used for boundary scan, including the boundary scan register for controlling I/O pins, instruction register for selecting operations, and bypass register for fast shifting. Common instructions like Sample, Preload, RunBIST and IDCODE are used for board testing, running built-in self-tests, and identifying devices.

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    Why Boundary Scan Needed?

    Uploaded by

    srikanth
    393 views39 pages
    The document describes boundary scan and JTAG testing. Boundary scan allows testing of board-level interconnects and I/O pins by stitching them into a scan chain. JTAG defines the Test Access Port interface and registers used for boundary scan, including the boundary scan register for controlling I/O pins, instruction register for selecting operations, and bypass register for fast shifting. Common instructions like Sample, Preload, RunBIST and IDCODE are used for board testing, running built-in self-tests, and identifying devices.

    Original Description:

    Explains JTAG modes and operations

    Original Title

    Jtag

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    The document describes boundary scan and JTAG testing. Boundary scan allows testing of board-level interconnects and I/O pins by stitching them into a scan chain. JTAG defines the Test Access Port interface and registers used for boundary scan, including the boundary scan register for controlling I/O pins, instruction register for selecting operations, and bypass register for fast shifting. Common instructions like Sample, Preload, RunBIST and IDCODE are used for board testing, running built-in self-tests, and identifying devices.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    393 views39 pages

    Why Boundary Scan Needed?

    Uploaded by

    srikanth
    The document describes boundary scan and JTAG testing. Boundary scan allows testing of board-level interconnects and I/O pins by stitching them into a scan chain. JTAG defines the Test Access Port interface and registers used for boundary scan, including the boundary scan register for controlling I/O pins, instruction register for selecting operations, and bypass register for fast shifting. Common instructions like Sample, Preload, RunBIST and IDCODE are used for board testing, running built-in self-tests, and identifying devices.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 39

    External Scan/ Boundary Scan:

     Internal Scan means stitching internal flops of a system logic in to a scan chain
     By this we cannot control system inputs and outputs
     In External scan, we stich system inputs and outputs as a chain, so that we can observe and
    control system inputs and outputs
     External scan is also called Boundary Scan
     To perform boundary scan, a standared need to followed as IEEE 1149.1 by all the vendors, So
    different chips from the vendors are tested together on a same board

    Why Boundary Scan Needed?


    Board Level Test and Diagnosis:

     All chips are stiched in one JTAG chain


     Online and Offline debugs are supported
     We can debug the board when the board is in normal operation
    Test On board Wires among chips

     Bridging fault among two chips / Stuck at fault at the interconnect wire

    Test On Chip System Logic


    JTAG Components:

    1. Test Access Port


     TDI
     TDO
     TCK
     TMS
     TRST
    2. TAP controller
    3. Registers
     Instruction register
     Boundary scan register
     Bypass Register
    4. Instruction Register

    Registers:

     Data Register
    o Mandatory Registers
     Bypass Register (BR)
     Boundary Scan Register (BSR)
     Instruction Register
     Optional Register
    o Device ID Register
    o Device Specific Register
     Registers share same TDI/TDO

    Bypass Register:

     It is a one bit data register


     Provides direct one Bit Filp Flop from TDI to TDO, when Shift DR=1
     Bypass register saves Test time

    Boundary Scan Registers( BSR):

     Control System I/O pins, Observe System I/O pins


    Boundary Scan Cell:

     Boundary Scan Cell Operates in 4 modes:


    1. Normal
    2. Scan
    3. Update
    4. Capture
     By using ShiftDR, Mode Pins we can control the Operation BSR
    Normal Operation:
    Scan Operation:
    Update Operation:
    Capture Operation:
    Output Boundary Scan Cell

    Input and Output Boudary , Direction of Operation changes for Capture and Update mode
    Instruction Register:
     Instruction decoder generated Mode , select signals to Data registers
     Select signals Control the scan output from the data register
     TAP controller generated Clock DR, Shift DR, Update DR to Data register
     Clock IR, Shift IR, Update IR to Instruction Register
     Clock DR, Clock IR take transition at Rising edge of TCK
     Update DR, Update IR take transition at Falling edge of TCK
     TDO is available at failing edge of TCK
    JTAG Instructions:
    Scan In Data in CHIP 1:

     Data is loaded in using TDI pin


     Shift in to all Boundary Scan Register
    Scan Out date in CHIP 2:

     Data is shifted Out using TDO pin from CHIP1


     Capture the TDO data from CHIP1 in to TDI of CHIP2, and clock DR to length of Boundary Scan
    Registers
    Step1:

    Load Instruction Register


    Step2:

    Load Boundary Scan Register with data and Update DR


    Step 3:

    Unload Boundary Scan Register and Compare the data.


    Sample and PreLoad instruction:

    The instruction of sample and preload can be decided by the designer

    Sample: Take the snap shot of system I/O pins

    Preload : Control system I/O pins by the output flip flop of boundary scan register

    Sample:
    Suppose we need to observe the 101 at chip 2

    We follow the above TAP pattern


    Preload:
    RunBIST?

     RUNBIST instruction is an optional instruction


     Standard does not specify an instruction bit pattern for it
     The purpose of this instruction is to provide users of an IC access to internal built-in self-tests
    with a standardized access protocol
     While RUNBIST is in effect, the IC output pins are controlled one of two ways
    o first, under control of the Boundary Register
    o second, all placed in a non-driving state.
     In the first instance, states supplied by a PRELOAD sequence executed before loading
    RUNBIST will be used to control the IC outputs, while the self test is being performed
     RUNBIST is self-initializing; it does not require any seed data
     Loading the Boundary Register with a PRELOAD process to eliminate board-level conflicts is not
    considered part of the initialization of the self-test

     RUNBIST targets some register between TDI and TDO as specified by the IC designer.
     It may be a dedicated register or it may be an existing register such as the Bypass or Boundary
    Registers.
     The purpose of this register is to accumulate the result of the self-test so it can be shifted out for
    observation
     The actual self-test runs when the TAP is placed in the RUN-TEST-IDLE state
     The test result is captured by the target register in each component upon passing through
    CAPTURE-DR.
     Then all results can be shifted out for examination.

    IDCODE:

     The IDCODE instruction places the 32-bit Device Identification Register


     IDCODE is an optional instruction.
     The Device ID Register is parallel loaded with a hard-coded value upon passing through the
    CAPTURE-DR state

    HIGHZ:

     It is an optional instruction
     By loading an IC with HIGHZ we make it release control of its output nodes
     HIGHZ targets the Bypass Register between TDI and TDO, to shorten the shift path
     It also causes all output and bidirectional pins to go into high-impedance states.
     This switching to a disabled state occurs when HIGHZ becomes effective, upon passing through
    UPDATE-IR.

    CLAMP:

     It is an optional instruction
     HIGHZ targets the Bypass Register between TDI and TDO, to shorten the shift path
     CLAMP is intended for “digital guarding.”
     When testing a board, it is often necessary to force static “0”s or “l”s on selected nodes in order to
    set up testable conditions or to block interfering signals
     If the nodes of interest are sourced from Boundary-Scan devices that possess the CLAMP
    function, then this digital guarding activity can be performed without nail access or potentially
    damaging overdrive

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