ADS7846

AD
S784
6
ADS ®
7846

AD
S784
6

SBAS125H – SEPTEMBER 1999 – REVISED JANUARY 2005

TOUCH SCREEN CONTROLLER

FEATURES DESCRIPTION
● SAME PINOUT AS ADS7843 The ADS7846 is a next-generation version to the industry
● 2.2V TO 5.25V OPERATION standard ADS7843 4-wire touch screen controller. The
ADS7846 is 100% pin-compatible with the existing ADS7843,
● INTERNAL 2.5V REFERENCE
and drops into the same socket. This allows for easy upgrade
● DIRECT BATTERY MEASUREMENT (0V to 6V) of current applications to the new version. Only software
● ON-CHIP TEMPERATURE MEASUREMENT changes are required to take advantage of the added fea-
● TOUCH-PRESSURE MEASUREMENT tures of direct battery measurement, temperature measure-
ment, and touch-pressure measurement. The ADS7846 also
● QSPITM/SPITM 3-WIRE INTERFACE
has an on-chip 2.5V reference that can be used for the
● AUTO POWER-DOWN auxiliary input, battery monitor, and temperature measure-
● TSSOP-16, SSOP-16, QFN-16, ment modes. The reference can also be powered down when
AND VFBGA-48 PACKAGES not used to conserve power. The internal reference operates
down to 2.7V supply voltage while monitoring the battery
voltage from 0V to 6V.
APPLICATIONS
The low-power consumption of < 0.75mW (typ at 2.7V,
● PERSONAL DIGITAL ASSISTANTS
reference off), high speed (up to 125kHz clock rate), and on-
● PORTABLE INSTRUMENTS chip drivers make the ADS7846 an ideal choice for battery-
● POINT-OF-SALE TERMINALS operated systems such as personal digital assistants (PDAs)
● PAGERS with resistive touch screens, pagers, cellular phones, and
other portable equipment. The ADS7846 is available in the
● TOUCH SCREEN MONITORS
small TSSOP-16, SSOP-16, QFN-16, and VFBGA-48 pack-
● CELLULAR PHONES ages and is specified over the –40°C to +85°C temperature
US Patent No. 6246394 range.
QSPI and SPI are registered trademarks of Motorola.
PENIRQ

+VCC

X+
Temperature
SAR
X– Sensor

Y+ ADS7846 DOUT
Y–
BUSY
Comparator
6-Channel Serial CS
MUX CDAC Data
Out

Battery DCLK
VBAT
Monitor
DIN
AUX

Internal 2.5V
VREF
Reference

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1999-2005, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
+VCC to GND ........................................................................ –0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V DISCHARGE SENSITIVITY
Digital Inputs to GND ............................................. –0.3V to +VCC + 0.3V
Power Dissipation .......................................................................... 250mW This integrated circuit can be damaged by ESD. Texas Instru-
Maximum Junction Temperature ................................................... +150°C ments recommends that all integrated circuits be handled with
Operating Temperature Range ........................................ –40°C to +85°C appropriate precautions. Failure to observe proper handling
Storage Temperature Range ......................................... –65°C to +150°C
and installation procedures can cause damage.
Lead Temperature (soldering, 10s) ............................................... +300°C
ESD damage can range from subtle performance degradation
NOTE: (1) Stresses above these ratings can cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade to complete device failure. Precision integrated circuits may be
device reliability. more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM
INTEGRAL SPECIFIED
LINEARITY PACKAGE TEMPERATURE PACKAGE ORDERING
PRODUCT ERROR (LSB) PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER

ADS7846E ±2 SSOP-16 DBQ –40°C to +85°C ADS7846E ADS7846E

" " " " " " ADS7846E/2K5

ADS7846N ±2 TSSOP-16 PW –40°C to +85°C ADS7846N ADS7846N

" " " " " " ADS7846N/2K5
" " " " " " ADS7846N/2K5G4

ADS7846I ±2 VFBGA-48 GQC –40°C to +85°C ADS7846 ADS7846IGQCR

ADS7846I ±2 QFN-16 RGV –40°C to +85°C ADS7846 ADS7846IRGVT

" " " " " " ADS7846IRGVR

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site
at www.ti.com.

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ADS7846
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ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, and digital inputs = GND or +VCC,
unless otherwise noted.

ADS7846E

PARAMETER CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT
Full-Scale Input Span Positive Input-Negative Input 0 VREF V
Absolute Input Range Positive Input –0.2 +VCC + 0.2 V
Negative Input –0.2 +0.2 V
Capacitance 25 pF
Leakage Current 0.1 µA
SYSTEM PERFORMANCE
Resolution 12 Bits
No Missing Codes 11 Bits
Integral Linearity Error ±2 LSB(1)
Offset Error ±6 LSB
Gain Error External VREF ±4 LSB
Noise Including Internal VREF 70 µVrms
Power-Supply Rejection 70 dB
SAMPLING DYNAMICS
Conversion Time 12 CLK Cycles
Acquisition Time 3 CLK Cycles
Throughput Rate 125 kHz
Multiplexer Settling Time 500 ns
Aperture Delay 30 ns
Aperture Jitter 100 ps
Channel-to-Channel Isolation VIN = 2.5Vp-p at 50kHz 100 dB
SWITCH DRIVERS
On-Resistance
Y+, X+ 5 Ω
Y–, X– 6 Ω
Drive Current(2) Duration 100ms 50 mA
REFERENCE OUTPUT
Internal Reference Voltage 2.45 2.50 2.55 V
Internal Reference Drift 15 ppm/°C
Quiescent Current 500 µA
REFERENCE INPUT
Range 1.0 +VCC V
Input Impedance SER/DFR = 0, PD1 = 0, 1 GΩ
Internal Reference Off
Internal Reference On 250 Ω
BATTERY MONITOR
Input Voltage Range 0.5 6.0 V
Input Impedance
Sampling Battery 10 kΩ
Battery Monitor Off 1 GΩ
Accuracy External VREF = 2.5V –2 +2 %
Internal Reference –3 +3 %
TEMPERATURE MEASUREMENT
Temperature Range –40 +85 °C
Resolution Differential Method(3) 1.6 °C
TEMP0(4) 0.3 °C
Accuracy Differential Method(3) ±2 °C
TEMP0(4) ±3 °C
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Levels, Except PENIRQ
VIH | IIH | ≤ +5µA +VCC • 0.7 +VCC + 0.3
VIL | IIL | ≤ +5µA –0.3 +0.8 V
VOH IOH = –250µA +VCC • 0.8 V
VOL IOL = 250µA 0.4 V
PENIRQ
VOL TA = 0°C to +85°C, 50kΩ Pull-Up 0.8 V
Data Format Straight Binary
POWER-SUPPLY REQUIREMENTS
+VCC(5) Specified Performance 2.7 3.6 V
Operating Range 2.2 5.25 V
Quiescent Current Internal Reference Off 280 650 µA
Internal Reference On 780 µA
fSAMPLE = 12.5kHz 220 µA
Power-Down Mode with 3 µA
CS = DCLK = DIN = +VCC
Power Dissipation +VCC = +2.7V 1.8 mW
TEMPERATURE RANGE
Specified Performance –40 +85 °C
NOTES: (1) LSB means least significant bit. With VREF equal to +2.5V, one LSB is 610µV. (2) Ensured by design, but not tested. Exceeding 50mA source current
may result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement. No calibration necessary. (4) Temperature drift is –2.1mV/°C.
(5) ADS7846 operates down to 2.2V.

ADS7846 3
SBAS125H www.ti.com
PIN CONFIGURATION
Top View SSOP, TSSOP Top View VFBGA

DCLK CS DIN BUSY DOUT

+VCC 1 16 DCLK
1 2 3 4 5 6 7
X+ 2 15 CS A NC NC

Y+ 3 14 DIN
B NC NC NC NC NC
+VCC PENIRQ
X– 4 13 BUSY
ADS7846 C NC NC NC NC
Y– 5 12 DOUT +VCC +VCC

GND 6 11 PENIRQ D NC NC NC NC NC
X+ VREF
VBAT 7 10 +VCC E NC NC NC NC NC
Y+ AUX
AUX 8 9 VREF
F NC NC NC NC NC NC NC

G NC NC

X– Y– GND GND VBAT

Top View QFN

15 PENIRQ
16 DOUT

14 +VCC

13 VREF

BUSY 1 12 AUX

DIN 2 11 VBAT
ADS7846
CS 3 10 GND

DCLK 4 9 Y–
5

8
+VCC

X+

Y+

X–

PIN DESCRIPTION
SSOP AND
TSSOP PIN # VFBGA PIN # QFN PIN # NAME DESCRIPTION
1 B1 and C1 5 +VCC Power Supply
2 D1 6 X+ X+ Position Input
3 E1 7 Y+ Y+ Position Input
4 G2 8 X– X– Position Input
5 G3 9 Y– Y– Position Input
6 G4 and G5 10 GND Ground
7 G6 11 VBAT Battery Monitor Input
8 E7 12 AUX Auxiliary Input to ADC
9 D7 13 VREF Voltage Reference Input/Output
10 C7 14 +VCC Digital I/O Power Supply
11 B7 15 PENIRQ Pen Interrupt. Open anode output (requires 10kΩ to 100kΩ pull-up resistor externally).
12 A6 16 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high
impedance when CS is high.
13 A5 1 BUSY Busy Output. This output is high impedance when CS is high.
14 A4 2 DIN Serial Data Input. If CS is low, data is latched on rising edge of DCLK.
15 A3 3 CS Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS high = power-down mode (ADC only).
16 A2 4 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serial data
I/O.

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ADS7846
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TYPICAL CHARACTERISTICS
At TA = +25°C, +VCC = +2.7V, VREF = External +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.

POWER-DOWN SUPPLY CURRENT

SUPPLY CURRENT vs TEMPERATURE vs TEMPERATURE
400 140

350 120
Supply Current (µA)

Supply Current (nA)

300 100

250 80

200 60

150 40

100 20
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
Temperature (°C) Temperature (°C)

SUPPLY CURRENT vs +VCC MAXIMUM SAMPLE RATE vs +VCC

390 1M

370
fSAMPLE = 12.5kHz
350
Supply Current (µA)

Sample Rate (Hz)

100k
330

310
10k
290

270

250 1k
2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0
+VCC (V) +VCC (V)

CHANGE IN GAIN vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE

0.15 0.6

0.10 0.4
Delta from +25°C (LSB)
Delta from +25°C (LSB)

0.05 0.2

0 0

–0.05 –0.2

–0.10 –0.4

–0.15 –0.6
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
Temperature (°C) Temperature (°C)

ADS7846 5
SBAS125H www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = External +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.

REFERENCE CURRENT vs SAMPLE RATE REFERENCE CURRENT vs TEMPERATURE

14 18

12 16

Reference Current (µA)

Reference Current (µA)

10
14
8
12
6
10
4

8
2

0 6
0 25 50 75 100 125 –40 –20 0 20 40 60 80 100
Sample Rate (kHz) Temperature (°C)

SWITCH-ON RESISTANCE vs +VCC SWITCH-ON RESISTANCE vs TEMPERATURE

(X+, Y+: +VCC to Pin; X–, Y–: Pin to GND) (X+, Y+: +VCC to Pin; X–, Y–: Pin to GND)
8 8

7 7
X– Y–
6 6
Y–
RON (Ω)

5
RON (Ω)

5
X–
X+ Y+
4 4
Y+ X+
3 3

2 2

1 1
2.0 2.5 3.0 3.5 4.0 4.5 5.0 –40 –20 0 20 40 60 80 100
+VCC (V) Temperature (°C)

MAXIMUM SAMPLING RATE vs RIN INTERNAL VREF vs TEMPERATURE

2.0 2.4920
1.8 INL: R = 2k 2.4915
1.6 INL: R = 500
DNL: R = 2k 2.4910
1.4 DNL: R = 500
Internal VREF (V)

2.4905
Error (LSB)

1.2
2.4900
1.0
2.4895
0.8
0.6 2.4890

0.4 2.4885

0.2 2.4880
0 2.4875
–40
–35
–30
–25
–20
–15
–10
–05
0
05
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85

20 40 60 80 100 120 140 160 180 200

Sampling Rate (kHz) Temperature (°C)

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ADS7846
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 TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = External +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.

INTERNAL VREF vs VCC INTERNAL VREF vs TURN-ON TIME

2.4865 100

2.4860 80

Internal VREF (%)

No Cap
2.4855 60 (52µS)
VREF (V)

12-Bit 1µF Cap

Settling (1110µS)
2.4850 40 12-Bit
Settling
2.4845 20

2.4840 0
2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6
0 200 400 600 800 1000 1200
Turn-On Time (µS)
VCC (V)

TEMP DIODE VOLTAGE

vs TEMPERATURE (2.7V SUPPLY) TEMP0 DIODE VOLTAGE vs VSUPPLY (25°C)
850 620

800
TEMP0 Diode Voltage (mV)
TEMP Diode Voltage (mV)

618
750
102.7mV TEMP1
700 616
650
132.25mV 614
600
TEMP0
550
612
500

450 610
2.7 3.0 3.3
–40
–35
–30
–25
–20
–15
–10
–05
0
05
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85

Temperature (°C) VSUPPLY (V)

TEMP1 DIODE VOLTAGE vs VSUPPLY (25°C)

732
TEMP1 Diode Voltage (mV)

730

728

726

724

722
2.7 3.0 3.3
VSUPPLY (V)

ADS7846 7
SBAS125H www.ti.com
THEORY OF OPERATION possible to negate the error from each touch panel driver
switch’s on-resistance (if this is a source of error for the
The ADS7846 is a classic successive approximation register particular measurement).
(SAR) analog-to-digital converter (ADC). The architecture is
based on capacitive redistribution which inherently includes
ANALOG INPUT
a sample-and-hold function. The converter is fabricated on a
0.6µm CMOS process. See Figure 2 for a block diagram of the input multiplexer on
the ADS7846, the differential input of the ADC, and the
The basic operation of the ADS7846 is shown in Figure 1.
differential reference of the converter. Table I and Table II
The device features an internal 2.5V reference and an
show the relationship between the A2, A1, A0, and SER/DFR
external clock. Operation is maintained from a single supply
control bits and the configuration of the ADS7846. The
of 2.7V to 5.25V. The internal reference can be overdriven
control bits are provided serially via the DIN pin—see the
with an external, low impedance source between 1V and
Digital Interface section of this data sheet for more details.
+VCC. The value of the reference voltage directly sets the
input range of the converter. When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (see Figure 2) is
The analog input (X-, Y-, and Z-position coordinates, auxil-
captured on the internal capacitor array. The input current
iary input, battery voltage, and chip temperature) to the
into the analog inputs depends on the conversion rate of the
converter is provided via a multiplexer. A unique configura-
device. During the sample period, the source must charge
tion of low on-resistance touch panel driver switches allows
the internal sampling capacitor (typically 25pF). After the
an unselected ADC input channel to provide power and its
capacitor has been fully charged, there is no further input
accompanying pin to provide ground for an external device,
current. The rate of charge transfer from the analog source
such as a touch screen. By maintaining a differential input to
to the converter is a function of conversion rate.
the converter and a differential reference architecture, it is

+2.7V to +5V

1µF ADS7846
+
to 0.1µF
10µF
(Optional) 1 +VCC DCLK 16 Serial/Conversion Clock

2 X+ CS 15 Chip Select

3 Y+ DIN 14 Serial Data In

Touch 4 X– BUSY 13 Converter Status

Screen
5 Y– DOUT 12 Serial Data Out
To Battery Pen Interrupt
6 GND PENIRQ 11

7 VBAT +VCC 10

Auxiliary Input 8 AUX VREF 9 50kΩ

Voltage
Regulator

FIGURE 1. Basic Operation of the ADS7846.

A2 A1 A0 VBAT AUXIN TEMP Y– X+ Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION X-DRIVERS Y-DRIVERS

0 0 0 +IN (TEMP0) Off Off
0 0 1 +IN Measure Off On
0 1 0 +IN Off Off
0 1 1 +IN Measure X–, On Y+, On
1 0 0 +IN Measure X–, On Y+, On
1 0 1 +IN Measure On Off
1 1 0 +IN Off Off
1 1 1 +IN (TEMP1) Off Off

TABLE I. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR high).

A2 A1 A0 +REF –REF Y– X+ Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION DRIVERS ON

0 0 1 Y+ Y– +IN Measure Y+, Y–
0 1 1 Y+ X– +IN Measure Y+, X–
1 0 0 Y+ X– +IN Measure Y+, X–
1 0 1 X+ X– +IN Measure X+, X–

TABLE II. Input Configuration (DIN), Differential Reference Mode (SER/DFR low).

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ADS7846
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 PENIRQ +VCC VREF

TEMP1 TEMP0

A2-A0 SER/DFR
(Shown 001B) (Shown High)

X+

X–

Ref On/Off

Y+ +REF
+IN
Y–
Converter
–IN
2.5V –REF
Reference

7.5kΩ
VBAT
2.5kΩ

Battery
On
AUX
GND

FIGURE 2. Simplified Diagram of Analog Input.

INTERNAL REFERENCE Reference

The ADS7846 has an internal 2.5V voltage reference that can Power Down
be turned on or off with the control bit, PD1 = 1 (see Table V and
Figure 3). Typically, the internal reference voltage is only used
in the single-ended mode for battery monitoring, temperature
measurement, and for using the auxiliary input. Optimal touch
screen performance is achieved when using the differential
VREF
mode. The internal reference voltage of the ADS7846 must be Band
Gap Buffer
commanded to be off to maintain compatibility with the ADS7843.
Therefore, after power-up, a write of PD1 = 0 is required to
Optional
insure the reference is off (see the Typical Characteristics for To
CDAC
power-up time of the reference from power-down).
FIGURE 3. Simplified Diagram of the Internal Reference.
REFERENCE INPUT
The voltage difference between +REF and –REF (shown in bit) size and is equal to the reference voltage divided by 4096
Figure 2) sets the analog input range. The ADS7846 oper- in 12-bit mode. Any offset or gain error inherent in the ADC
ates with a reference in the range of 1V to +VCC. There are appears to increase, in terms of LSB size, as the reference
several critical items concerning the reference input and its voltage is reduced. For example, if the offset of a given
wide voltage range. As the reference voltage is reduced, the converter is 2LSBs with a 2.5V reference, it is typically
analog voltage weight of each digital output code is also 5LSBs with a 1V reference. In each case, the actual offset of
reduced. This is often referred to as the LSB (least significant the device is the same, 1.22mV. With a lower reference

ADS7846 9
SBAS125H www.ti.com
voltage, more care must be taken to provide a clean layout +VCC
including adequate bypassing, a clean (low-noise, low-ripple)
power supply, a low-noise reference (if an external reference
is used), and a low-noise input signal.
The voltage into the VREF input directly drives the capacitor
digital-to-analog converter (CDAC) portion of the ADS7846. Y+
Therefore, the input current is very low (typically < 13µA).
There is also a critical item regarding the reference when
making measurements where the switch drivers are on. For +IN
+REF
this discussion, it is useful to consider the basic operation of X+
Converter
the ADS7846 (see Figure 1). This particular application –IN
–REF
shows the device being used to digitize a resistive touch
screen. A measurement of the current Y position of the
pointing device is made by connecting the X+ input to the Y–

ADC, turning on the Y+ and Y– drivers, and digitizing the

voltage on X+ (Figure 4 shows a block diagram). For this GND
measurement, the resistance in the X+ lead does not affect
the conversion (it does affect the settling time, but the FIGURE 5. Simplified Diagram of Differential Reference
resistance is usually small enough that this is not a concern). (SER/DFR Low, Y Switches Enabled, X+ is
However, since the resistance between Y+ and Y– is fairly Analog Input).
low, the on-resistance of the Y drivers does make a small
difference. Under the situation outlined so far, it is not As a final note about the differential reference mode, it must
possible to achieve a 0V input or a full-scale input regardless be used with +VCC as the source of the +REF voltage and
of where the pointing device is on the touch screen, because cannot be used with VREF. It is possible to use a high
some voltage is lost across the internal switches. In addition, precision reference on VREF and single-ended reference
the internal switch resistance is unlikely to track the resis- mode for measurements which do not need to be ratiometric.
tance of the touch screen, providing an additional source of error. In some cases, it is possible to power the converter directly
from a precision reference. Most references can provide
enough power for the ADS7846, but might not be able to
+VCC VREF
supply enough current for the external load (such as a
resistive touch screen).

TOUCH SCREEN SETTLING

Y+
In some applications, external capacitors may be required
across the touch screen for filtering noise picked up by the
touch screen (for example, noise generated by the LCD panel
+REF
+IN or backlight circuitry). These capacitors provide a low-pass
X+
Converter
filter to reduce the noise, but cause a settling time requirement
–IN
–REF when the panel is touched that typically shows up as a gain
error. The problem is that the input and/or reference has not
Y– settled to the final steady-state value prior to the ADC sam-
pling the input(s) and providing the digital output. Additionally,
GND
the reference voltage may still be changing during the mea-
surement cycle. There are several methods for minimizing or
FIGURE 4. Simplified Diagram of Single-Ended Reference eliminating this issue. Option 1 is to stop or slow down the
(SER/DFR High, Y Switches Enabled, X+ is ADS7846 DCLK for the required touch screen settling time.
Analog Input). This allows the input and reference to have stable values for
the Acquire period (3 clock cycles of the ADS7846; see Figure
This situation can be remedied as shown in Figure 5. By 9). This works for both the single-ended and the differential
setting the SER/DFR bit low, the +REF and –REF inputs are modes. Option 2 is to operate the ADS7846 in the differential
connected directly to Y+ and Y–, respectively, which makes mode only for the touch screen measurements and command
the analog-to-digital conversion ratiometric. The result of the the ADS7846 to remain on (touch screen drivers on) and not
conversion is always a percentage of the external resistance, go into power-down (PD0 = 1). Several conversions are made
regardless of how it changes in relation to the on-resistance of depending on the settling time required and the ADS7846 data
the internal switches. Note that there is an important consid- rate. Once the required number of conversions have been
eration regarding power dissipation when using the ratiometric made, the processor commands the ADS7846 to go into the
mode of operation (see the Power Dissipation section for power-down state on the last measurement. This process is
more details).

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ADS7846
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required for X-position, Y-position, and Z-position measure- represented by kT/q • ln (N), where N is the current ratio
ments. Option 3 is to operate in the 15 Clock-per-Conversion = 91, k = Boltzmann’s constant (1.38054 • 10–23 electron
mode which overlaps the analog-to-digital conversions and volts/degrees Kelvin), q = the electron charge (1.602189 •
maintains the touch screen drivers on until commanded to 10–19 C), and T = the temperature in degrees Kelvin. This
stop by the processor (see Figure 12). method can provide improved absolute temperature mea-
surement over the first mode at the cost of less resolution
TEMPERATURE MEASUREMENT (1.6°C/LSB). The equation for solving for °K is:

In some applications, such as battery recharging, a measure- °K = q • ∆V/(k • ln (N)) (1)

ment of ambient temperature is required. The temperature where, ∆V = V (I91) – V (I1) (in mV)
measurement technique used in the ADS7846 relies on the ∴ °K = 2.573°K/mV • ∆V
characteristics of a semiconductor junction operating at a
°C = 2.573 • ∆V(mV) – 273°K
fixed current level. The forward diode voltage (VBE) has a
well-defined characteristic versus temperature. The ambient NOTE: The bias current for each diode temperature mea-
temperature can be predicted in applications by knowing the surement is only on for 3 clock cycles (during the acquisition
25°C value of the VBE voltage and then monitoring the delta mode). Therefore, it does not add any noticeable increase in
of that voltage as the temperature changes. The ADS7846 power, especially if the temperature measurement only oc-
offers two modes of operation. The first mode requires curs occasionally.
calibration at a known temperature, but only requires a single
reading to predict the ambient temperature. The PENIRQ BATTERY MEASUREMENT
diode is used (turned on) during this measurement cycle.
An added feature of the ADS7846 is the ability to monitor the
The voltage across the diode is connected through the MUX
battery voltage on the other side of the voltage regulator (DC/DC
for digitizing the forward bias voltage by the ADC with an
converter), as shown in Figure 7. The battery voltage can vary
address of A2 = 0, A1 = 0, and A0 = 0 (see Table I and Figure
from 0.5V to 6V, while maintaining the voltage to the ADS7846
6 for details). This voltage is typically 600mV at +25°C with
at 2.7V, 3.3V, etc. The input voltage (VBAT) is divided down by
a 20µA current through the diode. The absolute value of this
4 so that a 6.0V battery voltage is represented as 1.5V to the
diode voltage can vary a few millivolts. However, the TC of
ADC. This simplifies the multiplexer and control logic. In order
this voltage is very consistent at –2.1mV/°C. During the final
to minimize the power consumption, the divider is only on
test of the end product, the diode voltage would be stored at
during the sampling period when A2 = 0, A1 = 1, and A0 = 0
a known room temperature, in memory, for calibration pur-
(see Table I for the relationship between the control bits and
poses by the user. The result is an equivalent temperature
configuration of the ADS7846).
measurement resolution of 0.3°C/LSB (in 12-bit mode).

+VCC

External 2.7V
X+ DC/DC
Pull-Up Converter
PENIRQ Battery
MUX ADC 0.5V +
to
6.0V
+VCC

Temperature Select 0.125V to 1.5V

VBAT
TEMP0 TEMP1
7.5kΩ

FIGURE 6. Functional Block Diagram of Temperature Mea- 2.5kΩ

surement Mode.

The second mode does not require a test temperature

calibration, but uses a two-measurement method to eliminate
the need for absolute temperature calibration and for achiev-
ing 2°C accuracy. This mode requires a second conversion
with an address of A2 = 1, A1 = 1, and A0 = 1, with a 91 times
larger current. The voltage difference between the first FIGURE 7. Battery Measurement Functional Block Diagram.
and second conversion using 91 times the bias current is

ADS7846 11
SBAS125H www.ti.com
PRESSURE MEASUREMENT
Measure X-Position
Measuring touch pressure can also be done with the ADS7846. X+ Y+
To determine pen or finger touch, the pressure of the touch
needs to be determined. Generally, it is not necessary to have Touch

very high performance for this test; therefore, the 8-bit resolu-
tion mode is recommended (however, calculations will be X-Position
shown here are in 12-bit resolution mode). There are several Y–
X–
different ways of performing this measurement. The ADS7846
supports two methods. The first method requires knowing the
X-plate resistance, measurement of the X-Position, and two Measure Z1-Position
additional cross-panel measurements (Z1 and Z2) of the touch X+ Y+

screen, as shown in Figure 8. Using Equation 2 calculates the

Touch
touch resistance:
X – Position  Z2 
RTOUCH = RX – plate •  – 1 (2)
Z1-Position
4096  Z1  X– Y–
The second method requires knowing both the X-plate and
Y-plate resistance, measurement of X-Position and Y-Posi-
tion, and Z1. Using Equation 3 also calculates the touch
X+ Y+
resistance:
Touch
R X − plate • X − Position  4096 
R TOUCH =  Z – 1
4096  1 
Z2-Position
 Y Position  (3)
– R Y − plate • 1–  X– Y–
 4096  Measure Z2-Position

DIGITAL INTERFACE FIGURE 8. Pressure Measurement Block Diagrams.

Figure 9 shows the typical operation of the ADS7846 digital

The first eight clock cycles are used to provide the control
interface. This diagram assumes that the source of the
byte via the DIN pin. When the converter has enough
digital signals is a microcontroller or digital signal processor
information about the following conversion to set the input
with a basic serial interface. Each communication between
multiplexer and reference inputs appropriately, the converter
the processor and the converter, such as SPI/SSI or
enters the acquisition (sample) mode and, if needed,
Microwire™ synchronous serial interface, consists of eight
the touch panel drivers are turned on. After three more
clock cycles. One complete conversion can be accom-
clock cycles, the control byte is complete and the converter
plished with three serial communications for a total of 24
enters the conversion mode. At this point, the input
clock cycles on the DCLK input.

CS
tACQ

DCLK 1 8 1 8 1 8

SER/
DIN S A2 A1 A0 MODE DFR PD1 PD0
(START)
Idle Acquire Conversion Idle

BUSY

DOUT 11 10 9 8 7 6 5 4 3 2 1 0 Zero Filled...

(MSB) (LSB)
DRIVERS 1 AND 2(1)
Off On Off
(SER/DFR High)

DRIVERS 1 AND 2(1, 2)

(SER/DFR Low) Off On Off

NOTES: (1) For Y-Position, Driver 1 is on, X+ is selected, and Driver 2 is off. For X-Position, Driver 1 is off, Y+ is selected, and
Driver 2 is on. Y– will turn on when power-down mode is entered and PD0 = 0B. (2) Drivers will remain on if PD0 = 1 (no power
down) until selected input channel, reference mode, or power-down mode is changed, or CS is HIGH.

FIGURE 9. Conversion Timing, 24 Clocks-per-Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated
serial port.

12
ADS7846
www.ti.com SBAS125H
sample-and-hold goes into the hold mode and the touch SER/DFR—The SER/DFR bit controls the reference mode,
panel drivers turn off (in single-ended mode). The next 12 either single-ended (high) or differential (low). The differential
clock cycles accomplish the actual analog-to-digital conver- mode is also referred to as the ratiometric conversion mode
sion. If the conversion is ratiometric (SER/DFR = 0), the and is preferred for X-Position, Y-Position, and Pressure-
drivers are on during the conversion and a 13th clock cycle Touch measurements for optimum performance. The refer-
is needed for the last bit of the conversion result. Three more ence is derived from the voltage at the switch drivers, which
clock cycles are needed to complete the last byte (DOUT will is almost the same as the voltage to the touch screen. In this
be low), which are ignored by the converter. case a reference voltage is not needed, as the reference
Control Byte voltage to the ADC is the voltage across the touch screen. In
the single-ended mode, the converter reference voltage is
The control byte (on DIN), as shown in Table III, provides the
always the difference between the VREF and GND pins (see
start conversion, addressing, ADC resolution, configuration,
Tables I and II, and Figures 2 through 5 for further informa-
and power-down of the ADS7846. Figure 9 and Tables III
tion).
and IV give detailed information regarding the order and
description of these control bits within the control byte. If X-Position, Y-Position, and Pressure-Touch are measured
in the single-ended mode, an external reference voltage is
needed. The ADS7846 should also be powered from the
Bit 7 Bit 0
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) external reference. Caution must be observed when using
S A2 A1 A0 MODE SER/DFR PD1 PD0
the single-ended mode such that the input voltage to the
ADC does not exceed the internal reference voltage, espe-
TABLE III. Order of the Control Bits in the Control Byte. cially if the supply voltage is greater than 2.7V.
NOTE: The differential mode can only be used for X-Position,
BIT NAME DESCRIPTION
Y-Position, and Pressure-Touch measurements. All other
7 S Start Bit. Control byte starts with first high bit on DIN.
measurements require the single-ended mode.
A new control byte can start every 15th clock cycle
in 12-bit conversion mode or every 11th clock cycle PD0 and PD1—Table V describes the power-down and the
in 8-bit conversion mode (see Figure 12).
internal reference voltage configurations. The internal refer-
6-4 A2-A0 Channel Select Bits. Along with the SER/DFR bit,
ence voltage can be turned on or off independently of the
these bits control the setting of the multiplexer input,
touch driver switches, and reference inputs (see ADC. This can allow extra time for the internal reference
Tables I and II). voltage to settle to the final value prior to making a conver-
3 MODE 12-Bit/8-Bit Conversion Select Bit. This bit controls sion. Make sure to also allow this extra wake-up time if the
the number of bits for the next conversion: 12-bits
internal reference is powered down. The ADC requires no
(low) or 8-bits (high).
wake-up time and can be instantaneously used. Also note
2 SER/DFR Single-Ended/Differential Reference Select Bit. Along
with bits A2-A0, this bit controls the setting of the that the status of the internal reference power-down is
multiplexer input, touch driver switches, and reference latched into the part (internally) with BUSY going high.
inputs (see Tables I and I).
Therefore, in order to turn the reference off, an additional
1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for
write to the ADS7846 is required after the channel is con-
details.
verted.
TABLE IV. Descriptions of the Control Bits within the Control
Byte. PD1 PD0 PENIRQ DESCRIPTION
0 0 Enabled Power-Down Between Conversions. When each
Initiate START—The first bit, the S bit, must always be high conversion is finished, the converter enters a
and initiates the start of the control byte. The ADS7846 low-power mode. At the start of the next conver-
sion, the device instantly powers up to full power.
ignores inputs on the DIN pin until the start bit is detected. There is no need for additional delays to assure
Addressing—The next three bits (A2, A1, and A0) select the full operation and the very first conversion is
valid. The Y– switch is on when in power-down.
active input channel(s) of the input multiplexer (see Tables I,
0 1 Disabled Reference is off and ADC is on.
II, and Figure 2), touch screen drivers, and the reference
1 0 Enabled Reference is on and ADC is off.
inputs.
1 1 Disabled Device is always powered. Reference is on and
MODE—The mode bit sets the resolution of the ADC. With ADC is on.
this bit low, the next conversion has 12 bits of resolution; with TABLE V. Power-Down and Internal Reference Selection.
this bit high, the next conversion has 8 bits of resolution.

ADS7846 13
SBAS125H www.ti.com
16 Clocks-per-Conversion SYMBOL DESCRIPTION MIN TYP MAX UNITS
The control bits for conversion n + 1 can be overlapped with tACQ Acquisition Time 1.5 µs
conversion n to allow for a conversion every 16 clock cycles, tDS DIN Valid Prior to DCLK Rising 100 ns
as shown in Figure 10. This figure also shows possible serial tDH DIN Hold After DCLK High 10 ns
communication occurring with other serial peripherals be- tDO DCLK Falling to DOUT Valid 200 ns
tween each byte transfer from the processor to the converter. tDV CS Falling to DOUT Enabled 200 ns
This is possible provided that each conversion completes tTR CS Rising to DOUT Disabled 200 ns
within 1.6ms of starting. Otherwise, the signal that is cap- tCSS CS Falling to First DCLK Rising 100 ns
tured on the input sample-and-hold may droop enough to tCSH CS Rising to DCLK Ignored 0 ns
affect the conversion result. Note that the ADS7846 is fully tCH DCLK High 200 ns
powered while other serial communications are taking place tCL DCLK Low 200 ns
during a conversion. tBD DCLK Falling to BUSY Rising 200 ns
tBDV CS Falling to BUSY Enabled 200 ns
Digital Timing
tBTR CS Rising to BUSY Disabled 200 ns
Figures 9, 11, and Table VI provide detailed timing for the
digital interface of the ADS7846. TABLE VI. Timing Specifications (+VCC = +2.7V and Above,
TA = –40°C to +85°C, CLOAD = 50pF).

CS

DCLK
1 8 1 8 1 8 1

DIN S S
Control Bits Control Bits

BUSY

DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9

FIGURE 10. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.

CS
tCL
tCSS tCH tBD tBD tD0 tCSH

DCLK
tDH
tDS

DIN PD0

tBDV tBTR

BUSY

tDV tTR

DOUT 11 10

FIGURE 11. Detailed Timing Diagram.

14
ADS7846
www.ti.com SBAS125H
15 Clocks-per-Conversion 8-Bit Conversion
Figure 12 provides the fastest way to clock the ADS7846. The ADS7846 provides an 8-bit conversion mode that can be
This method does not work with the serial interface of most used when faster throughput is needed and the digital result
microcontrollers and digital signal processors, as they are is not as critical. By switching to the 8-bit mode, a conversion
generally not capable of providing 15 clock cycles per serial is complete four clock cycles earlier. Not only does this shorten
transfer. However, this method can be used with field pro- each conversion by four bits (25% faster throughput), but each
grammable gate arrays (FPGAs) or application specific inte- conversion can actually occur at a faster clock rate. This is
grated circuits (ASICs). Note that this effectively increases because the internal settling time of the ADS7846 is not as
the maximum conversion rate of the converter beyond the critical—settling to better than 8 bits is all that is needed. The
values given in the specification tables, which assume 16 clock rate can be as much as 50% faster. The faster clock rate
clock cycles per conversion. and fewer clock cycles combine to provide a 2x increase in
Data Format conversion rate.

The ADS7846 output data is in Straight Binary format as

shown in Figure 13. This figure shows the ideal output code POWER DISSIPATION
for the given input voltage and does not include the effects There are two major power modes for the ADS7846: full power
of offset, gain, or noise. (PD0 = 1B) and auto power-down (PD0 = 0B). When operating
at full speed and 16 clocks-per-conversion (see Figure 10), the
ADS7846 spends most of the time acquiring or converting.
FS = Full-Scale Voltage = VREF(1) There is little time for auto power-down, assuming that this
1LSB = VREF(1)/4096
mode is active. Therefore, the difference between full-power
1LSB mode and auto power-down is negligible. If the conversion
11...111 rate is decreased by slowing the frequency of the DCLK input,
11...110 the two modes remain approximately equal. However, if the
11...101 DCLK frequency is kept at the maximum rate during a conver-
Output Code

sion but conversions are done less often, the difference

between the two modes is dramatic.
00...010

00...001

00...000

0V FS – 1LSB
Input Voltage(2) (V)

NOTES: (1) Reference voltage at converter: +REF – (–REF), see Figure 2.

(2) Input voltage at converter, after multiplexer: +IN – (–IN), see Figure 2.

FIGURE 13. Ideal Input Voltages and Output Codes.

CS Power Down

DCLK
1 15 1 15 1

SGL/ SGL/
DIN S A2 A1 A0 MODE DIF PD1 PD0 S A2 A1 A0 MODE DIF PD1 PD0 S A2 A1 A0

BUSY

DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 Tri-State

FIGURE 12. Maximum Conversion Rate, 15 Clocks-per-Conversion.

ADS7846 15
SBAS125H www.ti.com
Figure 14 shows the difference between reducing the DCLK
frequency (scaling DCLK to match the conversion rate) or
LAYOUT
maintaining DCLK at the highest frequency and reducing the The following layout suggestions provide the most optimum
number of conversions per second. In the latter case, the performance from the ADS7846. However, many portable
converter spends an increasing percentage of time in power- applications have conflicting requirements concerning power,
down mode (assuming the auto power-down mode is active). cost, size, and weight. In general, most portable devices
have fairly clean power and grounds because most of the
internal components are very low power. This situation means
less bypassing for the converter power and less concern
1000
regarding grounding. Still, each situation is unique and the
fCLK = 16 • fSAMPLE following suggestions should be reviewed carefully.
For optimum performance, care must be taken with the
Supply Current (µA)

100 physical layout of the ADS7846 circuitry. The basic SAR

architecture is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and digital
fCLK = 2MHz inputs that occur just prior to latching the output of the analog
10
comparator. Therefore, during any single conversion for an
TA = 25°C n-bit SAR converter, there are n ‘windows’ in which large
+VCC = +2.7V external transient voltages can easily affect the conversion
1 result. Such glitches can originate from switching power
1k 10k 100k 1M
supplies, nearby digital logic, and high-power devices. The
fSAMPLE (Hz)
degree of error in the digital output depends on the reference
voltage, layout, and the exact timing of the external event.
The error can change if the external event changes in time
FIGURE 14. Supply Current versus Directly Scaling the Fre-
with respect to the DCLK input.
quency of DCLK with Sample Rate or Maintain-
ing DCLK at the Maximum Possible Frequency. With this in mind, power to the ADS7846 should be clean and
well bypassed. A 0.1µF ceramic bypass capacitor should be
Another important consideration for power dissipation is the placed as close to the device as possible. A 1µF to 10µF
reference mode of the converter. In the single-ended refer- capacitor may also be needed if the impedance of the
ence mode, the touch panel drivers are on only when the connection between +VCC and the power supply is high. Low-
analog input voltage is being acquired (see Figure 9 and leakage capacitors should be used to minimize power dissi-
Table I). Therefore, the external device (e.g., a resistive pation through the bypass capacitors when the ADS7846 is
touch screen) is only powered during the acquisition period. in power-down mode.
In the differential reference mode, the external device must A bypass capacitor is generally not needed on the VREF pin
be powered throughout the acquisition and conversion peri- because the internal reference is buffered by an internal op
ods (see Figure 9). If the conversion rate is high, this could amp. If an external reference voltage originates from an op
substantially increase power dissipation. amp, make sure that it can drive any bypass capacitor that
CS also puts the ADS7846 into power-down mode. When is used without oscillation.
CS goes high, the ADS7846 immediately goes into power- The ADS7846 architecture offers no inherent rejection of
down and does not complete the current conversion. How- noise or voltage variation in regards to using an external
ever, the internal reference does not turn off with CS going reference input. This is of particular concern when the
high. To turn the reference off, an additional write is required reference input is tied to the power supply. Any noise and
before CS goes high (PD1 = 0). ripple from the supply appears directly in the digital results.
Whereas high-frequency noise can be filtered out, voltage
variation due to line frequency (50Hz or 60Hz) can be difficult
to remove.

16
ADS7846
www.ti.com SBAS125H
The GND pin must be connected to a clean ground point. In
many cases, this is the analog ground. Avoid connections
+VCC
which are too near the grounding point of a microcontroller or
digital signal processor. If needed, run a ground trace directly
from the converter to the power-supply entry or battery- 100kΩ
connection point. The ideal layout includes an analog ground
plane dedicated to the converter and associated analog Y+ PENIRQ
circuitry.
In the specific case of use with a resistive touch screen, care
should be taken with the connection between the converter
X+
and the touch screen. Although resistive touch screens have
fairly low resistance, the interconnection should be as short
and robust as possible. Longer connections are a source of
error, much like the on-resistance of the internal switches.
Y–
Likewise, loose connections can be a source of error when On
the contact resistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error Y or X drivers on,
or TEMP0, TEMP1
in touch screen applications (for example, applications that measurements
require a backlit LCD panel). This EMI noise can be coupled activated.
through the LCD panel to the touch screen and cause
“flickering” of the converted data. Several things can be done
to reduce this error, such as using a touch screen with a FIGURE 15. ADS7846 PENIRQ Functional Block Diagram.
bottom-side metal layer connected to ground to shunt the
majority of noise to ground. Additionally, filtering capacitors,
from Y+, Y–, X+, and X– pins to ground can also help. Furthermore, the PENIRQ output is disabled and low during
Caution should be observed under these circumstances for the measurement cycle for X-, Y-, and Z-Position. The PENIRQ
settling time of the touch screen, especially operating in the output is disabled and high during the measurement cycle for
single-ended mode and at high data rates. battery monitor, auxiliary input, and chip temperature. If the last
control byte written to the ADS7846 contains PD0 = 1, the pen-
interrupt output function is disabled and is not able to detect
PENIRQ OUTPUT when the screen is touched. In order to re-enable the pen-
The pen-interrupt output function is shown in Figure 15. While interrupt output function under these circumstances, a control
in power-down mode with PD0 = 0, the Y– driver is on and byte needs to be written to the ADS7846 with PD0 = 0. If the
connects the Y-plane of the touch screen to GND. The last control byte written to the ADS7846 contains PD0 = 0, the
PENIRQ output is connected to the X+ input through two pen-interrupt output function is enabled at the end of the
transmission gates. When the screen is touched, the X+ input conversion. The end of the conversion occurs on the falling
is pulled to ground through the touch screen. The PENIRQ edge of DCLK after bit 1 of the converted data is clocked out
output goes low due to the current path through the touch of the ADS7846.
screen to ground, which initiates an interrupt to the processor. It is recommended that the processor mask the interrupt
During the measurement cycle for X-, Y-, and Z-Position, the PENIRQ is associated with whenever the processor sends a
X+ input is disconnected from the external pull-up resistor. control byte to the ADS7846. This prevents false triggering
This is done to eliminate any leakage current from the of interrupts when the PENIRQ output is disabled, as in the
external pull-up resistor through the touch screen, thus caus- cases discussed in this section.
ing no errors.

ADS7846 17
SBAS125H www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

ADS7846E ACTIVE SSOP DBQ 16 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 7846E
ADS7846E/2K5 ACTIVE SSOP DBQ 16 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 7846E
ADS7846EG4 ACTIVE SSOP DBQ 16 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 7846E
ADS7846IRGVT ACTIVE VQFN RGV 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 7846
ADS7846N ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 7846N
ADS7846N/2K5 ACTIVE TSSOP PW 16 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 7846N
ADS7846N/2K5G4 ACTIVE TSSOP PW 16 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 7846N
ADS7846NG4 ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 7846N

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Oct-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7846E/2K5 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS7846IRGVT VQFN RGV 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
ADS7846N/2K5 TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Oct-2014

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7846E/2K5 SSOP DBQ 16 2500 367.0 367.0 35.0
ADS7846IRGVT VQFN RGV 16 250 210.0 185.0 35.0
ADS7846N/2K5 TSSOP PW 16 2500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1

2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]

8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]
GAGE PLANE

.004-.010
0 -8 [0.11-0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

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 EXAMPLE BOARD LAYOUT
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16

16X (.016 )
[0.41]

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6]
SYMM
1
16

16X (.016 )
[0.41]
SYMM

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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