ADS1100

BAA
I

SBAS239 – MAY 2002

Self-Calibrating, 16-Bit
ANALOG-TO-DIGITAL CONVERTER

FEATURES DESCRIPTION
● COMPLETE DATA ACQUISITION SYSTEM IN A The ADS1100 is a precision, continuously self-calibrating
TINY SOT23-6 PACKAGE Analog-to-Digital (A/D) converter with differential inputs and
up to 16 bits of resolution in a small SOT23-6 package.
● 16-BITS NO MISSING CODES
Conversions are performed ratiometrically, using the power
● INL: 0.0125% of FSR MAX supply as the reference voltage. The ADS1100 uses an
● CONTINUOUS SELF-CALIBRATION I2C-compatible serial interface and operates from a single
power supply ranging from 2.7V to 5.5V.
● SINGLE-CYCLE CONVERSION
The ADS1100 can perform conversions at rates of 8, 16, 32,
● PROGRAMMABLE GAIN AMPLIFIER
or 128 samples per second. The onboard programmable-
GAIN = 1, 2, 4, OR 8
gain amplifier, which offers gains of up to 8, allows smaller
● LOW NOISE: 4µVp-p signals to be measured with high resolution. In single-
● PROGRAMMABLE DATA RATE: 8SPS to 128SPS conversion mode, the ADS1100 automatically powers down
after a conversion, greatly reducing current consumption
● INTERNAL SYSTEM CLOCK
during idle periods.
● I2CTM INTERFACE The ADS1100 is designed for applications requiring high-
● POWER SUPPLY: 2.7V TO 5.5V resolution measurement, where space and power consump-
● LOW CURRENT CONSUMPTION: 90µA tion are major considerations. Typical applications include
portable instrumentation, industrial process control and smart
transmitters.
APPLICATIONS
● PORTABLE INSTRUMENTATION A = 1, 2, 4, or 8

● INDUSTRIAL PROCESS CONTROL VIN+ SCL

∆Σ A/D I2 C
● SMART TRANSMITTERS PGA
Converter Interface
VIN– SDA
● CONSUMER GOODS
● FACTORY AUTOMATION VDD

● TEMPERATURE MEASUREMENT Clock GND

Oscillator
I2C is a registered trademark of Philips Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC
VDD to GND ........................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary DISCHARGE SENSITIVITY
Input Current ................................................................. 10mA, Continuous
Voltage to GND, VIN+, VIN– ........................................ –0.3V to VDD + 0.3V This integrated circuit can be damaged by ESD. Texas
Voltage to GND, SDA, SCL ..................................................... –0.5V to 6V Instruments recommends that all integrated circuits be handled
Maximum Junction Temperature ................................................... +150°C with appropriate precautions. Failure to observe proper han-
Operating Temperature .................................................... –40°C to +85°C dling and installation procedures can cause damage.
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C ESD damage can range from subtle performance degrada-
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
tion to complete device failure. Precision integrated circuits
cause permanent damage to the device. Exposure to absolute maximum may be more susceptible to damage because very small
conditions for extended periods may affect device reliability. parametric changes could cause the device not to meet its
published specifications.

PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT I2C ADDRESS(1) PACKAGE-LEAD DESIGNATOR(2) RANGE MARKING NUMBER MEDIA, QUANTITY
ADS1100 1001 000 SOT23-6 DBV –40°C to +85°C BAAI ADS1100IDBVT Tape and Reel, 250
" " " " " " ADS1100IDBVR Tape and Reel, 3000
NOTES: (1) Contact TI or your local sales representative for more information on the availability of other addresses. (2) For the most current specifications and
package information, refer to our web site at www.ti.com.

PIN CONFIGURATION
Top View SOT
VIN– VDD SDA

6 5 4

BAAI
1 2 3
VIN+ GND SCL

NOTE: Marking text direction indicates pin 1.

2
ADS1100
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ELECTRICAL CHARACTERISTICS
All specifications at –40°C to +85°C, VDD = 5V, GND = 0V, all PGAs, unless otherwise noted.

ADS1100
PARAMETER CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT
Full-Scale Input Voltage (VIN+) – (VIN–) ±VDD/PGA V
Analog Input Voltage VIN+, VIN– to GND GND – 0.2 VDD + 0.2 V
Differential Input Impedance 2.4/PGA MΩ
Common-Mode Input Impedance 8 MΩ
SYSTEM PERFORMANCE
Resolution and No Missing Codes DR = 00 12 12 Bits
DR = 01 14 14 Bits
DR = 10 15 15 Bits
DR = 11 16 16 Bits
Conversion Rate DR = 00 104 128 184 SPS
DR = 01 26 32 46 SPS
DR = 10 13 16 23 SPS
DR = 11 6.5 8 11.5 SPS
Output Noise See Typical Characteristic Curves
Integral Nonlinearity DR = 11, PGA = 1, End Point Fit(1) ±0.003 ±0.0125 % of FSR(2)
Offset Error ±2.5/PGA ±5/PGA mV
Offset Drift PGA = 1 1.5 8 µV/°C
PGA = 2 1.0 4 µV/°C
PGA = 4 0.7 2 µV/°C
PGA = 8 0.6 2 µV/°C
Gain Error 0.01 0.1 %
Gain Error Drift 2 ppm/°C
Common-Mode Rejection At DC, PGA = 8 94 100 dB
At DC, PGA = 1 85 dB
DIGITAL INPUT/OUTPUT
Logic Level
VIH 0.7 • VDD 6 V
VIL GND – 0.5 0.3 • VDD V
VOL IOL = 3mA GND 0.4 V
Input Leakage
IIH VIH = 5.5V 10 µA
IIL VIL = GND –10 µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage VDD 2.7 5.5 V
Supply Current Power Down 0.05 2 µA
Active Mode 90 150 µA
Power Dissipation
VDD = 5.0V 450 750 µW
VDD = 3.0V 210 µW

NOTES: (1) 99% of full-scale. (2) FSR = Full-Scale Range = 2 • VDD/PGA.

ADS1100 3
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TYPICAL CHARACTERISTICS
At TA = 25°C, VDD = 5V, unless otherwise noted.

SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs I2C BUS FREQUENCY

120 250

225
VDD = 5V
100 200
25°C
175

IVDD (µA)
IVDD (µA)

125°C
80 150

125

60 100
VDD = 2.7V –40°C
75

40 50
–60 –40 –20 0 20 40 60 80 100 120 140 10 100 1k 10k
Temperature (°C) I2C Bus Frequency (kHz)

OFFSET ERROR vs TEMPERATURE OFFSET ERROR vs TEMPERATURE

2.0 2.0
VDD = 5V VDD = 2.7V

1.0 1.0
Offset Error (mV)

Offset Error (mV)

PGA = 8 PGA = 4 PGA = 2 PGA = 1 PGA = 8 PGA = 4 PGA = 2 PGA = 1

0.0
0.0

–1.0
–1.0

–2.0
–60 –40 –20 0 20 40 60 80 100 120 140 –2.0
–60 –40 –20 0 20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)

GAIN ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE

0.04 0.010
VDD = 5V VDD = 2.7V
0.03
0.005
PGA = 8 PGA = 4 PGA = 4
0.02 PGA = 8
PGA = 1
0.000
Gain Error (%)
Gain Error (%)

0.01

0.00 –0.005

–0.01 PGA = 1
–0.010
PGA = 2
–0.02
PGA = 2
–0.015
–0.03

–0.04 –0.020
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

4
ADS1100
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TYPICAL CHARACTERISTICS
At TA = 25°C, VDD = 5V, unless otherwise noted.

INTEGRAL NONLINEARITY vs
TOTAL ERROR vs INPUT SIGNAL
SUPPLY VOLTAGE
0.0 0.016
PGA = 8
PGA = 8 0.014 PGA = 4

Integral Nonlinearity (% of FSR)

–0.5 PGA = 2
0.012 PGA = 1
PGA = 4
Total Error (mV)

–1.0 0.010

PGA = 2 0.008
–1.5 0.006

0.004
–2.0
0.002
PGA = 1 Data Rate = 8SPS
–2.5 0.000
–100 –75 –50 –25 0 25 50 75 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Signal (% of Full-Scale) VDD (V)

INTEGRAL NONLINEARITY vs TEMPERATURE NOISE vs INPUT SIGNAL

0.05 20
PGA =1 Data Rate = 8SPS
Integral Nonlinearity (% of FSR)

PGA = 8
0.04
15
Noise (p-p, % of LSB)

PGA = 4
0.03
VDD = 2.7V PGA = 2
10
0.02 PGA = 1
VDD = 3.5V
VDD = 5V 5
0.01

0.00 0
–60 –40 –20 0 20 40 60 80 100 120 140 0 20 40 60 80 100
Temperature (°C) Input Signal (% of Full-Scale)

NOISE vs SUPPLY VOLTAGE NOISE vs TEMPERATURE

30 25
Data Rate = 8SPS
PGA = 8
25
PGA = 8 20
Noise (p-p, % of LSB)
Noise (p-p, % of LSB)

20
PGA = 4
15 15
PGA = 2
10
10
5
Data Rate = 8SPS PGA = 1
0 5
2.5 3.0 3.5 4.0 4.5 5.0 5.5 –60 –40 –20 0 20 40 60 80 100 120 140
VDD (V) Temperature (°C)

ADS1100 5
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TYPICAL CHARACTERISTICS
At TA = 25°C, VDD = 5V, unless otherwise noted.

DATA RATE vs TEMPERATURE FREQUENCY RESPONSE

10 0
Data Rate = 8SPS
VDD = 2.7V –20
9
Data Rate (SPS)

–40

Gain (dB)
8
–60
VDD = 5V
7
–80
Data Rate = 8SPS
6 –100
–60 –40 –20 0 20 40 60 80 100 120 140 0.1 1 10 100 1k
Input Frequency (Hz)
Temperature (°C)

6
ADS1100
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 puts codes in binary two’s complement format, so the abso-
THEORY OF OPERATION lute values of the minima and maxima are not the same; the
maximum n-bit code is 2n-1 – 1, while the minimum n-bit code
The ADS1100 is a fully differential, 16-bit, self-calibrating, is –1 • 2n-1.
delta-sigma A/D converter. Extremely easy to design with For example, the ideal expression for output codes with a
and configure, the ADS1100 allows you to take high-quality data rate of 16SPS and PGA = 2 is:
measurements with a minimum of effort.
The ADS1100 consists of a delta-sigma A/D converter core Output Code = 16384 • 2 •
(V ) – (V )
IN+ IN –

with adjustable gain, a clock generator, and an I2C interface. VDD

Each of these blocks are described in detail in the sections
that follow. The ADS1100 outputs all codes right-justified and sign-
extended. This arrangement makes it possible to perform
ANALOG-TO-DIGITAL CONVERTER averaging on the higher data rate codes using only a 16-bit
The ADS1100’s A/D converter core consists of a differential accumulator.
switched-capacitor delta-sigma modulator followed by a digi- Output codes for various input levels are shown in Table II.
tal filter. The modulator measures the difference between the
positive and negative analog inputs and compares this to a
SELF-CALIBRATION
reference voltage, which, in the ADS1100, is the power
supply. The digital filter receives a high-speed bitstream from The previous expressions for the ADS1100’s output code do
the modulator and outputs a code, which is a number not account for the gain and offset errors in the modulator. To
proportional to the input voltage. compensate for these, the ADS1100 incorporates self-cali-
bration circuitry.

OUTPUT CODE CALCULATION The self-calibration system operates continuously, and re-
quires no user intervention. No adjustments can be made to
The output code is a scalar value which is (except for clipping)
the self-calibration system, and none need to be made. The
proportional to the voltage difference between the two analog
self-calibration system cannot be deactivated.
inputs. The output code is confined to a finite range of numbers;
this range depends on the number of bits needed to represent The offset and gain error figures shown in the specifications
the code. The number of bits needed to represent the output table include the effects of calibration.
code for the ADS1100 depends on the data rate, as shown in
Table I. CLOCK GENERATOR
The ADS1100 features an onboard clock generator, which
Data rate Number of Bits Minimum Code Maximum Code drives the operation of the modulator and digital filter. The
8SPS 16 –32768 32767 Typical Characteristics show varieties in data rate over
16SPS 15 –16384 16383 supply voltage and temperature.
32SPS 14 –8192 8191
It is not possible to operate the ADS1100 with an external
128SPS 12 –2048 2047
modulator clock.
TABLE I. Minimum and Maximum Codes.
INPUT IMPEDANCE
For a minimum output code of Min Code, gain setting of The ADS1100 uses a switched-capacitor input stage. To
PGA, positive and negative input voltages of VIN+ and VIN-, external circuitry, it looks roughly like a resistance. The
and power supply of VDD, the output code is given by the resistance value, as with all switched-capacitor circuits, de-
expression: pends on the capacitor values and the rate at which they are

Output Code = –1• Min Code • PGA •

(V ) – (V )
IN+ IN –
switched. The switching frequency is the same as the modu-
lator frequency; the capacitor values depend on the PGA
VDD
setting. The switching clock is generated by the onboard
In the above expression, it is important to note that the clock generator, so its frequency, nominally 275 kHz, is
negated minimum output code is used. The ADS1100 out- somewhat dependent on supply voltage and temperature.

Input Signal
Data Rate Negative Full-Scale –1 LSB Zero +1 LSB Positive Full-Scale

8 SPS 8000H FFFFH 0000H 0001H 7FFFH

16 SPS C000H FFFFH 0000H 0001H 3FFFH
32 SPS E000H FFFFH 0000H 0001H 1FFFH
128 SPS F800H FFFFH 0000H 0001H 07FFH

TABLE II. Output Codes for Different Input Signals.

ADS1100 7
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The common-mode and differential input impedances are RESET AND POWER-UP
different. For a gain setting of PGA, the differential input When the ADS1100 powers up, it automatically performs a
impedance is typically: reset. As part of the reset, the ADS1100 sets all of the bits
2.4MΩ / PGA in the configuration register to their default setting.
The common mode impedance is typically 8MΩ. The ADS1100 responds to the I2C General Call Reset
command. When the ADS1100 receives a General Call
The typical value of the input impedance often cannot be
Reset, it performs an internal reset, exactly as though it had
neglected. Unless the input source has a low impedance, the
just been powered on.
ADS1100’s input impedance may affect the measurement
accuracy. For sources with high output impedance, buffering
may be necessary. Bear in mind, however, that active buffers I2C INTERFACE
introduce noise, and also introduce offset and gain errors. All The ADS1100 communicates through an I2C (Inter-Inte-
of these factors should be considered in high-accuracy grated Circuit) interface. The I2C interface is a 2-wire open-
applications. drain interface supporting multiple devices and masters on a
Because the clock generator frequency drifts slightly with single bus. Devices on the I2C bus only drive the bus lines
temperature, the input impedances will also drift. For many LOW, by connecting them to ground; they never drive the
applications, this input impedance drift can be neglected, and bus lines HIGH. Instead, the bus wires are pulled HIGH by
the typical impedance values above can be used. pull-up resistors, so the bus wires are HIGH when no device
is driving them LOW. This way, two devices cannot conflict;
if two devices drive the bus simultaneously, there is no driver
ALIASING
contention.
If frequencies are input to the ADS1100 which exceed half
Communication on the I2C bus always takes place between
the data rate, aliasing will occur. To prevent aliasing, the
two devices, one acting as the master and the other acting
input signal must be bandlimited. Some signals are inher-
as the slave. Both masters and slaves can read and write,
ently bandlimited, for example, a thermocouple’s output,
but slaves can only do so under the direction of the master.
which has a limited rate of change, but may nevertheless
Some I2C devices can act as masters or slaves, but the
contain noise and interference components. These can fold
ADS1100 can only act as a slave device.
back into the sampling band just as any other signal can.
An I2C bus consists of two lines, SDA and SCL. SDA carries
The ADS1100’s digital filter provides some attenuation of
data; SCL provides the clock. All data is transmitted across
high frequency noise, but the filter’s sinc1 frequency re-
the I2C bus in groups of eight bits. To send a bit on the I2C
sponse cannot completely replace an anti-aliasing filter;
bus, the SDA line is driven to the bit’s level while SCL is
some external filtering may still be needed. For many appli-
LOW. (A LOW on SDA indicates a zero bit; a HIGH indicates
cations, a simple RC filter will suffice.
a one bit.) Once the SDA line has settled, the SCL line is
When designing an input filter circuit, remember to take the brought HIGH, then LOW. This pulse on SCL clocks the SDA
interaction between the filter network and the input imped- bit into the receiver’s shift register.
ance of the ADS1100 into account.
The I2C bus is bidirectional: the SDA line is used both for
transmitting and receiving data. When a master reads from
USING THE ADS1100 a slave, the slave drives the data line; when a master sends
to a slave, the master drives the data line. The master always
OPERATING MODES drives the clock line. The ADS1100 never drives SCL,
The ADS1100 operates in one of two modes: continuous because it cannot act as a master. On the ADS1100, SCL is
conversion and single conversion. an input only.
In continuous conversion mode, the ADS1100 continuously Most of the time the bus is idle, no communication is taking
performs conversions. Once a conversion has been com- place, and both lines are HIGH. When communication is
pleted, the ADS1100 places the result in the output register, taking place, the bus is active. Only master devices can start
and immediately begins another conversion. When the a communication. They do this by causing a start condition
ADS1100 is in continuous conversion mode, the ST/BSY bit on the bus. Normally, the data line is only allowed to change
in the configuration register always reads 1. state while the clock line is LOW. If the data line changes
In single conversion mode, the ADS1100 waits until the state while the clock line is HIGH, it is either a start condition
ST/BSY bit in the conversion register is set to 1. When this or its counterpart, a stop condition. A start condition is when
happens, the ADS1100 powers up and performs a single the clock line is HIGH and the data line goes from HIGH to
conversion. After the conversion completes, the ADS1100 LOW. A stop condition is when the clock line is HIGH and the
places the result in the output register, resets the ST/BSY bit data line goes from LOW to HIGH.
to 0 and powers down. Writing a 1 to ST/BSY while a After the master issues a start condition, it sends a byte
conversion is in progress has no effect. which indicates which slave device it wants to communicate
When switching from continuous conversion mode to single with. This byte is called the address byte. Each device on an
conversion mode, the ADS1100 will complete the current I2C bus has a unique 7-bit address to which it responds.
conversion, reset the ST/BSY bit to 0 and power down. (Slaves can also have 10-bit addresses; see the I2C specifi-

8
ADS1100
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cation for details.) The master sends an address in the ADS1100 I2C ADDRESS
address byte, together with a bit which indicates whether it The ADS1100’s I2C address is 1001aaa, where aaa are bits
wishes to read from or write to the slave device. set at the factory. The ADS1100 is shipped with aaa set to
Every byte transmitted on the I2C bus, whether it be address zero, so its address is 1001000.
or data, is acknowledged with an acknowledge bit. When a Contact Texas Instruments for information about the avail-
master has finished sending a byte, eight data bits, to a ability of other addresses.
slave, it stops driving SDA and waits for the slave to acknowl-
edge the byte. The slave acknowledges the byte by pulling
I2C GENERAL CALL
SDA LOW. The master then sends a clock pulse to clock the
acknowledge bit. Similarly, when a master has finished The ADS1100 responds to General Call Reset, which is an
reading a byte, it pulls SDA LOW to acknowledge this to the address byte of 00H followed by a data byte of 06H. The
slave. It then sends a clock pulse to clock the bit. (Remember ADS1100 acknowledges both bytes.
that the master always drives the clock line.) On receiving a General Call Reset, the ADS1100 performs a
A not-acknowledge is performed by simply leaving SDA full internal reset, just as though it had been powered off and
HIGH during an acknowledge cycle. If a device is not present then on. If a conversion is in process, it is interrupted; the
on the bus, and the master attempts to address it, it will output register is set to zero; and the configuration register is
receive a not-acknowledge because no device is present at set to its default setting.
that address to pull the line LOW. The ADS1100 always acknowledges the General Call ad-
When a master has finished communicating with a slave, it dress byte of 00H, but it does not acknowledge any General
may issue a stop condition. When a stop condition is issued, Call data bytes other than 04H or 06H.
the bus becomes idle again. A master may also issue
another start condition. When a start condition is issued while I2C DATA RATES
the bus is active, it is called a repeated start condition. The I2C bus operates in one of three speed modes: Stan-
A timing diagram for an ADS1100 I2C transaction is shown in dard, which allows a clock frequency of up to 100kHz; Fast,
Figure 1. Table III gives the parameters for this diagram. which allows a clock frequency of up to 400kHz; and High-

t(LOW)
tR tF t(HDSTA)

SCL

t(HDSTA) t(HIGH) t(SUSTA) t(SUSTO)

t(HDDAT) t(SUDAT)

SDA
t(BUF)

P S S P

FIGURE 1. I2C Timing Diagram.

FAST MODE HIGH-SPEED MODE

PARAMETER MIN MAX MIN MAX UNITS
SCLK Operating Frequency f(SCLK) 0.4 3.4 MHz
Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns
Hold Time After Repeated START Condition. t(HDSTA) 600 160 ns
After this period, the first clock is generated.
Repeated START Condition Setup Time t(SUSTA) 600 160 ns
STOP Condition Setup Time t(SUSTO) 600 160 ns
Data Hold Time t(HDDAT) 0 0 ns
Data Setup Time t(SUDAT) 100 10 ns
SCLK Clock LOW Period t(LOW) 1300 160 ns
SCLK Clock HIGH Period t(HIGH) 600 60 ns
Clock/Data Fall Time tF 300 160 ns
Clock/Data Rise Time tR 300 160 ns

TABLE III. Timing Diagram Definitions.

ADS1100 9
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speed mode (also called Hs mode), which allows a clock In continuous conversion mode, the ADS1100 ignores the
frequency of up to 3.4MHz. The ADS1100 is fully compatible value written to ST/BSY.
with all three modes. When read in single conversion mode, ST/BSY indicates
No special action needs to be taken to use the ADS1100 in whether the A/D converter is busy taking a conversion. If ST/
Standard or Fast modes, but High-speed mode must be BSY is read as 1, the A/D converter is busy, and a conversion
activated. To activate High-speed mode, send a special is taking place; if 0, no conversion is taking place, and the
address byte of 00001XXX following the start condition, result of the last conversion is available in the output register.
where the XXX bits are unique to the Hs-capable master. In continuous mode, ST/BSY is always read as 1.
This byte is called the Hs master code. (Note that this is
different from normal address bytes: the low bit does not
Bits 6-5: Reserved
indicate read/write status.) The ADS1100 will not acknowl-
edge this byte; the I2C specification prohibits acknowledg- Bits 6 and 5 must be set to zero.
ment of the Hs master code. On receiving a master code, the
ADS1100 will switch on its High-speed mode filters, and will Bit 4: SC
communicate at up to 3.4MHz. The ADS1100 switches out of SC controls whether the ADS1100 is in continuous conver-
Hs mode with the next stop condition. sion or single conversion mode. When SC is 1, the ADS1100
For more information on High-speed mode, consult the I2C is in single conversion mode; when SC is 0, the ADS1100 is
specification. in continuous conversion mode. The default setting is 0.

REGISTERS Bits 3-2: DR

The ADS1100 has two registers which are accessible via its Bits 3 and 2 control the ADS1100’s data rate, as shown in
I2C port. The output register contains the result of the last Table VI.
conversion; the configuration register allows you to change
the ADS1100’s operating mode and query the status of the DR1 DR0 DATA RATE
device. 0 0 128SPS
0 1 32SPS
1 0 16SPS
OUTPUT REGISTER
1(1) 1(1) 8SPS(1)
The 16-bit output register contains the result of the last NOTE: (1) Default Setting
conversion in binary two’s complement format. Following
TABLE VI. DR Bits.
reset or power-up, the output register is cleared to zero; it
remains zero until the first conversion is completed. There-
fore, if you read the ADS1100 just after reset or power-up, Bits 1-0: PGA
you will read zero from the output register. Bits 1 and 0 control the ADS1100’s gain setting, as shown in
The output register’s format is shown in Table V. Table VII.

CONFIGURATION REGISTER PGA1 PGA0 GAIN

0(1) 0(1) 1(1)
You can use the 8-bit configuration register to control the
0 1 2
ADS1100’s operating mode, data rate, and PGA settings. 1 0 4
The configuration register’s format is shown in Table IV. The 1 1 8
default setting is 8CH. NOTE: (1) Default Setting.

TABLE VII. PGA Bits.

BIT 7 6 5 4 3 2 1 0

NAME ST/BSY 0 0 SC DR1 DR0 PGA1 PGA0 READING FROM THE ADS1100
TABLE IV. Configuration Register. You can read the output register and the contents of the
configuration register from the ADS1100. To do this, address
Bit 7: ST/BSY the ADS1100 for reading, and read three bytes from the
device. The first two bytes are the output register’s contents;
The meaning of the ST/BSY bit depends on whether it is
the third byte is the configuration register’s contents.
being written to or read from.
You do not always have to read three bytes from the
In single conversion mode, writing a 1 to the ST/BSY bit
ADS1100. If you want only the contents of the output regis-
causes a conversion to start, and writing a 0 has no effect.
ter, read only two bytes.

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

TABLE V. Output Register.

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Reading more than three bytes from the ADS1100 has no do this, address the ADS1100 for writing, and write one byte
effect. All of the bytes beginning with the fourth will be FFH. to it. This byte is written into the configuration register.
A timing diagram for an ADS1100 read operation is shown in Writing more than one byte to the ADS1100 has no effect.
Figure 2. The ADS1100 will ignore any bytes sent to it after the first
one, and it will only acknowledge the first byte.
WRITING TO THE ADS1100 A timing diagram for an ADS1100 write operation is shown in
You can write new contents into the configuration register Figure 3.
(you cannot change the contents of the output register). To

1 9 1 9
SCL …

SDA
1 0 0 1 A2 A1 A0 R/W D15 D14 D13 D12 D11 D10 D9 D8 …
Start By ACK By From ACK By
Master ADS1100 ADS1100 Master
Frame 1: I2C Slave Address Byte Frame 2: Output Register Upper Byte

1 9 1 9
SCL
(Continued)
…

SDA ST/
(Continued)
… D7 D6 D5 D4 D3 D2 D1 D0
BSY
0 0 SC DR1 DR0 PGA1 PGA0

From ACK By From ACK By Stop By

ADS1100 Master ADS1100 Master Master
Frame 3: Output Register Lower Byte Frame 4: Configuration Register
(Optional)

FIGURE 2. Timing Diagram for Reading From the ADS1100.

1 9 1 9

SCL

A2 ST/
SDA 1 0 0 1 A1 A0 R/W 0 0 SC DR1 DR0 PGA1 PGA0 Stop By
BSY
Master
Start By ACK By ACK By
Master ADS1100 ADS1100
Frame 1: I2C Slave Address Byte Frame 2: Configuration Register

FIGURE 3. Timing Diagram for Writing to the ADS1100.

ADS1100 11
SBAS239 www.ti.com
PACKAGE DRAWING
MPDS026D – FEBRUARY 1997 – REVISED FEBRUARY 2002

DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE

0,50
0,95 6X 0,20 M
0,25
6 4

0,15 NOM
1,70 3,00
1,50 2,60

1 3
Gage Plane
3,00
2,80
0,25
0 –8
0,55
0,35

Seating Plane

1,45
0,05 MIN 0,10
0,95

4073253-5/G 01/02

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.

12
ADS1100
www.ti.com SBAS239
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