High Precision Voltage Reference

AD588*
FEATURES FUNCTIONAL BLOCK DIAGRAM
Low Drift: 1.5 ppm/ⴗC
NOISE A3 OUT
Low Initial Error: 1 mV REDUCTION VHIGH A3 IN SENSE
Pin Programmable Output:
+10 V, +5 V, +65 V Tracking, –5 V, –10 V
Flexible Output Force and Sense Terminals A3 OUT
A3
High Impedance Ground Sense RB FORCE

Machine lnsertable DIP Packaging A1

MIL-STD-883 Compliant Versions Available A4 OUT
R1 R4 SENSE

A4 OUT
A4
GENERAL DESCRIPTION R2
R5
FORCE
The AD588 represents a major advance in the state-of-the-art
in monolithic voltage references. Low initial error and low tem- R6 +VS
R3
perature drift give the AD588 absolute accuracy performance A2 AD588
previously not available in monolithic form. The AD588 uses a –VS
proprietary ion-implanted buried Zener diode, and laser-wafer-
drift trimming of high stability thin-film resistors to provide GAIN GND GND VLOW BAL VCT A4 IN
outstanding performance at low cost. ADJ SENSE SENSE ADJ
+IN –IN
The AD588 includes the basic reference cell and three additional
amplifiers that provide pin programmable output ranges. The
amplifiers are laser-trimmed for low offset and low drift to main-
tain the accuracy of the reference. The amplifiers are configured PRODUCT HIGHLIGHTS
to allow Kelvin connections to the load and/or boosters for driv- 1. The AD588 offers 12-bit absolute accuracy without any user
ing long lines or high current loads, delivering the full accuracy adjustments. Optional fine-trim connections are provided for
of the AD588 where it is required in the application circuit. applications requiring higher precision. The fine trimming does
not alter the operating conditions of the Zener or the buffer
The low initial error allows the AD588 to be used as a system amplifiers, and thus does not increase the temperature drift.
reference in precision measurement applications requiring 12-bit
absolute accuracy. In such systems, the AD588 can provide a 2. Output noise of the AD588 is very low—typically 6 µV p-p.
known voltage for system calibration in software, and the low A pin is provided for additional noise filtering using an exter-
drift allows compensation for the drift of other components in nal capacitor.
a system. Manual system calibration and the cost of periodic 3. A precision ± 5 V tracking mode with Kelvin output connec-
recalibration can therefore be eliminated. Furthermore, the tions is available with no external components. Tracking error
mechanical instability of a trimming potentiometer and the is less than 1 mV and a fine-trim is available for applications
potential for improper calibration can be eliminated by using requiring exact symmetry between the +5 V and –5 V outputs.
the AD588 in conjunction with autocalibration software. 4. Pin strapping capability allows configuration of a wide vari-
The AD588 is available in four versions. The AD588JQ and ety of outputs: ± 5 V, +5 V, +10 V, –5 V, and –10 V dual
AD588KQ and grades are packaged in a 16-lead CERDIP and outputs or +5 V, –5 V, +10 V, and –10 V single outputs.
are specified for 0°C to 70°C operation. AD588AQ and BQ
grades are packaged in a 16-lead CERDIP and are specified for
the –25°C to +85°C industrial temperature range.

*Protected by Patent Number 4,644,253.

REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003, Analog Devices, Inc. All rights reserved.
AD588–SPECIFICATIONS (Typical @ 25°C, 10 V output, V = ⴞ15 V, unless otherwise noted. ) S
1

AD588JQ/AQ AD588BQ/KQ
Parameter Min Typ Max Min Typ Max Unit
OUTPUT VOLTAGE ERROR
+10 V, –10 V Outputs ±3 –1 +1 mV
+5 V, –5 V Outputs ±3 –1 +1 mV
± 5 V TRACKING MODE
Symmetry Error ± 1.5 ± 0.75 mV
OUTPUT VOLTAGE DRIFT
0°C to 70°C (J, K, B) ±2 ±3 ± 1.5 ppm/°C
–25°C to +85°C (A, B) ±3 ±3 ppm/°C
GAIN ADJ AND BAL ADJ2
Trim Range ±4 ±4 mV
Input Resistance 150 150 kΩ
LINE REGULATION
TMIN to TMAX3 ± 200 ± 200 µV/V
LOAD REGULATION
TMIN to TMAX
+10 V Output, 0 mA < IOUT < 10 mA ± 50 ± 50 µV/mA
–10 V Output, –10 mA < IOUT < 0 mA ± 50 ± 50 µV/mA
SUPPLY CURRENT
TMIN to TMAX 6 10 6 10 mA
Power Dissipation 180 300 180 300 mW
OUTPUT NOISE (Any Output)
0.1 Hz to 10 Hz 6 6 µV p-p
Spectral Density, 100 Hz 100 100 nV/√Hz
LONG-TERM STABILITY (@ 25°C) 15 15 ppm/1000 hr
BUFFER AMPLIFIERS
Offset Voltage 100 10 µV
Offset Voltage Drift 1 1 µV/°C
Bias Current 20 20 nA
Open-Loop Gain 110 110 dB
Output Current A3, A4 –10 +10 –10 +10 mA
Common-Mode Rejection (A3, A4)
VCM = 1 V p-p 100 100 dB
Short Circuit Current 50 50 mA
TEMPERATURE RANGE
Specified Performance
J, K Grades 0 70 0 70 °C
A, B Grades –25 +85 –25 +85 °C
NOTES
1
Output Configuration
+10 V Figure 2a
–10 V Figure 2c
+5 V, –5 V, ± 5 V Figure 2b
Specifications tested using +10 V configuration, unless otherwise indicated.
2
Gain and balance adjustments guaranteed capable of trimming output voltage error and symmetry error to zero.
3
Test Conditions:
+10 V Output –VS = –15 V, 13.5 V ≤ +VS ≤ 18 V
–10 V Output –18 V ≤ –VS ≤ –13.5 V, +VS = 15 V
± 5 V Output +VS = +18 V, –VS = –18 V
+VS = +10.8 V, –V S = –10.8 V
For ± 10 V output, ± VS can be as low as ± 12 V.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

–2– REV. D
 AD588
ABSOLUTE MAXIMUM RATINGS*
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V PIN CONFIGURATION
Power Dissipation (25°C) . . . . . . . . . . . . . . . . . . . . . . 600 mW
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
A3 OUT FORCE 1 16 –VS
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
+VS 2 15 A4 OUT FORCE
Package Thermal Resistance (␪JA/␪JC) . . . . . . . . 90°C/25°C/W
Output Protection: All Outputs Safe if Shorted to Ground A3 OUT SENSE 3 14 A4 OUT SENSE

A3 IN 4 AD588 13 A4 IN
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
TOP VIEW
nent damage to the device. This is a stress rating only; functional operation of the GAIN ADJ 5 (Not to Scale) 12 BAL ADJ
device at these or any other conditions above those indicated in the operational VHIGH 6 11 VCT
sections of this specification is not implied. Exposure to absolute maximum rating NOISE 7 10 GND SENSE –IN
conditions for extended periods may affect device reliability. REDUCTION
VLOW 8 9 GND SENSE +IN

ORDERING GUIDE

Part Number1 Initial Error (mV) Temperature Coefficient2 Temperature Range (°C) Package Option
AD588AQ 3 3 ppm/°C –25 to +85 CERDIP (Q-16)
AD588BQ 1 1.5 ppm/°C –25 to +852 CERDIP (Q-16)
AD588JQ 3 3 ppm/°C 0 to 70 CERDIP (Q-16)
AD588KQ 1 1.5 ppm/°C 0 to 70 CERDIP (Q-16)
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current
AD588/883B.
2
Temperature coefficient specified from 0°C to 70°C.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD588 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. D –3–
AD588
THEORY OF OPERATION APPLYING THE AD588
The AD588 consists of a buried Zener diode reference, amplifiers The AD588 can be configured to provide +10 V and –10 V
used to provide pin programmable output ranges, and associ- reference outputs as shown in Figures 2a and 2c, respectively. It
ated thin-film resistors as shown in Figure 1. The temperature can also be used to provide +5 V, –5 V, or a ± 5 V tracking
compensation circuitry provides the device with a temperature reference, as shown in Figure 2b. Table I details the appropriate
coefficient of 1.5 ppm/°C or less. pin connections for each output range. In each case, Pin 9 is
connected to system ground and power is applied to Pins 2 and 16.
NOISE A3 OUT
REDUCTION VHIGH A3 IN SENSE The architecture of the AD588 provides ground sense and
uncommitted output buffer amplifiers that offer the user a great
deal of functional flexibility. The AD588 is specified and tested
A3 A3 OUT in the configurations shown in Figure 2a. The user may choose
RB FORCE
to take advantage of the many other configuration options available
A1 with the AD588. However, performance in these configurations
A4 OUT
R1 R4 SENSE is not guaranteed to meet the extremely stringent data sheet
specifications.
A4 OUT
R2 A4 As indicated in Table I, a +5 V buffered output can be provided
FORCE
R5
using amplifier A4 in the +10 V configuration (Figure 2a). A –5 V
R6 +VS buffered output can be provided using amplifier A3 in the –10 V
R3
A2 AD588 configuration (Figure 2c). Specifications are not guaranteed for
–VS the +5 V or –5 V outputs in these configurations. Performance
will be similar to that specified for the +10 V or –10 V outputs.
GAIN GND GND VLOW BAL VCT A4 IN As indicated in Table I, unbuffered outputs are available at
ADJ SENSE SENSE ADJ
+IN –IN Pins 6, 8, and 11. Loading of these unbuffered outputs will
impair circuit performance.
Figure 1. AD588 Functional Block Diagram
Amplifiers A3 and A4 can be used interchangeably. However,
Amplifier A1 performs several functions. A1 primarily acts to the AD588 is tested (and the specifications are guaranteed) with
amplify the Zener voltage from 6.5 V to the required 10 V output. the amplifiers connected as indicated in Figure 2a and Table I.
In addition, A1 also provides for external adjustment of the When either A3 or A4 is unused, its output force and sense pins
10 V output through Pin 5, GAIN ADJ. Using the bias compen- should be connected and the input tied to ground.
sation resistor between the Zener output and the noninverting
Two outputs of the same voltage may be obtained by connect-
input to A1, a capacitor can be added at the NOISE REDUCTION
ing both A3 and A4 to the appropriate unbuffered output on
pin (Pin 7) to form a low-pass filter and reduce the noise contri-
Pins 6, 8, or 11. Performance in these dual-output configura-
bution of the Zener to the circuit. Two matched 10 kΩ nominal
tions will typically meet data sheet specifications.
thin-film resistors (R4 and R5) divide the 10 V output in half.
Pin VCT (Pin 11) provides access to the center of the voltage
CALIBRATION
span and Pin 12 (BAL ADJ) can be used for fine adjustment
Generally, the AD588 will meet the requirements of a precision
of this division.
system without additional adjustment. Initial output voltage
Ground sensing for the circuit is provided by amplifier A2. The error of 1 mV and output noise specs of 10 µV p-p allow for
noninverting input (Pin 9) senses the system ground, which accuracies of 12 bits to 16 bits. However, in applications where
will be transferred to the point on the circuit where the invert- an even greater level of accuracy is required, additional calibra-
ing input (Pin 10) is connected. This may be Pin 6, 8, or 11. tion may be called for. Provision for trimming has been made
The output of A2 drives Pin 8 to the appropriate voltage. Thus, if through the use of the GAIN ADJ and BAL ADJ pins (Pins 5 and
Pin 10 is connected to Pin 8, the VLOW pin will be the same 12, respectively).
voltage as the system ground. Alternatively, if Pin 10 is con-
The AD588 provides a precision 10 V span with a center tap
nected to the VCT pin, it will be ground and Pin 6 and Pin 8 will
(VCT) that is used with the buffer and ground sense amplifiers to
be +5 V and –5 V, respectively.
achieve the voltage output configurations in Table I. GAIN
Amplifiers A3 and A4 are internally compensated and are used ADJUST and BALANCE ADJUST can be used in any of these
to buffer the voltages at Pins 6, 8, and 11, as well as to provide a configurations to trim the magnitude of the span voltage and
full Kelvin output. Thus, the AD588 has a full Kelvin capability the position of the center tap within the span. The GAIN
by providing the means to sense a system ground and provide ADJUST should be performed first. Although the trims are not
forced and sensed outputs referenced to that ground. interactive within the device, the GAIN trim will move the
BALANCE trim point as it changes the magnitude of the span.

–4– REV. D
 AD588
Table I. Pin Connections

Connect Buffered
Pin 10 Unbuffered* Output on Pins Output Buffered Output on Pins
Range to Pin: –10 V –5 V 0 V +5 V +10 V Connections –10 V –5 V 0V +5 V +10 V
+10 V 8 8 11 6 11 to 13, 14 to 15 15
6 to 4, and 3 to 1 1
–5 V or +5 V 11 8 11 6 8 to 13, 14 to 15, 15
6 to 4, and 3 to 1 1
–10 V 6 8 11 6 8 to 13, 14 to 15, 15
11 to 4, and 3 to 1 1
+5 V 11 6 6 to 4 and 3 to 1 1

–5 V 11 8 8 to 13 and 14 to 15 15
*Unbuffered outputs should not be loaded.

Figure 2b shows GAIN and BALANCE trims in a +5 V and

–5 V tracking configuration. A 100 kΩ 20-turn potentiometer is
A3 +10V
used for each trim. The potentiometer for GAIN trim is con- RB
nected between Pin 6 (VHIGH) and Pin 8 (VLOW) with the wiper A1
connected to Pin 5 (GAIN ADJ). The potentiometer is adjusted
R1 R4
to produce exactly 10 V between Pin 1 and Pin 15, the amplifier
outputs. The BALANCE potentiometer, also connected between A4 +5V
R2
Pin 6 and Pin 8 with the wiper to Pin 12 (BAL ADJ), is then R5
adjusted to center the span from +5 V to –5 V. +VS +15V
R6 0.1␮F
Trimming in other configurations works in exactly the same R3 AD588 SYSTEM
A2
manner. When producing +10 V and +5 V, GAIN ADJ is used –VS GROUND
to trim +10 V and BAL ADJ is used to trim +5 V. In the –10 V 0.1␮F

and –5 V configuration, GAIN ADJ is again used to trim the –15V

magnitude of the span, –10 V, while BAL ADJ is used to trim

SYSTEM
the center tap, –5 V. GROUND
In single output configurations, GAIN ADJ is used to trim outputs
Figure 2a. +10 V Output
utilizing the full span (+10 V or –10 V), while BAL ADJ is used
to trim outputs using half the span (+5 V or –5 V). +15V
NOISE
Input impedance on both the GAIN ADJ and BAL ADJ pins is 1␮F REDUCTION
approximately 150 kΩ. The GAIN ADJUST trim network
effectively attenuates the 10 V across the trim potentiometer
by a factor of about 1500 to provide a trim range of –3.5 mV to
A3 +5V
+7.5 mV with a resolution of approximately 550 µV/turn RB
(20-turn potentiometer). The BAL ADJ trim network attenu- A1
ates the trim voltage by a factor of about 1400, providing a
R1 R4
trim range of ± 4.5 mV with resolution of 450 µV/turn.
R2 A4 –5V
R5

+VS –15V
R6 0.1␮F
R3 AD588
A2 SYSTEM
–VS GROUND
0.1␮F
–15V

SYSTEM
GROUND
100k⍀
20T
BALANCE
ADJUST

100k⍀
20T
GAIN ADJUST

Figure 2b. +5 V and –5 V Outputs

REV. D –5–
AD588
0.1␮F Note that a second capacitor is needed in order to implement
the NOISE REDUCTION feature when using the AD588 in
0.1␮F
NOISE
the –10 V mode (Figure 2c.). The NOISE REDUCTION capaci-
REDUCTION tor is limited to 0.1 µF maximum in this mode.

A3 –5V
RB

A1

R1 R4

R2 A4 –10V
R5

+VS +15V
R6 0.1␮F
R3 AD588
A2 SYSTEM
–VS GROUND
0.1␮F
–15V Figure 4. Effect of 1 µ F Noise Reduction Capacitor
on Broadband Noise
SYSTEM
GROUND
TURN-ON TIME
Upon application of power (cold start), the time required for the
Figure 2c. –10 V Output
output voltage to reach its final value within a specified error
Trimming the AD588 introduces no additional errors over band is the turn-on settling time. Two components normally
temperature, so precision potentiometers are not required. associated with this are: time for active circuits to settle and
For single-output voltage ranges, or in cases when BALANCE time for thermal gradients on the chip to stabilize. Figures 5a
ADJUST is not required, Pin 12 should be connected to Pin 11. and 5b show the turn-on characteristics of the AD588. It
If GAIN ADJUST is not required, Pin 5 should be left floating. shows the settling to be about 600 µs. Note the absence of any
thermal tails when the horizontal scale is expanded to 2 ms/cm in
NOISE PERFORMANCE AND REDUCTION Figure 5b.
The noise generated by the AD588 is typically less than 6 µV p-p
over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz bandwidth is
approximately 600 µV p-p. The dominant source of this noise is
the buried Zener, which contributes approximately 100 nV/√Hz.
In comparison, the op amp’s contribution is negligible. Figure 3
shows the 0.1 Hz to 10 Hz noise of a typical AD588.

Figure 5a. Electrical Turn-On

Figure 3. 0.1 Hz to 10 Hz Noise (0.1 Hz to 10 Hz BPF

with Gain of 1000 Applied)
If further noise reduction is desired, an optional capacitor, CN,
may be added between the NOISE REDUCTION pin and ground,
as shown in Figure 2b. This will form a low-pass filter with the
4 kΩ RB on the output of the Zener cell. A 1 µF capacitor will
have a 3 dB point at 40 Hz and will reduce the high frequency
(to 1 MHz) noise to about 200 µV p-p. Figure 4 shows the 1 MHz Figure 5b. Extended Time Scale Turn-On
noise of a typical AD588 both with and without a 1 µF capacitor.
Output turn-on time is modified when an external noise reduc-
tion capacitor is used. When present, this capacitor presents an

–6– REV. D
 AD588
additional load to the internal Zener diode’s current source, DEVICE
MAXIMUM OUTPUT CHANGE – mV

resulting in a somewhat longer turn-on time. In the case of a GRADE 0ⴗC TO +70ⴗC –25ⴗC TO +85ⴗC –55ⴗC TO +125ⴗC

1 µF capacitor, the initial turn-on time is approximately 60 ms AD588JQ 2.10

(see Figure 6). AD588JQ 1.05
AD588JQ 1.40(typ) 3.30
Note: If the NOISE REDUCTION feature is used in the ± 5 V AD588JQ 1.05 3.30
configuration, a 39 kΩ resistor between Pin 6 and Pin 2 is required AD588JQ 10.80
for proper startup. AD588JQ 7.20

Figure 8. Maximum Output Change—mV

KELVIN CONNECTIONS
Force and sense connections, also referred to as Kelvin connec-
tions, offer a convenient method of eliminating the effects of
voltage drops in circuit wires. As seen in Figure 9, the load
current and wire resistance produce an error (VERROR = R × IL) at
the load. The Kelvin connection of Figure 9 overcomes the
problem by including the wire resistance within the forcing loop
of the amplifier and sensing the load voltage. The amplifier
corrects for any errors in the load voltage. In the circuit shown,
Figure 6. Turn-On with CN = 1 ␮F the output of the amplifier would actually be at 10 V + VERROR and
the voltage at the load would be the desired 10 V.
TEMPERATURE PERFORMANCE The AD588 has three amplifiers that can be used to implement
The AD588 is designed for precision reference applications Kelvin connections. Amplifier A2 is dedicated to the ground
where temperature performance is critical. Extensive tempera- force-sense function, while uncommitted amplifiers A3 and A4
ture testing ensures that the device’s high level of performance is are free for other force-sense chores.
maintained over the operating temperature range.
R
Figure 7 shows typical output voltage drift for the AD588BD
and illustrates the test methodology. The box in Figure 7 is I=0
V = 10V
bounded on the sides by the operating temperature extremes R V = 10V – RIL R
and on top and bottom by the maximum and minimum output + IL RLOAD
10V IL RLOAD I=0
voltages measured over the operating temperature range. The –
V = 10V + RIL
slope of the diagonal drawn from the lower left corner of the
box determines the performance grade of the device. Figure 9. Advantage of Kelvin Connection
OUTPUT In some single-output applications, one amplifier may be unused.
VOLTS
10.002 In such cases, the unused amplifier should be connected as a
unity-gain follower (force + sense pin tied together), and the
VMAX
input should be connected to ground.
10.001 An unused amplifier section may be used for other circuit functions
VMAX – VMIN as well. Figures 10 through 14 show the typical performance of
SLOPE = T.C. =
(TMAX – TMIN ) × 10 × 1–6
VMIN A3 and A4.
10.0013V − 10.00025V
10.000
(85°C − –25°C) × 10 × 10–6
100 0
= 0.95ppm / °C
–35 –15 5 25 45 65 85
TEMPERATURE – ⴗC
Tmin Tmax 80 –30
GAIN
Figure 7. Typical AD588BD Temperature Drift
60 –60
OPEN-LOOP GAIN – dB

Each AD588A and B grade unit is tested at –25°C, 0°C, +25°C,

PHASE – Degrees

+50°C, +70°C, and +85°C. This approach ensures that the

40 –90
variations of output voltage that occur as the temperature changes PHASE
within the specified range will be contained within a box whose
20 –120
diagonal has a slope equal to the maximum specified drift. The
position of the box on the vertical scale will change from device
to device as initial error and the shape of the curve vary. Maxi- 0 –150

mum height of the box for the appropriate temperature range is

shown in Figure 8. Duplication of these results requires a combi- –20 –180
10 100 1k 10k 100k 1M 10M
nation of high accuracy and stable temperature control in a test FREQUENCY – Hz
system. Evaluation of the AD588 will produce a curve similar to
that in Figure 7, but output readings may vary depending on the Figure 10. Open-Loop Frequency Response (A3, A4)
test methods and equipment utilized.
REV. D –7–
AD588
110 110
VS = ⴞ15V WITH VS = ⴞ15V
1V p-p SINE WAVE VCM = 1V p-p +25ⴗC
100 100
+SUPPLY
POWER SUPPLY REJECTION – dB

80 80

CMRR – dB
60 60
–SUPPLY

40 40

20 20

10 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz

Figure 11. Power Supply Rejection vs. Frequency (A3, A4) Figure 13. Common-Mode Rejection vs.
Frequency (A3, A4)

100

90

NOISE SPECTRAL DENSITY – nV/ Hz

80

70

60

50

40

30

20

Figure 12a. Unity-Gain Follower Pulse Response 10

(Large Signal) 0
1 10 100 1k 10k
FREQUENCY – Hz

Figure 14. Input Noise Voltage Spectral Density

DYNAMIC PERFORMANCE
The output buffer amplifiers (A3 and A4) are designed to
provide the AD588 with static and dynamic load regulation
superior to less complete references.
Many A/D and D/A converters present transient current loads
to the reference, and poor reference response can degrade the
converter’s performance.
Figures 15a and 15b display the characteristics of the AD588
Figure 12b. Unity-Gain Follower Pulse Response output amplifier driving a 0 mA to 10 mA load.
(Small Signal)
A3 OR A4 1k⍀

VOUT
IL
10V VL 10V
0V

Figure 15a. Transient Load Test Circuit

–8– REV. D
 AD588

Figure 15b. Large-Scale Transient Response Figure 17b. Output Response with Capacitive Load
Figures 16a and 16b display the output amplifier characteristics Figures 18a and 18b display the crosstalk between output am-
driving a 5 mA to 10 mA load, a common situation found when plifiers. The top trace shows the output of A4, dc-coupled and
the reference is shared among multiple converters or is used to offset by 10 V, while the output of A3 is subjected to a 0 mA
provide a bipolar offset current. to 10 mA load current step. The transient at A4 settles in about
1 µs, and the load-induced offset is about 100 µV.
A3 OR A4

VOUT
IL VOUT
+ 2k⍀ 2k⍀ A4 A3
10V + 1k⍀ +
VL 10V
– 0V 10V 10V 10V
VL
– 0V –

Figure 16a. Transient and Constant Load Test Circuit

Figure 18a. Load Crosstalk Test Circuit

Figure 16b. Transient Response 5 mA to10 mA Load

Figure 18b. Load Crosstalk
In some applications, a varying load may be both resistive and
capacitive in nature or be connected to the AD588 by a long
capacitive cable.
Figures 17a and 17b display the output amplifier characteristics
driving a 1,000 pF, 0 mA to 10 mA load.

A3 OR A4

VOUT
1000pF 1k⍀
CL
10V
VL 10V
0V

Figure 17a. Capacitive Load Transient Response

Test Circuit

REV. D –9–
AD588
Attempts to drive a large capacitive load (in excess of 1,000 pF) USING THE AD588 WITH CONVERTERS
may result in ringing or oscillation, as shown in the step response The AD588 is an ideal reference for a wide variety of A/D and
photo (Figure 19a). This is due to the additional pole formed by D/A converters. Several representative examples follow.
the load capacitance and the output impedance of the amplifier, 14-Bit Digital-to-Analog Converter—AD7535
which consumes phase margin. The recommended method of High resolution CMOS D/A converters require a reference voltage
driving capacitive loads of this magnitude is shown in Figure 19b. of high precision to maintain rated accuracy. The combination
The 150 Ω resistor isolates the capacitive load from the output of the AD588 and AD7535 takes advantage of the initial accu-
stage, while the 10 kΩ resistor provides a dc feedback path and racy, drift, and full Kelvin output capability of the AD588 as
preserves the output accuracy. The 1 µF capacitor provides a well as the resolution, monotonicity, and accuracy of the AD7535
high frequency feedback loop. The performance of this circuit is to produce a subsystem with outstanding characteristics. See
shown in Figure 19c. Figure 20.
16-Bit Digital-to-Analog Converter—AD569
Another application that fully utilizes the capabilities of the
AD588 is supplying a reference for the AD569, as shown in
Figure 21. Amplifier A2 senses system common and forces VCT
to assume this value, producing +5 V and –5 V at Pin 6 and
Pin 8, respectively. Amplifiers A3 and A4 buffer these voltages
out to the appropriate reference force-sense pins of the AD569.
The full Kelvin scheme eliminates the effect of the circuit traces
or wires and the wire bonds of the AD588 and AD569 them-
selves, which would otherwise degrade system performance.

SUBSTITUTING FOR INTERNAL REFERENCES

Many converters include built-in references. Unfortunately,
such references are the major source of drift in these converters.
Figure 19a. Output Amplifier Step Response, CL = 1 µ F
By using a more stable external reference like the AD588, drift
performance can be improved dramatically.
10k⍀
1␮F

150⍀ VOUT

+ CL
VIN
1␮F
–

Figure 19b. Compensation for Capacitive Loads

Figure 19c. Output Amplifier Step Response

Using Figure 19b Compensation

–10– REV. D
 AD588
N.C. VDD

VREFS
RFS

14-BIT DAC IOUT

+10V
VREFF
A3
RB 14 AD7535
A1 AGNDS
AD588
R1 R4
DAC REGISTER LDAC
AGNDF
R2 A4 6 8
R5
MS LS
CSLSB
INPUT INPUT
R6 +VS REGISTER REGISTER
R3
A2 CSMSB
–VS
WR

DB13 DB0 DGND VSS

Figure 20. AD588/AD7535 Connections

+12V
–12V
+VS –VS

VH A3 + IN
A3 +VREF
OUT FORCE
A3
+VREF AD569
A3 – IN +5V SENSE

A1
S S
10k⍀ S
E E
VCT E
L L
G T VOUT
E E
M A –5V TO
10k⍀ A2 – IN C C
E P +5V
T T
A2 A2 + IN N
O O
T
R R
–VREF
A4 – IN –5V SENSE
AD588 A4 –VREF
OUT FORCE
A4

VL A4 + IN
8 MSBs 8 LSBs
GND LATCHES

CS LDAC HBE LBE

DB15 DB0

Figure 21. High Accuracy ± 5 V Tracking Reference for AD569

REV. D –11–
AD588
12-Bit Analog-to-Digital Converter—AD574A ohms measurement overcomes this problem. This method uses
The AD574A is specified for gain drift from 10 ppm/°C to two wires to bring an excitation current to the RTD and two
50 ppm/°C, (depending on grade) using its on-chip reference. additional wires to tap off the resulting RTD voltage. If these
The reference contributes typically 75% of this drift. Therefore, additional two wires go to a high input impedance measurement
the total drift using an AD588 to supply the reference can be circuit, the effect of their resistance is negligible. Therefore, they
improved by a factor of 3 to 4. transmit the true RTD voltage.
Using this combination may result in apparent increases in full-
I=0
scale error due to the difference between the on-board reference R

by which the device is laser-trimmed and the external reference R

+
with which the device is actually applied. The on-board reference IEXC VOUT ␣R RTD
RTD
is specified to be 10 V ± 100 mV, while the external reference is –
specified to be 10 V ± 1 mV. This may result in up to 101 mV R R
of apparent full-scale error beyond the ± 25 mV specified AD574
I=0
gain error. External resistors R2 and R3 allow this error to be
nulled. Their contribution to full-scale drift is negligible. Figure 23. 4-Wire Ohms Measurement
The high output drive capability allows the AD588 to drive up A practical consideration when using the 4-wire ohms technique
to six converters in a multiconverter system. All converters will with an RTD is the self-heating effect that the excitation current
have gain errors that track to better than ± 5 ppm/°C. has on the temperature of the RTD. The designer must choose
the smallest practical excitation current that still gives the desired
RTD EXCITATION resolution. RTD manufacturers usually specify the self-heating
The resistance temperature detector (RTD) is a circuit element effect of each of their models or types of RTDs.
whose resistance is characterized by a positive temperature Figure 24 shows an AD588 providing the precision excitation
coefficient. A measurement of resistance indicates the measured current for a 100 Ω RTD. The small excitation current of 1 mA
temperature. Unfortunately, the resistance of the wires leading dissipates a mere 0.1 mW of power in the RTD.
to the RTD often adds error to this measurement. The 4-wire

12 8 STS

CS
HIGH
BITS
AO

R/C
MIDDLE
BITS
CE
R1
50⍀
AD574A
A3 REF IN
RB R3 LOW
500⍀ BITS
REF OUT
A1 20 TURN

R1 R4 BIPP OFF +5V

R2
61.9⍀
VIN 10VIN +15V
R2 A4
R5 10V
20VIN –15V

R6 +VS ANA COM DIG

R3
AD588 COM
A2
–VS

Figure 22. AD588/AD574A Connections

–12– REV. D
 AD588
RC voltage equal to approximately VIN/2. Further processing of this
VISHAY S102C signal may necessarily be limited to high common-mode rejec-
OR SIMILAR
tion techniques such as instrumentation or isolation amplifiers.
A3 Figure 26b shows the same bridge transducer, this time driven
RB
from a pair of bipolar supplies. This configuration ideally elimi-
A1
RC = 10k⍀
nates the common-mode voltage and relaxes the restrictions on
R1 R4 any processing elements that follow.
1.0mA
0.01%
R2 A4 +
R5
100⍀ VOUT
R4 R3
+VS +
R6 – +
R3 – VIN
EO
A2 AD588 –
–VS –15V R1 R2
OR
GROUND

Figure 26a. Bridge Transducer Excitation—

Unipolar Drive
RTD = OMEGA K4515
0.24ⴗC/mW SELF-HEATING
+
V1 R4 R3
Figure 24. Precision Current Source for RTD – – +
EO
+ R1
V2 R2
BOOSTED PRECISION CURRENT SOURCE –
In the RTD current-source application, the load current is
limited to ± 10 mA by the output drive capability of amplifier Figure 26b. Bridge Transducer Excitation—
A3. In the event that more drive current is needed, a series-pass Bipolar Drive
transistor can be inserted inside the feedback loop to provide
+15V
higher current. Accuracy and drift performance are unaffected
by the pass transistor. 220⍀ Q1 =
2N3904

VCC

220⍀
A3 Q1
RB A3
RB – +
EO
A1 AD588 A1 AD588
R1 R4
R1 R4

A4 220⍀ Q2 =
R2 A4
R5 R2 2N3904
R5
10V
+VS IL = –15V
R6 RC
R3 R6 +VS
R3
A2
–VS A2
–VS

LIMITED BY
Q1 AND RC
POWER
DISSIPATION
LOAD Figure 27. Bipolar Bridge Drive

As shown in Figure 27, the AD588 is an excellent choice for the

Figure 25. Boosted Precision Current Source control element in a bipolar bridge driver scheme. Transistors
Q1 and Q2 serve as series-pass elements to boost the current
BRIDGE DRIVER CIRCUITS drive capability to the 28 mA required by a typical 350 Ω bridge.
The Wheatstone bridge is a common transducer. In its simplest A differential gain stage may still be required if the bridge balance
form, a bridge consists of four, two-terminal elements connected is not perfect. Such gain stages can be expensive.
to form a quadrilateral, a source of excitation connected along
one of the diagonals and a detector comprising the other diago-
nal. Figure 26a shows a simple bridge driven from a unipolar
excitation supply. EO, a differential voltage, is proportional to
the deviation of the element from the initial bridge values. Unfor-
tunately, this bridge output voltage is riding on a common-mode

REV. D –13–
AD588
Additional common-mode voltage reduction is realized by using
the circuit illustrated in Figure 28. A1, the ground sense ampli-
fier, serves the supplies on the bridge to maintain a virtual ground
at one center tap. The voltage that appears on the opposite
center tap is now single-ended (referenced to ground) and can
be amplified by a less expensive circuit.
+15V

220⍀ Q1 =
2N3904

A3 AD OP-07
RB
+
A1 VOUT
–
R1 R4 R1

220⍀
Q2 =
R2 A4
2N3904
R5 R2

–15V
R6 +VS
R3
A2 AD588
–VS

Figure 28. Floating Bipolar Bridge Drive with Minimum CMV

–14– REV. D
 AD588
OUTLINE DIMENSIONS

16-Lead Ceramic DIP-Glass Hermetic Seal Package [CERDIP]

(Q-16)
Dimensions shown in inches and (millimeters)

0.005 0.098 (2.49)

(0.13) MAX 0.310 (7.87)
MIN 16 9 0.220 (5.59)
PIN 1
1 8

0.060 (1.52)
0.200 (5.08) 0.320 (8.13)
0.840 (21.34) MAX 0.015 (0.38)
MAX 0.290 (7.37)
0.150 (3.81)
MIN
0.015 (0.38)
0.200 (5.08) 15 0.008 (0.20)
0.125 (3.18) 0.100 0.070 (1.78) SEATING 0
0.023 (0.58) (2.54) PLANE
0.030 (0.76)
BSC
0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Revision History
Location Page
2/03—Data Sheet changed from REV. C to REV. D.
Added KQ model and deleted SQ and TQ models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10/02—Data Sheet changed from REV. B to REV. C.
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to TABLE 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deleted Figure 10c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OUTLINE DIMENSIONS updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

REV. D –15–
–16–
PRINTED IN U.S.A. C00531–0–2/03(D)