Multiple Choice Questions

1. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

a) The logic level at the D input is transferred to Q on NGT of CLK.
b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
c) The Q output is ALWAYS identical to the D input when CLK = PGT.

d) The Q output is ALWAYS identical to the D input.

2. Propagation delay time, tp, is measured from the ________.

a) triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
b) triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
c) preset input to the LOW-to-HIGH transition of the output
d) clear input to the HIGH-to-LOW transition of the output

3. How is a J-K flip-flop made to toggle?

a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1

4. How many flip-flops are required to produce a divide-by-128 device?

a) 1
b) 4
c) 6
d) 7

5. On a master-slave flip-flop, when is the master enabled?

a) when the gate is LOW
b) when the gate is HIGH
c) both of the above
d) neither of the above

6. One example of the use of an S-R flip-flop is as a(n):

a) Racer
b) astable oscillator
c) binary storage register
d) transition pulse generator

7. Which of the following is correct for a gated D flip-flop?

a) The output toggles if one of the inputs is held HIGH.
b) Only one of the inputs can be HIGH at a time.
c) The output complement follows the input when enabled.
d) Q output follows the input D when the enable is HIGH.

8. With regard to a D latch, ________.

a) the Q output follows the D input when EN is LOW
b) the Q output is opposite the D input when EN is LOW
c) the Q output follows the D input when EN is HIGH
d) the Q output is HIGH regardless of EN's input state

9. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
a) It can't be done.
b) Invert the Q outputs.
c) Invert the S-R inputs.

10. When is a flip-flop said to be transparent?

a) when the Q output is opposite the input
b) when the Q output follows the input
c) when you can see through the IC packaging

11. Which of the following is correct for a D latch?

a) The output toggles if one of the inputs is held HIGH.
b) Q output follows the input D when the enable is HIGH.
c) Only one of the inputs can be HIGH at a time.

d) The output complement follows the input when enabled

stable while the:

a) clock is LOW
b) slave is transferring
c) flip-flop is reset
d) clock is HIGH

13. What does the triangle on the clock input of a J-K flip-flop mean?
a) level enabled
b) edge-triggered

14. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
________.
a) the clock pulse is LOW
b) the clock pulse is HIGH
c) the clock pulse transitions from LOW to HIGH
d) the clock pulse transitions from HIGH to LOW

15. What is the hold condition of a flip-flop?

a) both S and R inputs activated
b) no active S or R input
c) only S is active
d) only R is active

16. The circuit that is primarily responsible for certain flip-flops to be designated as
edgetriggered
is the:
a) edge-detection circuit.
b) NOR latch.
c) NAND latch.
d) pulse-steering circuit.

17. What is the significance of the J and K terminals on the J-K flip-flop?
a) There is no known significance in their designations.
b) The J represents "jump," which is how the Q output reacts whenever the clock
goes high and the J input is also HIGH.
c) The letters were chosen in honor of Jack Kilby, the inventory of the integrated
circuit.
d) All of the other letters of the alphabet are already in use.
18. Which of the following is not generally associated with flip-flops?
a) Hold time
b) Propagation delay time
c) Interval time
d) Set up time

19. What is one disadvantage of an S-R flip-flop?

a) It has no enable input.
b) It has an invalid state.
c) It has no clock input.
d) It has only a single output.

20. The output of a gated S-R flip-flop changes only if the:

a) flip-flop is set
b) control input data has changed
c) flip-flop is reset

d) input data has no change

21. An invalid condition in the operation of an active-HIGH input S-R latch occurs when
________.
a) HIGHs are applied simultaneously to both inputs S and R
b) LOWs are applied simultaneously to both inputs S and R
c) a LOW is applied to the S input while a HIGH is applied to the R input
d) a HIGH is applied to the S input while a LOW is applied to the R input

True/False
1. Flip-Flop outputs are always opposite or complementary.
2. Combinational circuit is having memory unit.
3. Flip flop is 1bit storage unit.
4. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because
input data is read during the entire time the clock pulse is at a LOW level.
5. Gated S-R flip-flops are called asynchronous because the output responds immediately
to input changes.
6. Asynchronous inputs will cause the flip-flop to respond immediately with regard to the
clock input.
7. For an S-R flip-flop to be set or reset, No change will occur in the output.
8. A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is
HIGH.
9. A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.
10. The term CLEAR always means that Q = 0, Q = 1.
11. PRESET and CLEAR inputs are normally synchronous.
12. The Q output of a flip-flop is normally HIGH when the device is in the "CLEAR" or
"RESET" state.
13. An input which can only be accepted when an enable or trigger is present is called
asynchronous.
14. Inputs that cause the output of a flip-flop to change instantaneously are asynchronous.
15. The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and
the clock transitions.
16. A D-type latch is able to change states and "follow" the D input regardless of the level of
the ENABLE input.
17. A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the
clock input.
18. A D latch has one data-input line.
19. Edge-triggered flip-flops can be identified by the triangle on the clock input.
20. The S-R flip-flop has no invalid or unused state.
21. Some flip-flops have invalid states.
22. Simple gate circuits, combinational logic, and transparent S-R flip-flops are
synchronous.
23. A flip-flop is in the CLEAR condition when Q = 1, Q = 0.
24. Pulse-triggered or level-triggered devices are the same.
25. A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.

26. It takes four flip-flops to act as a divide-by-4 frequency divider.

27. Flip-flops are wired together to form counters registers and memory devices.

Fill in the Blanks

1. _______ are the basic building blocks of combinational logic circuits.

2. _______ are the basic building blocks of sequential logic circuits.
3. The “D” in flip-flop stands for ________ or data.
4. f an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R
input goes to 0, the latch will be ________.
5. On a J-K flip-flop, when is the flip-flop in a hold condition J = _____ , K = ______.
6. If an input is activated by a signal transition, it is ________.
7. For an S-R flip-flop to be set or reset, the respective input must be ________.S
8. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the
output to ________.
9. In synchronous systems, the exact times at which any output can change state are
determined by a signal commonly called the ________.
10. When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are _____, ______.
11. A major drawback to an SR Flip Flop is its ________.
12. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the
inputs are ________.
13. The signal used to identify edge-triggered flip-flops is ________.
14. An edge-triggered flip-flop can change states only when ________.
15. When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output
will ________.
16. The term hold always means ________.
17. A gated S-R flip-flop goes into the CLEAR condition when _________________.
18. If an input is activated by a signal transition, it is ________.
19. A flip-flop operation is described as a toggle when the result after a clock is ________.
20. A positive edge-triggered flip-flop will accept inputs only when the clock ________.
21. The advantage of a J-K flip-flop over an S-R FF is that ________.
22. A S-R flip-flop is in the hold condition whenever ________.
23. The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.

Part B:

The minimum number of flip-flops needed to construct a BCD decade counter is

a) 4
b) 3
c) 10
d) 2
2. A shift counter comprising five flip-flops with an inverse feedback from the output of
MSB flip-flop to the input of the LSB flip-flop is a
a) Divide-by-32- counter
b) Divide-by-10- counter
c) Divide-by-5- counter
d) Five-bit shift counter
3. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1.
On the sixth clock pulse, the sequence is ________.
a) Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
b) Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0
c) Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
d) Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1
4. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out
shift register that is initially clear. What are the Q outputs after two clock pulses?
a) 0000
b) 0010
c) 1000
d) 1111
5. What is a shift register that will accept a parallel input, or a bidirectional serial load
and internal shift features, called?
a) tristate
b) end around
c) universal
d) conversion
6. On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3= 0.
On the fourth clock pulse, the sequence is ________.
a) Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
b) Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
c) Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
d) Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0
7. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is
HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three
clock pulses, the shift register is storing ________.
a) 1101
b) 0111
c) 0001
d) 1110
8. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF.
b) Use the Q output of the last FF.

d) Use the Q output of each FF.

9. What is meant by parallel load of a shift register?
a) All FFs are preset with data.
b) Each FF is loaded with data, one at a time.
10. How many flip-flops are required to make a MOD-32 binary counter?
a) 3
b) 45
c) 5
d) 6
11. Using four cascaded counters with a total of 16 bits, how many states must be deleted
to achieve a modulus of 50,000?
a) 50,000
b) 65,536
c) 25,536
d) 15,536
12. The terminal count of a modulus-11 binary counter is ________.
a) 1010
b) 1000
c) 1001
d) 1100
13. Synchronous counters eliminate the delay problems encountered with asynchronous
counters because the:
a) input clock pulses are applied only to the first and last stages
b) input clock pulses are applied only to the last stage
c) input clock pulses are not used to activate any of the counter stages
d) input clock pulses are applied simultaneously to each stage
14. What is the difference between combinational logic and sequential logic?
a) Combinational circuits are not triggered by timing pulses, sequential circuits are
triggered by timing pulses.
b) Combinational and sequential circuits are both triggered by timing pulses.
c) Neither circuit is triggered by timing pulses.
15. A BCD counter is a ________.
a) Binary counter.
b) Full-modulus counter.
c) Decade counter.
d) Divide-by-10 counter.
16. A five bit counter
a) Has a modulus of 5.
b) Has a modulus of 2.
c) Has modulus that is less than or equal to 32.
d) Cant not have a modulus that is greater than 32.
e) Both c and d are true.
17. All BCD counters
a) Are decade counters because all decades counters are BCD counters.
b) Are not decade’s counters.
c) Have a modulus of 10.
d) Are constructed with only presettable D flip-flops.

18. A counter that has a modulus of 64 should use minimum of

a) 6 flip-flops

b) 6 J-K type flip-flops

c) 6 D flip-flops
d) 64 flip-flops
19. A MOD-32 binary synchronous counter would require
a) 6 flip-flops and 3 AND gates
b) 5 flip-flops
c) 5 flip-flops and 3 AND gates
d) None of these
20. In what type of shift register do we have access to only the leftmost and rightmost flipflops?
a) Serial-in serial-out shift register
b) Serial-in parallel-out shift register
c) Parallel-in serial-out shift register
d) Parallel-in Parallel-out shift register