1.

Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input
clock frequency of 20.48 MHz.

A. 10.24 kHz

B. 5 kHz

C. 30.24 kHz

D. 15 kHz

2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

A. The logic level at the D input is transferred to Q on NGT of CLK.

B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.

C. The Q output is ALWAYS identical to the D input when CLK = PGT.

D. The Q output is ALWAYS identical to the D input.

3. Propagation delay time, tPLH, is measured from the ________.

A. triggering edge of the clock pulse to the LOW-to-HIGH transition of the output

B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output

C. preset input to the LOW-to-HIGH transition of the output

D. clear input to the HIGH-to-LOW transition of the output

4. How is a J-K flip-flop made to toggle?

A. J = 0, K = 0

B. J = 1, K = 0

C. J = 0, K = 1

D. J = 1, K = 1

5. How many flip-flops are in the 7475 IC?

A. 1

B. 2

C. 4

D. 8
6. How many flip-flops are required to produce a divide-by-128 device?

A. 1

B. 4

C. 6

D. 7

7. Which is not an Altera primitive port identifier?

A. clk

B. ena

C. clr

D. prn

8. The timing network that sets the output frequency of a 555 astable circuit contains ________.
A. three external resistors are used
B. two external resistors and an external capacitor are used
C. an external resistor and two external capacitors are used
D. no external resistor or capacitor is required

9. What is the difference between the enable input of the 7475 and the clock input of the 7474?
A. The 7475 is edge-triggered.
B. The 7474 is edge-triggered.

10. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called
________.

A
parity error checking
.
B. ones catching
C. digital discrimination
D
digital filtering
.

11. What is another name for a one-shot?

A. Monostable
B. Multivibrator
C. Bistable
D. Astable

12. On a master-slave flip-flop, when is the master enabled?

A when the gate is LOW

 .
B. when the gate is HIGH
C. both of the above
D
neither of the above
.

13. One example of the use of an S-R flip-flop is as a(n):

A
racer
.
B. astable oscillator
C
binary storage register
.
D
transition pulse generator
.

14. What is the difference between the 7476 and the 74LS76?

A. the 7476 is master-slave, the 74LS76 is master-slave

B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
C. the 7476 is edge-triggered, the 74LS76 is master-slave
D. the 7476 is master-slave, the 74LS76 is edge-triggered

15. Which of the following is correct for a gated D flip-flop?

A
The output toggles if one of the inputs is held HIGH.
.
B. Only one of the inputs can be HIGH at a time.
C. The output complement follows the input when enabled.
D
Q output follows the input D when the enable is HIGH
.

16. With regard to a D latch, ________.

A
the Q output follows the D input when EN is LOW
.
B. the Q output is opposite the D input when EN is LOW
C
the Q output follows the D input when EN is HIGH
.
D
the Q output is HIGH regardless of EN's input state
.

17. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

A
It can't be done.
.
B. Invert the Q outputs.
C
Invert the S-R inputs.
.
18. When is a flip-flop said to be transparent?

A
when the Q output is opposite the input
.
B. when the Q output follows the input
C. when you can see through the IC packaging

19. Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below.
Determine if the circuit is functioning properly, and if not, what might be wrong.

A
The circuit is functioning properly.
.
B. Q2 is incorrect; the flip-flop is probably bad.
C. The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
D
A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.
.

20. A 555 operating as a monostable multivibrator has an R1 of 1 M . Determine C1 for a pulse width of 2 s.

A
1.8 F
.
B. 18 F
C. 18 pF
D 18 nF
 .

21. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read
during the entire time the clock pulse is at a LOW level.
A. True
B. False

22. Which of the following is correct for a D latch?

A
The output toggles if one of the inputs is held HIGH.
.
B. Q output follows the input D when the enable is HIGH.
C. Only one of the inputs can be HIGH at a time.
D
The output complement follows the input when enabled.
.

23. A J-K flip-flop is in a "no change" condition when ________.

A
J = 1, K = 1
.
B. J = 1, K = 0
C. J = 0, K = 1
D
J = 0, K = 0
.

24. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

A
clock is LOW
.
B. slave is transferring
C. flip-flop is reset
D
clock is HIGH
.

25. Which of the following describes the operation of a positive edge-triggered D flip-flop?

A
If both inputs are HIGH, the output will toggle.
.
B. The output will follow the input on the leading edge of the clock.
C. When both inputs are LOW, an invalid state exists.
D The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the
. trailing edge of the clock.

26. What does the triangle on the clock input of a J-K flip-flop mean?

A
level enabled
.
B. edge-triggered

27. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
 A
constantly LOW
.
B. constantly HIGH
C. a 20 kHz square wave
D
a 10 kHz square wave
.

28. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________
state(s) at the ________.

A
opposite, active clock edge
.
B. inverted, positive clock edge
C. quiescent, negative clock edge
D
reset, synchronous clock edge
.

29. An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of 0.2 F. The
pulse width (tW) is approximately ________.

A
6.9 s
.
B. 6.9 ms
C. 69 ms
D
690 ms
.

30. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.

A
the clock pulse is LOW
.
B. the clock pulse is HIGH
C
the clock pulse transitions from LOW to HIGH
.
D
the clock pulse transitions from HIGH to LOW
.

31. What is the hold condition of a flip-flop?

A
both S and R inputs activated
.
B. no active S or R input
C. only S is active
D
only R is active
.

32. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the
latch will be ________.
A. SET
B. RESET
C. Clear
 D. Invalid

33. In VHDL, how many inputs will a primitive JK flip-flop have?

A. 2
B. 3
C. 4
D. 5

34. A 555 operating as a monostable multivibrator has a C1 = 0.01 F. Determine R1 for a pulse width of 2 ms.

A
200 k
.
B. 182 k
C. 91 k
D
182
.

35. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause
it to change states?

A
CLK = NGT, D = 0
.
B. CLK = PGT, D = 0
C. CLOCK NGT, D = 1
D
CLOCK PGT, D = 1
.
E. CLK = NGT, D = 0, CLOCK NGT, D = 1

36. The symbols on this flip-flop device indicate ________.

A
triggering takes place on the negative-going edge of the CLK pulse
.
B. triggering takes place on the positive-going edge of the CLK pulse
C. triggering can take place anytime during the HIGH level of the CLK waveform
D
triggering can take place anytime during the LOW level of the CLK waveform
.

37. In a 555 timer, three 5 k resistors provide a trigger level of ________.

A
1/4 VCC and a threshold level 1/2 VCC
.
B. 1/3 VCC and a threshold level 3/4 VCC
C
1/3 VCC and a threshold level 2/3 VCC
.
D 1/4 VCC and a threshold level 2/3 VCC
 .

38. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
A. Active-HIGH
B. Active-LOW

39. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:

A
edge-detection circuit.
.
B. NOR latch.
C. NAND latch.
D
pulse-steering circuit.
.

40. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a
count of how many input clock pulses?
A. 16
B. 8
C. 4
D. 2

41. What is the significance of the J and K terminals on the J-K flip-flop?

A
There is no known significance in their designations.
.
The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is
B.
also HIGH.
C
The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
.
D
All of the other letters of the alphabet are already in use.
.

42. Why are the S and R inputs of a gated flip-flop said to be synchronous?

A
They must occur with the gate.
.
B.They occur independent of the gate.

43. Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
A. True
B. False

44. Which of the following is not generally associated with flip-flops?

A
Hold time
.
B. Propagation delay time
C
Interval time
.
D
Set up time
.
45. An RC circuit used in a 74122 retriggerable one-shot has an REXT of 100 k and a CEXT of 0.005 F. The
pulse width is ________.

A
70 s
.
B. 16 s
C
160 s
.
D
32 s
.

46. Edge-triggered flip-flops must have:

A
very fast response times
.
B. at least two inputs to handle rising and falling edges
C
positive edge-detection circuits
.
D
negative edge-detection circuits
.

47. A 555 operating as a monostable multivibrator has an R1 of 220 k . Determine C1 for a pulse width of 4
ms.

A
0.017 F
.
B. 17 pF
C. 170 pF
D
1,700 F
.

48. What is one disadvantage of an S-R flip-flop?

A
It has no enable input.
.
B. It has an invalid state.
C. It has no clock input.
D
It has only a single output.
.

49. To completely load and then unload an 8-bit register requires how many clock pulses?
A. 2
B. 4
C. 8
D. 16

50. What is one disadvantage of an S-R flip-flop?

A It has no enable input.

 .
B. It has an invalid state.
C. It has no clock input.
D
It has only a single output.
.

51. Which of the following best describes the action of pulse-triggered FF's?

A
The clock and the S-R inputs must be pulse shaped.
.
The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the
B.
clock.
C.A pulse on the clock transfers data from input to output.
D
The synchronous inputs must be pulsed.
.

52. An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.

A
HIGHs are applied simultaneously to both inputs S and R
.
B. LOWs are applied simultaneously to both inputs S and R
C. a LOW is applied to the S input while a HIGH is applied to the R input
D
a HIGH is applied to the S input while a LOW is applied to the R input
.

53. On a J-K flip-flop, when is the flip-flop in a hold condition?

A
J = 0, K = 0
.
B. J = 1, K = 0
C. J = 0, K = 1
D
J = 1, K = 1
.

54. The output pulse width for a 555 monostable circuit with R1 = 3.3 k and C1 = 0.02 F is ________.

A
7.3 s
.
B. 73 s
C. 7.3 ms
D
73 ms
.

55. Edge-triggered flip-flops must have:

A
very fast response times.
.
B. at least two inputs to handle rising and falling edges.
C
a pulse transition detector.
.
 D
active-LOW inputs and complemented outputs.
.

56. As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:

A. very long.
B. very short.
C. at a maximum value to enable the input control signals to stabilize.
D. of no consequence as long as the levels are within the determinate range of value.

57. A positive edge-triggered D flip-flop will store a 1 when ________.

A
the D input is HIGH and the clock transitions from HIGH to LOW
.
the D input is HIGH and the clock transitions from LOW to
B.
HIGH
C. the D input is HIGH and the clock is LOW
D
the D input is HIGH and the clock is HIGH
.

58. If an input is activated by a signal transition, it is ________.

A
edge-triggered
.
B. toggle triggered
C. clock triggered
D
noise triggered
.

59. A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is
operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What
causes the glitches, and how might the problem be corrected?

A The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being
. used.
The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of
B.
the terminals to correct the problem.
A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a
C.
NAND gate.
D A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace
. the flip-flop with a negative edge-triggered J-K Flip-Flop.

60. A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse width of 500
ms.

A
45
.
B. 455
C
4.5 k
.
D
455
.
61. Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.
A. True
B. False

62. Which is not a real advantage of HDL?

A
Using higher levels of abstraction
.
B.Tailoring components to exactly fit the needs of the project
C
The use of graphical tools
.
D
Using higher levels of abstraction and tailoring components to exactly fit the needs of the project
.

63. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input
clock pulses, the binary count is ________.
A. 00
B. 11
C. 01
D. 10

64. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which
configuration feature?

A
cross coupling
.
B. gate impedance
C. low input voltages
D
asynchronous operation
.

65. In VHDL, how is each instance of a component addressed?

A A name followed by a colon and the name of the library

. primitive
B. A name followed by a semicolon and the component type
C. A name followed by the library being used
D
A name followed by the component library number
.

66. The output of a gated S-R flip-flop changes only if the:

A
flip-flop is set
.
B. control input data has changed
C. flip-flop is reset
D
input data has no change
.

67. In VHDL, in which declaration section is a COMPONENT declared?

 A
Architecture
.
B. Library
C. Entity
D
Port map
.

68. A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what
could be causing the problem?

A
. The output is always low; the circuit is defective.
B. The Q output should be the complement of the output; the S and R terminals are reversed.
C. The Q should be following the R input; the R input is defective.
D
There is nothing wrong with the circuit.
.

69. The output pulse width of a 555 monostable circuit with R1 = 4.7 k and C1 = 47 F is ________.

A
24 s
.
B. 24 ms
C
243 ms
.
D
243 s
.

70. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

A
An invalid state will exist.
.
B. No change will occur in the output.
C. The output will toggle.
D
The output will reset.
.

71. The circuit given below fails to function; the inputs are checked with a logic probe and the following
indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are
LOW. What could be causing the problem?
 A
There is no problem.
.
B. The clock should be held HIGH.
C
The PRE is stuck LOW.
.
D
The CLR is stuck HIGH
.

72. A push-button switch is used to input data to a register. The output of the register is erratic. What could be
causing the problem?

A
The power supply is probably noisy.
.
B. The switch contacts are bouncing.
C. The socket contacts on the register IC are corroded.
D
The register IC is intermittent and failure is imminent.
.

73. A 555 timer is connected for astable operation as shown below along with the output waveform. It is
determined that the duty cycle should be 0.5. What steps need to be taken to correct the duty cycle, while
maintaining the same output frequency?
 A
Increase the value of C.
.
B. Increase Vcc and decrease RL.
C. Decrease R1 and R2.
D
Decrease R1 and increase R2.
.

74. The pulse width of a one-shot circuit is determined by ________.

A
a resistor and capacitor
.
B. two resistors
C. two capacitors
D
none of the above
.

75. For an S-R flip-flop to be set or reset, the respective input must be:

A
installed with steering diodes
.
B. in parallel with a limiting resistor
C. LOW
D
HIGH
.
76. An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?

A
.
B
.
C
.
D
.

77. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?

A
No change will occur in the output.
.
B. An invalid state will exist.
C. The output will toggle.
D
The output will reset.
.

78. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-
flop is 32 kHz, the output frequency (fout) is ________.

A
1 kHz
.
B. 2 kHz
C. 4 kHz
D
16 kHz
.