TN 423: Vlsi Circuits: Lecture 4a

TN 423: VLSI CIRCUITS
Lecture 4a
FABRICATION OF CMOS ICs
1
Outline
1. Introduction
2. Material growth and Depositions
3. Fabrication processes
4. NMOS Transistor fabrication
2
Introduction…
Ω The process of building devices in a single
piece of Si crystal involves building successive
layers of insulating, conducting and
semiconducting materials
Ω Each layer is patterned to give a distinct
function and relationship with the surrounding
areas and subsequent layers
Ω Building a succession of layers needs careful
consideration of each layer’s relative position
3
Introduction
MOS STRUCTURE
❖MOS consisting of three
layers
1. The top layer is a conductive
metal electrode (gate)
2. the middle layer is an
insulator of glass or silicon
dioxide (insulator-SiO2)
3. the bottom layer is another
conductive electrode made
out of crystal silicon (Si)
•. 4
Introduction…
Ω MOS devices can be Depletion type or
Enhancement type
✓ There are processes for both types
Ω MOS devices can be either p-channel or n-
channel
✓ So we have PMOS and NMOS processes
respectively
5
Material Growth and Depositions
Ω Silicon Dioxide (SiO2)
 An excellent electrical insulator
 It can be grown on a silicon wafer or deposited on
top of the wafer
 Thermal oxidation
 Chemical vapor deposition (CVD) oxidation
Ω Silicon Nitride (Si3N4)
 Nitrides act as strong barriers to most atoms,
 ideal for use as an overglass layer
Ω Polycrystal Silicon
 Called polysilicon or just poly for short
 used as the gate material in MOSFETs
 It adheres well to silicon dioxide
6
Metal Depositions
Ω Aluminum (Al)
Ω Al is the most common metal used for
✓ interconnect wiring in ICs
✓ It is prone to electromigration
✓ Layout engineers cannot alter the thickness t of the
layer
✓ Electromigration is thus controlled by specifying the
minimum width w to keep J below a max. value
7
Electromigration
the shortcoming of Aluminium
Ω Undesired movement
Ω When the current density is high enough,
there can be a momentum transfer from
moving electrons to metal Ions that make
up the lattice of interconnect material.
Ω Ions drift in the direction of electron flow
Ω Result in gradual displacement of metal
atoms in a semiconductor, causing open
or short circuits.
8
Ω Copper (Cu)
✓ Cu has recently been introduced as a replacement
to aluminum
✓ Its resistivity is about one-half the value of Al
✓ Standard patterning techniques cannot be used on
copper layers; specialized techniques had to be
developed
9
Fabrication Processes
Ω Oxidation: Addition of the layer of oxide on the
substrate
Ω Deposition: Materials such as metals,
insulators, or semiconductors are added in thin
layers (like painting) onto the wafer
Ω Implantation: Atoms or molecules are added to
the silicon wafer, changing its electronic
properties
Ω Etching: Material is removed from the wafer
through chemical reactions or mechanical
motion
10
Lithography
ΩWhen building a multi-component IC, we need to perform
different modifications to different areas of the wafer.
ΩWe may want to etch some areas and add metal to
others, for example.
ΩThe method by which we define which areas will be
modified is known as lithography.
ΩPhotolithography (optical lithography or UV
lithography) is a process used in microfabrication to
pattern parts of a thin film or the bulk of a substrate.
ΩIt uses light to transfer a geometric pattern from a
photomask to a light-sensitive chemical "photoresist", or
simply "resist," on the substrate.
11
MOS Devices Fabrication…
1.Starting with an n-substrate will construct n-
channel devices by creating p-regions known as
wells or tubs for fabricating n-channel devices
✓ This is called p-well process
2.Starting with a p-substrate, n-wells will be
created for fabricating p-channel devices
✓ This is called n-well process
3.Starting with a neutral substrate, both n and p
wells will be created
✓ This is called twin-tub process
12
Ω p-well process
13
Ω n-well process
14
Ω twin-tub process
15
NMOS Transistor Fabrication
Ω The simplest IC fabrication technology is
the NMOS technology
Ω The process sequence for this technology
requires least number of lithography
levels
Ω Fundamental aspects of this technology
are used for the development of CMOS
Technology
16
NMOS Transistor Fabrication
n-well Process
Ω The starting Si wafer is a lightly doped p-
type substrate
Ω n-well device will be fabricated
17
NMOS Transistor Fabrication…
Ω The fabrication process follows the steps:
Step 1: p-substrate
Ω Processing is carried on single crystal silicon (p-
substrate) of high purity on which required P
impurities are introduced as crystal is grown.
18
Step 2 : Oxidation
ΩA thick layer of silicon dioxide (SiO2) (typically 1
micrometer) is grown all over the surface of the wafer
by thermal oxidation.
ΩIt protects the surface, acts as a barrier to
the dopant during processing, and provide a
generally insulating substrate on to which other layers
may be deposited and patterned.
19
Step 3: photoresist
ΩThe surface is now covered with the photo
resist which is deposited onto the wafer and spun
to an even distribution of the required thickness.
ΩThis photoresist is light sensitive, acid-resistant,
insoluble in the developing solution
20
Step 4: UV light Exposure
ΩThe photo resist layer is then exposed to UV light
ΩThe UV light passes through a glass mask which defines
those regions into which diffusion is to take place together
with transistor channels.
ΩAreas exposed to UV radiations are polymerized
(hardened), but the areas required for diffusion are
shielded by the mask and remain unaffected.
Ngeze, LV VLSI Circuits 21

Step 5: Etching to remove photoresist
Ω Photoresist is removed by using a solvent in
etching process
22
Step 6 Etching to remove SiO2
Ω SiO2 is removed by etching with HF
23
Step7 Etching to remove other photoresist
Ω Remaining photoresist removed with
another etchant
24
Step 8: Deposition of SiO2
ΩA thin layer of SiO2 (0.1 micro m typical) is grown over the
entire chip surface
25
Step9: Deposition of PolySilicon layer
Ω On top of the thin oxide, a layer of polysilicon is
deposited to form the gate structure
Ω This also acts as an interconnect medium in ICs
26
Step10: Etching of Polysilicon layer
Ω The polysilicon layer is patterned and
etched to form interconnects of the gate
27
Step11 Doping of Silicon
Ω Si is doped with donors to create n+
regions
28
Step12: Thick oxidation
ΩThick oxide (SiO2) is grown over all again and is
then masked with photoresist and etched to expose
selected areas of the poly silicon gate, drain and
source areas where connections are to be made.
(contacts cut)
29
Step 13 Opening of the Source and Drain
regions
ΩSource/Drain regions opened
30
Step14 Metal Deposition
ΩAluminum evaporated to cover surface
31
Step 14 Metal Etching
ΩAluminum etched to form metal interconnects
32
Ω NMOS Transistor structure
Source Gate Drain

Polysilicon
SiO2
n+ n+
Body
p bulk Si
33
Ω Gate – oxide – body stack looks like a capacitor
✓ Gate and body are conductors
✓ SiO2 (oxide) is a very good insulator
Ω Called metal – oxide – semiconductor (MOS)
capacitor
Source Gate Drain
Polysilicon
SiO2
n+ n+
Body
p bulk Si
34
PMOS Transistor Fabrication
2. p-well Process
ΩThe starting Si wafer is a lightly doped n-
type substrate
Ωp-well device will be fabricated
ACTIVITY: Summarize the following

1.nMOS and pMOS
2.p-well process
3.Twin-tub process
35
End of Lecture 4
36

TN 423: Vlsi Circuits: Lecture 4a

Uploaded by

Copyright:

Available Formats

TN 423: Vlsi Circuits: Lecture 4a

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

TN 423: Vlsi Circuits: Lecture 4a

Uploaded by

Copyright:

Available Formats

TN 423: VLSI CIRCUITS

FABRICATION OF CMOS ICs

Ngeze, LV VLSI Circuits 21

Source Gate Drain

ACTIVITY: Summarize the following

You might also like