Four-Phase Buck PWM Controller With Integrated MOSFET Drivers For Intel VR10, VR11, and AMD Applications

DATASHEET
ISL6312 FN9289
Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10, Rev 6.00
VR11, and AMD Applications February 1, 2011
The ISL6312 four-phase PWM control IC provides a Features

precision voltage regulation system for advanced
microprocessors. The integration of power MOSFET drivers • Integrated Multiphase Power Conversion
into the controller IC marks a departure from the separate - 2- or 3-Phase Operation with Internal Drivers
PWM controller and driver configuration of previous - 4-Phase Operation with External PWM Driver Signal
multiphase product families. By reducing the number of • Precision Core Voltage Regulation
external parts, this integration is optimized for a cost and - Differential Remote Voltage Sensing
space saving power management solution. - 0.5% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
One outstanding feature of this controller IC is its • Optimal Transient Response
multi-processor compatibility, allowing it to work with both Intel - Active Pulse Positioning (APP) Modulation
and AMD microprocessors. Included are programmable VID - Adaptive Phase Alignment (APA)
codes for Intel VR10, VR11, as well as AMD DAC tables. A • Fully Differential, Continuous DCR Current Sensing
unity gain, differential amplifier is provided for remote voltage - Accurate Load Line Programming
sensing, compensating for any potential difference between - Precision Channel Current Balancing
remote and local grounds. The output voltage can also be • User Selectable Adaptive Dead Time Scheme
positively or negatively offset through the use of a single
- PHASE Detect or LGATE Detect for Application Flexibility
external resistor.
• Variable Gate Drive Bias: 5V to 12V
The ISL6312 also includes advanced control loop features • Multi-Processor Compatible
for optimal transient response to load apply and removal. - Intel VR10 and VR11 Modes of Operation
One of these features is highly accurate, fully differential, - AMD Mode of Operation
continuous DCR current sensing for load line programming • Microprocessor Voltage Identification Inputs
and channel current balance. Active Pulse Positioning (APP) - 8-bit DAC
modulation is another unique feature, allowing for quicker - Selectable between Intel’s Extended VR10, VR11, AMD
initial response to high di/dt load transients. 5-bit, and AMD 6-bit DAC Tables
- Dynamic VID Technology
This controller also allows the user the flexibility to choose
• Overcurrent Protection
between PHASE detect or LGATE detect adaptive dead time
schemes. This ability allows the ISL6312 to be used in a • Multi-Tiered Overvoltage Protection
multitude of applications where either scheme is required. • Digital Soft-Start
• Selectable Operation Frequency up to 1.5MHz Per Phase
Protection features of this controller IC include a set of
• Pb-Free (RoHS Compliant)
sophisticated overvoltage, undervoltage, and overcurrent
protection. Furthermore, the ISL6312 includes protection Ordering Information
against an open circuit on the remote sensing inputs.
PART NUMBER PART TEMP. PACKAGE PKG.
Combined, these features provide advanced protection for the
(Note 1) MARKING (°C) (Pb-Free) DWG. #
microprocessor and power system.
ISL6312CRZ ISL6312 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6312CRZ-T ISL6312 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
(Note 2)
ISL6312CRZ-TK ISL6312 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
(Note 2)
ISL6312IRZ ISL6312 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
ISL6312IRZ-T ISL6312 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
(Note 2)
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. Please refer to TB347 for details on reel specifications.
FN9289 Rev 6.00 Page 1 of 35

February 1, 2011
ISL6312
Pinout
ISL6312
(48 LD QFN)
TOP VIEW
PHASE3
UGATE3
LGATE3
PGOOD
ISEN3+
BOOT3
PVCC3
ISEN3-
VID5
VID6
VID7
FS
48 47 46 45 44 43 42 41 40 39 38 37
VID4 1 36 EN
VID3 2 35 ISEN1+
VID2 3 34 ISEN1-
VID1 4 33 PHASE1
VID0 5 32 UGATE1
VRSEL 6 49 31 BOOT1
GND
DRSEL 7 30 LGATE1
OVPSEL 8 29 PVCC1_2
SS 9 28 LGATE2
VCC 10 27 BOOT2
REF 11 26 UGATE2
OFS 12 25 PHASE2
13 14 15 16 17 18 19 20 21 22 23 24
EN_PH4
PWM4
RGND
ISEN4+
ISEN4-
IDROOP
ISEN2+
ISEN2-
COMP
VDIFF
VSEN
FB
ISL6312 Integrated Driver Block Diagram
PVCC
DRSEL
BOOT
UGATE
20k
PWM
GATE SHOOT-
CONTROL THROUGH PHASE
LOGIC PROTECTION
SOFT-START
AND 10k
FAULT LOGIC
LGATE
FN9289 Rev 6.00 Page 2 of 35

February 1, 2011
ISL6312
Block Diagram
PGOOD SS EN
OPEN SENSE
LINE PREVENTION
0.85V
VSEN
x1 VCC
RGND POWER-ON
RESET
VDIFF SOFT-START PVCC1_2
AND
UNDERVOLTAGE FAULT LOGIC
DETECTION
LOGIC BOOT1
UGATE1
MOSFET
OVERVOLTAGE DRIVER
DETECTION PHASE1
LOGIC
0.2V
LGATE1
LOAD APPLY
OVPSEL TRANSIENT
ENHANCEMENT
DRSEL
CLOCK AND
MODULATOR FS
WAVEFORM
GENERATOR
VRSEL MODE/DAC
SELECT BOOT2
UGATE2
PWM1 MOSFET
DRIVER
VID7
 PHASE2
VID6
LGATE2
VID5 OC PWM2
VID4 DYNAMIC
VID3
VID
D/A

VID2 I_TRIP
PWM3
VID1 PH4 POR/
EN_PH4

DETECT
VID0 CHANNEL
DETECT
PVCC3
REF PWM4
E/A
FB 
BOOT3
COMP
UGATE3
MOSFET
DRIVER
OFS OFFSET CHANNEL I_AVG PHASE3
1
CURRENT
BALANCE N
LGATE3
I_AVG
IDROOP

PWM4
SIGNAL PWM4
LOGIC
CH1 CH2 CH3 CH4

CURRENT CURRENT CURRENT CURRENT
SENSE SENSE SENSE SENSE
ISEN1- ISEN1+ ISEN2- ISEN2+ ISEN3- ISEN3+ ISEN4- ISEN4+ GND
FN9289 Rev 6.00 Page 3 of 35

February 1, 2011
ISL6312
Typical Application - ISL6312 (4-Phase)
+12V
FB IDROOP VDIFF
COMP
VSEN BOOT1
RGND
UGATE1
+5V
VCC PHASE1
LGATE1
OFS ISEN1-
ISEN1+
FS
+12V
REF
PVCC1_2
BOOT2
SS
UGATE2
PHASE2
LGATE2 LOAD
OVPSEL
ISEN2-
ISL6312 ISEN2+
+12V
VID7
VID6 PVCC3
VID5
VID4
VID3 BOOT3
VID2
UGATE3
VID1
VID0
PHASE3
VRSEL
PGOOD LGATE3
+12V
ISEN3-
ISEN3+
+12V
+12V
EN
BOOT
VCC UGATE
EN_PH4
PVCC
DRSEL PHASE
ISL6612
LGATE
PWM4 PWM
GND
GND
ISEN4-
ISEN4+
FN9289 Rev 6.00 Page 4 of 35

February 1, 2011
ISL6312
Typical Application - ISL6312 with NTC Thermal Compensation (4-Phase)
+12V
FB IDROOP VDIFF
COMP
VSEN BOOT1 PLACE IN

NTC CLOSE
RGND
UGATE1 PROXIMITY
+5V
PHASE1
VCC
LGATE1
OFS ISEN1-
ISEN1+
FS
+12V
REF
PVCC1_2
BOOT2
SS
UGATE2
PHASE2
LGATE2 LOAD
OVPSEL
ISEN2-
ISL6312 ISEN2+
VID7 +12V
VID6 PVCC3
VID5
VID4
VID3 BOOT3
VID2
UGATE3
VID1
VID0
PHASE3
VRSEL
PGOOD LGATE3
+12V
ISEN3-
ISEN3+
+12V
+12V
EN
BOOT
EN_PH4 VCC UGATE
PVCC
PHASE
DRSEL
ISL6612
LGATE
PWM4 PWM GND
GND
ISEN4-
ISEN4+
FN9289 Rev 6.00 Page 5 of 35

February 1, 2011
ISL6312
Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Thermal Resistance JA (°C/W) JC (°C/W)
Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V QFN Package (Notes 3, 4) . . . . . . . . . . 32 3.5
BOOT Voltage, VBOOT . . . . . . . . . . . . . . GND - 0.3V to GND + 36V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
BOOT to PHASE Voltage, VBOOT-PHASE . . . . . . -0.3V to 15V (DC) Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
-0.3V to 16V (<10ns, 10µJ) Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
PHASE Voltage, VPHASE . . . . . . . GND - 0.3V to 15V (PVCC = 12) http://www.intersil.com/pbfree/Pb-FreeReflow.asp
GND - 8V (<400ns, 20µJ) to 24V (<200ns, VBOOT - PHASE = 12V)
UGATE Voltage, VUGATE. . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V
Recommended Operating Conditions
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE Voltage, VLGATE . . . . . . . . . . . GND - 0.3V to PVCC + 0.3V VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V Ambient Temperature (ISL6312CRZ) . . . . . . . . . . . . . 0°C to +70°C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD Ambient Temperature (ISL6312IRZ) . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.
MIN MAX
PARAMETER TEST CONDITIONS (Note 6) TYP (Note 6) UNITS
BIAS SUPPLIES
Input Bias Supply Current IVCC; EN = high 15 20 25 mA
Gate Drive Bias Current - PVCC1_2 Pin IPVCC1_2; EN = high 2 4.3 6 mA
Gate Drive Bias Current - PVCC3 Pin IPVCC3; EN = high 1 2.1 3 mA

VCC POR (Power-On Reset) Threshold VCC rising 4.25 4.38 4.50 V
VCC falling 3.75 3.88 4.00 V
PVCC POR (Power-On Reset) Threshold PVCC rising 4.25 4.38 4.50 V
PVCC falling 3.60 3.88 4.00 V
PWM MODULATOR
Oscillator Frequency Accuracy, fSW RT = 100k (± 0.1%) 225 250 275 kHz
Adjustment Range of Switching Frequency (Note 5) 0.08 - 1.0 MHz
Oscillator Ramp Amplitude, VPP (Note 5) - 1.50 - V
CONTROL THRESHOLDS
EN Rising Threshold - 0.85 - V
EN Hysteresis - 110 - mV
EN_PH4 Rising Threshold 1.160 1.210 1.250 V

EN_PH4 Falling Threshold 1.00 1.06 1.10 V
COMP Shutdown Threshold COMP falling 0.1 0.2 0.3 V
REFERENCE AND DAC
System Accuracy (1.000V - 1.600V) -0.5 - 0.5 %

DAC Input Low Voltage (VR10, VR11) - - 0.4 V
DAC Input High Voltage (VR10, VR11) 0.8 - - V
FN9289 Rev 6.00 Page 6 of 35

February 1, 2011
ISL6312
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)
MIN MAX
DAC Input Low Voltage (AMD) - - 0.6 V
DAC Input High Voltage (AMD) 1.0 - - V
PIN-ADJUSTABLE OFFSET
OFS Sink Current Accuracy (Negative Offset) ROFS = 10kfrom OFS to GND 37.0 40.0 43.0 A
OFS Source Current Accuracy (Positive Offset) ROFS = 30kfrom OFS to VCC 50.5 53.5 56.5 A
ERROR AMPLIFIER
DC Gain RL = 10k to ground, (Note 5) - 96 - dB
Gain-Bandwidth Product CL = 100pF, RL = 10k to ground, (Note 5) - 20 - MHz
Slew Rate CL = 100pF, Load = ±400mA, (Note 5) - 8 - V/s
Maximum Output Voltage Load = 1mA 3.90 4.20 - V

Minimum Output Voltage Load = -1mA - 1.30 1.5 V
SOFT-START RAMP
Soft-Start Ramp Rate VR10/VR11, RS = 100k - 1.563 - mV/µs

AMD 2.063 mV/µs
Adjustment Range of Soft-Start Ramp Rate (Note 5) 0.625 - 6.25 mV/µs
PWM OUTPUT
PWM Output Voltage LOW Threshold Iload = ±500µA - - 0.5 V

PWM Output Voltage HIGH Threshold Iload = ±500µA 4.5 - - V
CURRENT SENSING
Current Sense Resistance, RISEN T = +25°C 297 300 303 

Sensed Current Tolerance ISEN1+ = ISEN2+ = ISEN3+ = ISEN4+ = 80A 76 80 84 A
OVERCURRENT PROTECTION
Overcurrent Trip Level - Average Channel Normal operation 110 125 140 A
Dynamic VID change 143 163 183 A
Overcurrent Trip Level - Individual Channel Normal operation 150 177 204 A
Dynamic VID change (Note NOTES:) 209.4 238 266.6 A
PROTECTION
Undervoltage Threshold VSEN falling 55 60 65 %VID
Undervoltage Hysteresis VSEN rising - 10 - %VID

Overvoltage Threshold During Soft-Start VR10/VR11 1.24 1.28 1.32 V
AMD 2.13 2.20 2.27 V
Overvoltage Threshold (Default) VR10/VR11, OVPSEL tied to ground, VSEN rising VDAC + VDAC + VDAC + V
150mV 175mV 200mV
AMD, OVPSEL tied to ground, VSEN rising VDAC + VDAC + VDAC + V

225mV 250mV 275mV
Overvoltage Threshold (Alternate) OVPSEL tied to +5V, VSEN rising VDAC + VDAC + VDAC + V
325mV 350mV 375mV
Overvoltage Hysteresis VSEN falling - 100 - mV
SWITCHING TIME (Note 5)
UGATE Rise Time tRUGATE; VPVCC = 12V, 3nF load, 10% to 90% - 26 - ns
FN9289 Rev 6.00 Page 7 of 35

February 1, 2011
ISL6312
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)
MIN MAX
LGATE Rise Time tRLGATE; VPVCC = 12V, 3nF load, 10% to 90% - 18 - ns
UGATE Fall Time tFUGATE; VPVCC = 12V, 3nF load, 90% to 10% - 18 - ns
LGATE Fall Time tFLGATE; VPVCC = 12V, 3nF load, 90% to 10% - 12 - ns
UGATE Turn-On Non-Overlap tPDHUGATE; VPVCC = 12V, 3nF load, adaptive - 10 - ns
LGATE Turn-On Non-Overlap tPDHLGATE; VPVCC = 12V, 3nF load, adaptive - 10 - ns
GATE DRIVE RESISTANCE (Note 5)
Upper Drive Source Resistance VPVCC = 12V, 15mA source current 1.25 2.0 3.0 
Upper Drive Sink Resistance VPVCC = 12V, 15mA sink current 0.9 1.65 3.0 
Lower Drive Source Resistance VPVCC = 12V, 15mA source current 0.85 1.25 2.2 
Lower Drive Sink Resistance VPVCC = 12V, 15mA sink current 0.60 0.80 1.35 
OVER TEMPERATURE SHUTDOWN (Note 5)
Thermal Shutdown Setpoint - 160 - °C
Thermal Recovery Setpoint - 100 - °C

NOTES:
5. Limits established by characterization and are not production tested.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Timing Diagram
tPDHUGATE
tRUGATE tFUGATE
UGATE
LGATE
tFLGATE tRLGATE
tPDHLGATE
FN9289 Rev 6.00 Page 8 of 35

February 1, 2011
ISL6312
Functional Pin Descriptions FB and COMP

These pins are the internal error amplifier inverting input and
VCC
output respectively. FB, VDIFF, and COMP are tied together
VCC is the bias supply for the ICs small-signal circuitry. through external R-C networks to compensate the regulator.
Connect this pin to a +5V supply and decouple using a
quality 0.1µF ceramic capacitor. IDROOP
The IDROOP pin is the average channel-current sense
PVCC1_2 and PVCC3
output. Connecting this pin through a tuned parallel R-C
These pins are the power supply pins for the corresponding network to FB allows the converter to incorporate output
channel MOSFET drive, and can be connected to any voltage droop proportional to the output current. If voltage
voltage from +5V to +12V depending on the desired droop is not desired leave this pin unconnected.
MOSFET gate-drive level. Decouple these pins with a quality
1.0µF ceramic capacitor. REF
The REF input pin is the positive input of the error amplifier. It
Leaving PVCC3 unconnected or grounded programs the
is internally connected to the DAC output through a 1k
controller for 2-phase operation.
resistor. A capacitor is used between the REF pin and ground
GND to smooth the voltage transition during Dynamic VID
GND is the bias and reference ground for the IC. operations.
EN OFS
This pin is a threshold-sensitive (approximately 0.85V) enable The OFS pin provides a means to program a DC current for
input for the controller. Held low, this pin disables controller generating an offset voltage across the resistor between FB
operation. Pulled high, the pin enables the controller for and VDIFF. The offset current is generated via an external
operation. resistor and precision internal voltage references. The polarity
of the offset is selected by connecting the resistor to GND or
FS VCC. For no offset, the OFS pin should be left unconnected.
A resistor, placed from FS to ground, sets the switching
frequency of the controller. ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, ISEN3+,
ISEN4-, and ISEN4+
VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7 These pins are used for differentially sensing the
These are the inputs for the internal DAC that provides the corresponding channel output currents. The sensed currents
reference voltage for output regulation. These pins respond to are used for channel balancing, protection, and load line
TTL logic thresholds. These pins are internally pulled high, to regulation.
approximately 1.2V, by 40µA internal current sources for Intel
Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node
modes of operation, and pulled low by 20µA internal current
between the RC sense elements surrounding the inductor of
sources for AMD modes of operation. The internal pull-up
their respective channel. Tie the ISEN+ pins to the VCORE
current decreases to 0 as the VID voltage approaches the
side of their corresponding channel’s sense capacitor.
internal pull-up voltage. All VID pins are compatible with
external pull-up voltages not exceeding the IC’s bias voltage UGATE1, UGATE2, and UGATE3
(VCC). Connect these pins to the corresponding upper MOSFET
VRSEL gates. These pins are used to control the upper MOSFETs
and are monitored for shoot-through prevention purposes.
The state of this pin selects which of the available DAC tables
will be used to decode the VID inputs and puts the controller BOOT1, BOOT2, and BOOT3
into the corresponding mode of operation. Refer to Table 1 for These pins provide the bias voltage for the corresponding
available options and details of implementation. upper MOSFET drives. Connect these pins to appropriately-
VSEN and RGND chosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC pins provide the necessary
VSEN and RGND are inputs to the precision differential
bootstrap charge.
remote-sense amplifier and should be connected to the sense
pins of the remote load.
VDIFF
VDIFF is the output of the differential remote-sense amplifier.
The voltage on this pin is equal to the difference between
VSEN and RGND.
FN9289 Rev 6.00 Page 9 of 35

February 1, 2011
ISL6312
PHASE1, PHASE2, and PHASE3 Operation

Connect these pins to the sources of the corresponding
Multiphase Power Conversion
upper MOSFETs. These pins are the return path for the
upper MOSFET drives. Microprocessor load current profiles have changed to the
point that using single-phase regulators is no longer a viable
LGATE1, LGATE2, and LGATE3 solution. Designing a regulator that is cost-effective,
These pins are used to control the lower MOSFETs. Connect thermally sound, and efficient has become a challenge that
these pins to the corresponding lower MOSFETs’ gates. only multiphase converters can accomplish. The ISL6322
controller helps simplify implementation by integrating vital
PWM4 functions and requiring minimal external components. The
Pulse-width modulation output. Connect this pin to the PWM “Block Diagram” on page 3 provides a top level view of
input pin of an Intersil driver IC if 4-phase operation is multiphase power conversion using the ISL6322 controller.
desired.
EN_PH4
This pin has two functions. First, a resistor divider connected IL1 + IL2 + IL3, 7A/DIV
to this pin will provide a POR power-up synch between the
on-chip and external driver. The resistor divider should be IL3, 7A/DIV
designed so that when the POR-trip point of the external
driver is reached the voltage on this pin should be 1.21V. PWM3, 5V/DIV
IL2, 7A/DIV
The second function of this pin is disabling PWM4 for
3-phase operation. This can be accomplished by connecting
PWM2, 5V/DIV
this pin to a +5V supply.
IL1, 7A/DIV
SS
A resistor, placed from SS to ground, will set the soft-start PWM1, 5V/DIV
ramp slope for the Intel DAC modes of operation. Refer to 1µs/DIV
Equations 18 and 19 for proper resistor calculation. FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
For AMD modes of operation, the soft-start ramp frequency
is preset, so this pin can be left unconnected.
Interleaving
OVPSEL The switching of each channel in a multiphase converter is
This pin selects the OVP trip point during normal operation. timed to be symmetrically out of phase with each of the other
Leaving it unconnected or tieing it to ground selects the channels. In a 3-phase converter, each channel switches 1/3
default setting of VDAC+175mV for Intel Modes of operation cycle after the previous channel and 1/3 cycle before the
and VDAC+250mV for AMD modes of operation. Connecting following channel. As a result, the three-phase converter has a
this pin to VCC will select an OVP trip setting of VID+350mV combined ripple frequency three times greater than the ripple
for all modes of operation. frequency of any one phase. In addition, the peak-to-peak
amplitude of the combined inductor currents is reduced in
DRSEL
proportion to the number of phases (Equations 1 and 2).
This pin selects the adaptive dead time scheme the internal Increased ripple frequency and lower ripple amplitude mean
drivers will use. If driving MOSFETs, tie this pin to ground to that the designer can use less per-channel inductance and
select the PHASE detect scheme or to a +5V supply through lower total output capacitance for any performance
a 50k resistor to select the LGATE detect scheme. specification.
PGOOD Figure 1 illustrates the multiplicative effect on output ripple
During normal operation PGOOD indicates whether the frequency. The three channel currents (IL1, IL2, and IL3)
output voltage is within specified overvoltage and combine to form the AC ripple current and the DC load
undervoltage limits. If the output voltage exceeds these limits current. The ripple component has three times the ripple
or a reset event occurs (such as an overcurrent event), frequency of each individual channel current. Each PWM
PGOOD is pulled low. PGOOD is always low prior to the end pulse is terminated 1/3 of a cycle after the PWM pulse of the
of soft-start. previous phase. The peak-to-peak current for each phase is
about 7A, and the DC components of the inductor currents
combine to feed the load.
FN9289 Rev 6.00 Page 10 of 35

February 1, 2011
ISL6312
To understand the reduction of ripple current amplitude in the Active Pulse Positioning (APP) Modulated PWM
multiphase circuit, examine the equation representing an Operation
individual channel peak-to-peak inductor current. The ISL6312 uses a proprietary Active Pulse Positioning
 V IN – V OUT   V OUT (APP) modulation scheme to control the internal PWM
I  P – P  = ---------------------------------------------------------
- (EQ. 1)
L  fS  V signals that command each channel’s driver to turn their
IN
upper and lower MOSFETs on and off. The time interval in
In Equation 1, VIN and VOUT are the input and output
which a PWM signal can occur is generated by an internal
voltages respectively, L is the single-channel inductor value,
clock, whose cycle time is the inverse of the switching
and fS is the switching frequency.
frequency set by the resistor between the FS pin and
The output capacitors conduct the ripple component of the ground. The advantage of Intersil’s proprietary Active Pulse
inductor current. In the case of multiphase converters, the Positioning (APP) modulator is that the PWM signal has the
capacitor current is the sum of the ripple currents from each ability to turn on at any point during this PWM time interval,
of the individual channels. Compare Equation 1 to the
and turn off immediately after the PWM signal has
expression for the peak-to-peak current after the summation
transitioned high. This is important because is allows the
of N symmetrically phase-shifted inductor currents in
controller to quickly respond to output voltage drops
Equation 2. Peak-to-peak ripple current decreases by an
associated with current load spikes, while avoiding the ring
amount proportional to the number of channels. Output
back affects associated with other modulation schemes.
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple The PWM output state is driven by the position of the error
current. Reducing the inductor ripple current allows the amplifier output signal, VCOMP, minus the current correction
designer to use fewer or less costly output capacitors. signal relative to the proprietary modulator ramp waveform
 V IN – N  V OUT   V OUT as illustrated in Figure 3. At the beginning of each PWM time
I C  P – P  = -------------------------------------------------------------------
- (EQ. 2)
L  fS  V interval, this modified VCOMP signal is compared to the
IN
internal modulator waveform. As long as the modified
Another benefit of interleaving is to reduce input ripple VCOMP voltage is lower then the modulator waveform
current. Input capacitance is determined in part by the
voltage, the PWM signal is commanded low. The internal
maximum input ripple current. Multiphase topologies can
MOSFET driver detects the low state of the PWM signal and
improve overall system cost and size by lowering input ripple
turns off the upper MOSFET and turns on the lower
current and allowing the designer to reduce the cost of input
synchronous MOSFET. When the modified VCOMP voltage
capacitance. The example in Figure 2 illustrates input
crosses the modulator ramp, the PWM output transitions
currents from a three-phase converter combining to reduce
the total input ripple current. high, turning off the synchronous MOSFET and turning on
the upper MOSFET. The PWM signal will remain high until
The converter depicted in Figure 2 delivers 1.5V to a 36A load the modified VCOMP voltage crosses the modulator ramp
from a 12V input. The RMS input capacitor current is 5.9A.
again. When this occurs the PWM signal will transition low
Compare this to a single-phase converter also stepping down
again.
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter During each PWM time interval the PWM signal can only
must use an input capacitor bank with twice the RMS current transition high once. Once PWM transitions high it can not
capacity as the equivalent three-phase converter. transition high again until the beginning of the next PWM
INPUT-CAPACITOR CURRENT, 10A/DIV
time interval. This prevents the occurrence of double PWM
pulses occurring during a single period.
To further improve the transient response, ISL6312 also

implements Intersil’s proprietary Adaptive Phase Alignment
CHANNEL 3 (APA) technique, which turns on all phases together under
INPUT CURRENT transient events with large step current. With both APP and
10A/DIV
APA control, ISL6312 can achieve excellent transient
performance and reduce the demand on the output
CHANNEL 2
INPUT CURRENT capacitors.
10A/DIV
Channel-Current Balance
CHANNEL 1 One important benefit of multiphase operation is the thermal
INPUT CURRENT advantage gained by distributing the dissipated heat over
10A/DIV
multiple devices and greater area. By doing this the designer
1µs/DIV
avoids the complexity of driving parallel MOSFETs and the
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
expense of using expensive heat sinks and exotic magnetic
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER materials.
FN9289 Rev 6.00 Page 11 of 35

February 1, 2011
ISL6312
In order to realize the thermal advantage, it is important that Continuous Current Sampling
each channel in a multiphase converter be controlled to In order to realize proper current-balance, the currents in
carry equal amounts of current at any load level. To achieve each channel are sensed continuously every switching
this, the currents through each channel must be sampled cycle. During this time the current-sense amplifier uses the
every switching cycle. The sampled currents, In, from each ISEN inputs to reproduce a signal proportional to the
active channel are summed together and divided by the inductor current, IL. This sensed current, ISEN, is simply a
number of active channels. The resulting cycle average scaled version of the inductor current.
current, IAVG, provides a measure of the total load-current
demand on the converter during each switching cycle. The ISL6312 supports inductor DCR current sensing to
Channel-current balance is achieved by comparing the continuously sense each channel’s current for channel-
sampled current of each channel to the cycle average current balance. The internal circuitry, shown in Figure 5
current, and making the proper adjustment to each channel represents channel n of an N-channel converter. This
pulse width based on the error. Intersil’s patented current- circuitry is repeated for each channel in the converter, but
balance method is illustrated in Figure 3, with error may not be active depending on how many channels are
correction for Channel 1 represented. In the figure, the cycle operating.
average current, IAVG, is compared with the Channel 1 VIN
IL
sample, I1 , to create an error signal IER.
UGATE(n)
L
MOSFET DCR VOUT
+ PWM1
VCOMP DRIVER
+ TO GATE LGATE(n) INDUCTOR COUT
MODULATOR CONTROL
- VL(s) -
+
RAMP - LOGIC
WAVEFORM
VC(s) -
+
FILTER f(s)
I4 R1 C1
IER
IAVG
N  I3 R2*
- ISL6312 INTERNAL CIRCUIT
+
I2
I1 In
NOTE: Channel 3 and 4 are optional.

SAMPLE
FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT +
ISEN-(n)
VC(s)
-
+
-
The filtered error signal modifies the pulse width RISEN ISEN+(n)
commanded by VCOMP to correct any unbalance and force

*R2 is OPTIONAL
IER toward zero. The same method for error signal ISEN
correction is applied to each active channel.

FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
Inductor windings have a characteristic distributed

PWM resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
SWITCHING PERIOD lumped quantity, as shown in Figure 5. The channel current
IL, flowing through the inductor, passes through the DCR.
IL Equation 3 shows the s-domain equivalent voltage, VL,
across the inductor.
V L  s  = I L   s  L + DCR  (EQ. 3)
ISEN
A simple R-C network across the inductor (R1 and C)

extracts the DCR voltage, as shown in Figure 5. The voltage
across the sense capacitor, VC, can be shown to be
TIME
proportional to the channel current IL, shown in Equation 4.
FIGURE 4. CONTINUOUS CURRENT SAMPLING
FN9289 Rev 6.00 Page 12 of 35

February 1, 2011
ISL6312
sL
 ------------- + 1 (EQ. 4) TABLE 1. ISL6312 DAC SELECT TABLE
 DCR 
VC  s  = -  DCR  I L
-------------------------------------
 s  R1  C + 1  DAC VERSION VRSEL PIN VID7 PIN
In some cases it may be necessary to use a resistor divider VR10(Extended) VRSEL = GND -
R-C network to sense the current through the inductor. This VR11 VRSEL = VCC/2 -
can be accomplished by placing a second resistor, R2,
AMD 5-Bit VRSEL = VCC LOW
across the sense capacitor. In these cases the voltage
across the sense capacitor, VC, becomes proportional to the AMD 6-Bit VRSEL = VCC HIGH
channel current IL, and the resistor divider ratio, K.
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
sL
 ------------- + 1 (EQ. 5) CODES
 DCR 
VC  s  = -  K  DCR  I L
------------------------------------------------------- VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC
  R 1  R 2  
 s  ------------------------  C + 1 0 1 0 1 0 1 1 1.60000
 R1 + R2 
0 1 0 1 0 1 0 1.59375
R2
K = --------------------- (EQ. 6) 0 1 0 1 1 0 1 1.58750
R2 + R1
0 1 0 1 1 0 0 1.58125
If the R-C network components are selected such that the 0 1 0 1 1 1 1 1.57500
RC time constant matches the inductor L/DCR time 0 1 0 1 1 1 0 1.56875
constant, then VC is equal to the voltage drop across the
0 1 1 0 0 0 1 1.56250
DCR multiplied by the ratio of the resistor divider, K. If a
resistor divider is not being used, the value for K is 1. 0 1 1 0 0 0 0 1.55625
0 1 1 0 0 1 1 1.55000
The capacitor voltage VC, is then replicated across the
sense resistor RISEN. The current through RISEN is 0 1 1 0 0 1 0 1.54375
proportional to the inductor current. Equation 7 shows that 0 1 1 0 1 0 1 1.53750
the proportion between the channel current and the sensed
0 1 1 0 1 0 0 1.53125
current (ISEN) is driven by the value of the sense resistor,
the resistor divider ratio, and the DCR of the inductor. 0 1 1 0 1 1 1 1.52500
DCR 0 1 1 0 1 1 0 1.51875
I SEN = K  I L  ------------------ (EQ. 7)
R ISEN
0 1 1 1 0 0 1 1.51250
0 1 1 1 0 0 0 1.50625
Output Voltage Setting
The ISL6312 uses a digital to analog converter (DAC) to 0 1 1 1 0 1 1 1.50000
generate a reference voltage based on the logic signals at 0 1 1 1 0 1 0 1.49375
the VID pins. The DAC decodes the logic signals into one of
0 1 1 1 1 0 1 1.48750
the discrete voltages shown in Tables 2, 3, 4 and 5. In Intel
modes of operation, each VID pin is pulled up to an internal 0 1 1 1 1 0 0 1.48125
1.2V voltage by a weak current source (40µA), which 0 1 1 1 1 1 1 1.47500
decreases to 0A as the voltage at the VID pin varies from 0
0 1 1 1 1 1 0 1.46875
to the internal 1.2V pull-up voltage. In AMD modes of
operation the VID pins are pulled low by a weak 20µA 1 0 0 0 0 0 1 1.46250
current source. External pull-up resistors or active-high 1 0 0 0 0 0 0 1.45625
output stages can augment the pull-up current sources, up to
1 0 0 0 0 1 1 1.45000
a voltage of 5V.
1 0 0 0 0 1 0 1.44375
The ISL6312 accommodates four different DAC ranges: Intel
1 0 0 0 1 0 1 1.43750
VR10 (Extended), Intel VR11, AMD K8/K9 5-bit, and AMD
6-bit. The state of the VRSEL and VID7 pins decide which 1 0 0 0 1 0 0 1.43125
DAC version is active. Refer to Table 1 for a description of 1 0 0 0 1 1 1 1.42500
how to select the desired DAC version. For VR11 setting, tie
1 0 0 0 1 1 0 1.41875
the VRSEL pin to the midpoint of a 10k(or other suitable
value) resistor divider connected from VCC to GND. 1 0 0 1 0 0 1 1.41250
1 0 0 1 0 0 0 1.40625
FN9289 Rev 6.00 Page 13 of 35

February 1, 2011
ISL6312
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES (Continued) CODES (Continued)
VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC
1 0 0 1 0 1 1 1.40000 1 1 1 0 0 0 0 1.15625
1 0 0 1 0 1 0 1.39375 1 1 1 0 0 1 1 1.15000
1 0 0 1 1 0 1 1.38750 1 1 1 0 0 1 0 1.14375
1 0 0 1 1 0 0 1.38125 1 1 1 0 1 0 1 1.13750
1 0 0 1 1 1 1 1.37500 1 1 1 0 1 0 0 1.13125
1 0 0 1 1 1 0 1.36875 1 1 1 0 1 1 1 1.12500
1 0 1 0 0 0 1 1.36250 1 1 1 0 1 1 0 1.11875
1 0 1 0 0 0 0 1.35625 1 1 1 1 0 0 1 1.11250
1 0 1 0 0 1 1 1.35000 1 1 1 1 0 0 0 1.10625
1 0 1 0 0 1 0 1.34375 1 1 1 1 0 1 1 1.10000
1 0 1 0 1 0 1 1.33750 1 1 1 1 0 1 0 1.09375
1 0 1 0 1 0 0 1.33125 1 1 1 1 1 0 1 OFF
1 0 1 0 1 1 1 1.32500 1 1 1 1 1 0 0 OFF
1 0 1 0 1 1 0 1.31875 1 1 1 1 1 1 1 OFF
1 0 1 1 0 0 1 1.31250 1 1 1 1 1 1 0 OFF
1 0 1 1 0 0 0 1.30625 0 0 0 0 0 0 1 1.08750
1 0 1 1 0 1 1 1.30000 0 0 0 0 0 0 0 1.08125
1 0 1 1 0 1 0 1.29375 0 0 0 0 0 1 1 1.07500
1 0 1 1 1 0 1 1.28750 0 0 0 0 0 1 0 1.06875
1 0 1 1 1 0 0 1.28125 0 0 0 0 1 0 1 1.06250
1 0 1 1 1 1 1 1.27500 0 0 0 0 1 0 0 1.05625
1 0 1 1 1 1 0 1.26875 0 0 0 0 1 1 1 1.05000
1 1 0 0 0 0 1 1.26250 0 0 0 0 1 1 0 1.04375
1 1 0 0 0 0 0 1.25625 0 0 0 1 0 0 1 1.03750
1 1 0 0 0 1 1 1.25000 0 0 0 1 0 0 0 1.03125
1 1 0 0 0 1 0 1.24375 0 0 0 1 0 1 1 1.02500
1 1 0 0 1 0 1 1.23750 0 0 0 1 0 1 0 1.01875
1 1 0 0 1 0 0 1.23125 0 0 0 1 1 0 1 1.01250
1 1 0 0 1 1 1 1.22500 0 0 0 1 1 0 0 1.00625
1 1 0 0 1 1 0 1.21875 0 0 0 1 1 1 1 1.00000
1 1 0 1 0 0 1 1.21250 0 0 0 1 1 1 0 0.99375
1 1 0 1 0 0 0 1.20625 0 0 1 0 0 0 1 0.98750
1 1 0 1 0 1 1 1.20000 0 0 1 0 0 0 0 0.98125
1 1 0 1 0 1 0 1.19375 0 0 1 0 0 1 1 0.97500
1 1 0 1 1 0 1 1.18750 0 0 1 0 0 1 0 0.96875
1 1 0 1 1 0 0 1.18125 0 0 1 0 1 0 1 0.96250
1 1 0 1 1 1 1 1.17500 0 0 1 0 1 0 0 0.95625
1 1 0 1 1 1 0 1.16875 0 0 1 0 1 1 1 0.95000
1 1 1 0 0 0 1 1.16250 0 0 1 0 1 1 0 0.94375
FN9289 Rev 6.00 Page 14 of 35

February 1, 2011
ISL6312
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)
CODES (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC
VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC
0 0 0 1 0 0 1 1 1.49375
0 0 1 1 0 0 1 0.93750
0 0 0 1 0 1 0 0 1.48750
0 0 1 1 0 0 0 0.93125
0 0 0 1 0 1 0 1 1.48125
0 0 1 1 0 1 1 0.92500
0 0 0 1 0 1 1 0 1.47500
0 0 1 1 0 1 0 0.91875
0 0 0 1 0 1 1 1 1.46875
0 0 1 1 1 0 1 0.91250
0 0 0 1 1 0 0 0 1.46250
0 0 1 1 1 0 0 0.90625
0 0 0 1 1 0 0 1 1.45625
0 0 1 1 1 1 1 0.90000
0 0 0 1 1 0 1 0 1.45000
0 0 1 1 1 1 0 0.89375
0 0 0 1 1 0 1 1 1.44375
0 1 0 0 0 0 1 0.88750
0 0 0 1 1 1 0 0 1.43750
0 1 0 0 0 0 0 0.88125
0 0 0 1 1 1 0 1 1.43125
0 1 0 0 0 1 1 0.87500
0 0 0 1 1 1 1 0 1.42500
0 1 0 0 0 1 0 0.86875
0 0 0 1 1 1 1 1 1.41875
0 1 0 0 1 0 1 0.86250
0 0 1 0 0 0 0 0 1.41250
0 1 0 0 1 0 0 0.85625
0 0 1 0 0 0 0 1 1.40625
0 1 0 0 1 1 1 0.85000
0 0 1 0 0 0 1 0 1.40000
0 1 0 0 1 1 0 0.84375
0 0 1 0 0 0 1 1 1.39375
0 1 0 1 0 0 1 0.83750
0 0 1 0 0 1 0 0 1.38750
0 1 0 1 0 0 0 0.83125
0 0 1 0 0 1 0 1 1.38125
TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES 0 0 1 0 0 1 1 0 1.37500
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC 0 0 1 0 0 1 1 1 1.36875
0 0 0 0 0 0 0 0 OFF 0 0 1 0 1 0 0 0 1.36250
0 0 0 0 0 0 0 1 OFF 0 0 1 0 1 0 0 1 1.35625
0 0 0 0 0 0 1 0 1.60000 0 0 1 0 1 0 1 0 1.35000
0 0 0 0 0 0 1 1 1.59375 0 0 1 0 1 0 1 1 1.34375
0 0 0 0 0 1 0 0 1.58750 0 0 1 0 1 1 0 0 1.33750
0 0 0 0 0 1 0 1 1.58125 0 0 1 0 1 1 0 1 1.33125
0 0 0 0 0 1 1 0 1.57500 0 0 1 0 1 1 1 0 1.32500
0 0 0 0 0 1 1 1 1.56875 0 0 1 0 1 1 1 1 1.31875
0 0 0 0 1 0 0 0 1.56250 0 0 1 1 0 0 0 0 1.31250
0 0 0 0 1 0 0 1 1.55625 0 0 1 1 0 0 0 1 1.30625
0 0 0 0 1 0 1 0 1.55000 0 0 1 1 0 0 1 0 1.30000
0 0 0 0 1 0 1 1 1.54375 0 0 1 1 0 0 1 1 1.29375
0 0 0 0 1 1 0 0 1.53750 0 0 1 1 0 1 0 0 1.28750
0 0 0 0 1 1 0 1 1.53125 0 0 1 1 0 1 0 1 1.28125
0 0 0 0 1 1 1 0 1.52500 0 0 1 1 0 1 1 0 1.27500
0 0 0 0 1 1 1 1 1.51875 0 0 1 1 0 1 1 1 1.26875
0 0 0 1 0 0 0 0 1.51250 0 0 1 1 1 0 0 0 1.26250
0 0 0 1 0 0 0 1 1.50625 0 0 1 1 1 0 0 1 1.25625
0 0 0 1 0 0 1 0 1.50000 0 0 1 1 1 0 1 0 1.25000
FN9289 Rev 6.00 Page 15 of 35

February 1, 2011
ISL6312
TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued) TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC
0 0 1 1 1 0 1 1 1.24375 0 1 1 0 0 0 1 1 0.99375
0 0 1 1 1 1 0 0 1.23750 0 1 1 0 0 1 0 0 0.98750
0 0 1 1 1 1 0 1 1.23125 0 1 1 0 0 1 0 1 0.98125
0 0 1 1 1 1 1 0 1.22500 0 1 1 0 0 1 1 0 0.97500
0 0 1 1 1 1 1 1 1.21875 0 1 1 0 0 1 1 1 0.96875
0 1 0 0 0 0 0 0 1.21250 0 1 1 0 1 0 0 0 0.96250
0 1 0 0 0 0 0 1 1.20625 0 1 1 0 1 0 0 1 0.95625
0 1 0 0 0 0 1 0 1.20000 0 1 1 0 1 0 1 0 0.95000
0 1 0 0 0 0 1 1 1.19375 0 1 1 0 1 0 1 1 0.94375
0 1 0 0 0 1 0 0 1.18750 0 1 1 0 1 1 0 0 0.93750
0 1 0 0 0 1 0 1 1.18125 0 1 1 0 1 1 0 1 0.93125
0 1 0 0 0 1 1 0 1.17500 0 1 1 0 1 1 1 0 0.92500
0 1 0 0 0 1 1 1 1.16875 0 1 1 0 1 1 1 1 0.91875
0 1 0 0 1 0 0 0 1.16250 0 1 1 1 0 0 0 0 0.91250
0 1 0 0 1 0 0 1 1.15625 0 1 1 1 0 0 0 1 0.90625
0 1 0 0 1 0 1 0 1.15000 0 1 1 1 0 0 1 0 0.90000
0 1 0 0 1 0 1 1 1.14375 0 1 1 1 0 0 1 1 0.89375
0 1 0 0 1 1 0 0 1.13750 0 1 1 1 0 1 0 0 0.88750
0 1 0 0 1 1 0 1 1.13125 0 1 1 1 0 1 0 1 0.88125
0 1 0 0 1 1 1 0 1.12500 0 1 1 1 0 1 1 0 0.87500
0 1 0 0 1 1 1 1 1.11875 0 1 1 1 0 1 1 1 0.86875
0 1 0 1 0 0 0 0 1.11250 0 1 1 1 1 0 0 0 0.86250
0 1 0 1 0 0 0 1 1.10625 0 1 1 1 1 0 0 1 0.85625
0 1 0 1 0 0 1 0 1.10000 0 1 1 1 1 0 1 0 0.85000
0 1 0 1 0 0 1 1 1.09375 0 1 1 1 1 0 1 1 0.84375
0 1 0 1 0 1 0 0 1.08750 0 1 1 1 1 1 0 0 0.83750
0 1 0 1 0 1 0 1 1.08125 0 1 1 1 1 1 0 1 0.83125
0 1 0 1 0 1 1 0 1.07500 0 1 1 1 1 1 1 0 0.82500
0 1 0 1 0 1 1 1 1.06875 0 1 1 1 1 1 1 1 0.81875
0 1 0 1 1 0 0 0 1.06250 1 0 0 0 0 0 0 0 0.81250
0 1 0 1 1 0 0 1 1.05625 1 0 0 0 0 0 0 1 0.80625
0 1 0 1 1 0 1 0 1.05000 1 0 0 0 0 0 1 0 0.80000
0 1 0 1 1 0 1 1 1.04375 1 0 0 0 0 0 1 1 0.79375
0 1 0 1 1 1 0 0 1.03750 1 0 0 0 0 1 0 0 0.78750
0 1 0 1 1 1 0 1 1.03125 1 0 0 0 0 1 0 1 0.78125
0 1 0 1 1 1 1 0 1.02500 1 0 0 0 0 1 1 0 0.77500
0 1 0 1 1 1 1 1 1.01875 1 0 0 0 0 1 1 1 0.76875
0 1 1 0 0 0 0 0 1.01250 1 0 0 0 1 0 0 0 0.76250
0 1 1 0 0 0 0 1 1.00625 1 0 0 0 1 0 0 1 0.75625
0 1 1 0 0 0 1 0 1.00000 1 0 0 0 1 0 1 0 0.75000
FN9289 Rev 6.00 Page 16 of 35

February 1, 2011
ISL6312
TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued) TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC
1 0 0 0 1 0 1 1 0.74375 1 1 1 1 1 1 1 0 OFF
1 0 0 0 1 1 0 0 0.73750 1 1 1 1 1 1 1 1 OFF
1 0 0 0 1 1 0 1 0.73125
TABLE 4. AMD 5-BIT VOLTAGE IDENTIFICATION CODES
1 0 0 0 1 1 1 0 0.72500
VID4 VID3 VID2 VID1 VID0 VDAC
1 0 0 0 1 1 1 1 0.71875
1 1 1 1 1 Off
1 0 0 1 0 0 0 0 0.71250
1 1 1 1 0 0.800
1 0 0 1 0 0 0 1 0.70625
1 1 1 0 1 0.825
1 0 0 1 0 0 1 0 0.70000
1 1 1 0 0 0.850
1 0 0 1 0 0 1 1 0.69375
1 1 0 1 1 0.875
1 0 0 1 0 1 0 0 0.68750
1 1 0 1 0 0.900
1 0 0 1 0 1 0 1 0.68125
1 1 0 0 1 0.925
1 0 0 1 0 1 1 0 0.67500
1 1 0 0 0 0.950
1 0 0 1 0 1 1 1 0.66875
1 0 1 1 1 0.975
1 0 0 1 1 0 0 0 0.66250
1 0 1 1 0 1.000
1 0 0 1 1 0 0 1 0.65625
1 0 1 0 1 1.025
1 0 0 1 1 0 1 0 0.65000
1 0 1 0 0 1.050
1 0 0 1 1 0 1 1 0.64375
1 0 0 1 1 1.075
1 0 0 1 1 1 0 0 0.63750
1 0 0 1 0 1.100
1 0 0 1 1 1 0 1 0.63125
1 0 0 0 1 1.125
1 0 0 1 1 1 1 0 0.62500
1 0 0 0 0 1.150
1 0 0 1 1 1 1 1 0.61875
0 1 1 1 1 1.175
1 0 1 0 0 0 0 0 0.61250
0 1 1 1 0 1.200
1 0 1 0 0 0 0 1 0.60625
0 1 1 0 1 1.225
1 0 1 0 0 0 1 0 0.60000
0 1 1 0 0 1.250
1 0 1 0 0 0 1 1 0.59375
0 1 0 1 1 1.275
1 0 1 0 0 1 0 0 0.58750
0 1 0 1 0 1.300
1 0 1 0 0 1 0 1 0.58125
0 1 0 0 1 1.325
1 0 1 0 0 1 1 0 0.57500
0 1 0 0 0 1.350
1 0 1 0 0 1 1 1 0.56875
0 0 1 1 1 1.375
1 0 1 0 1 0 0 0 0.56250
0 0 1 1 0 1.400
1 0 1 0 1 0 0 1 0.55625
0 0 1 0 1 1.425
1 0 1 0 1 0 1 0 0.55000
0 0 1 0 0 1.450
1 0 1 0 1 0 1 1 0.54375
0 0 0 1 1 1.475
1 0 1 0 1 1 0 0 0.53750
0 0 0 1 0 1.500
1 0 1 0 1 1 0 1 0.53125
0 0 0 0 1 1.525
1 0 1 0 1 1 1 0 0.52500
0 0 0 0 0 1.550
1 0 1 0 1 1 1 1 0.51875
1 0 1 1 0 0 0 0 0.51250
1 0 1 1 0 0 0 1 0.50625
1 0 1 1 0 0 1 0 0.50000
FN9289 Rev 6.00 Page 17 of 35

February 1, 2011
ISL6312
TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION CODES TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION CODES
(Continued)
VID5 VID4 VID3 VID2 VID1 VID0 VDAC VID5 VID4 VID3 VID2 VID1 VID0 VDAC
0 0 0 0 0 0 1.5500 1 0 0 1 1 1 0.6750
0 0 0 0 0 1 1.5250 1 0 1 0 0 0 0.6625
0 0 0 0 1 0 1.5000 1 0 1 0 0 1 0.6500
0 0 0 0 1 1 1.4750 1 0 1 0 1 0 0.6375
0 0 0 1 0 0 1.4500 1 0 1 0 1 1 0.6250
0 0 0 1 0 1 1.4250 1 0 1 1 0 0 0.6125
0 0 0 1 1 0 1.4000 1 0 1 1 0 1 0.6000
0 0 0 1 1 1 1.3750 1 0 1 1 1 0 0.5875
0 0 1 0 0 0 1.3500 1 0 1 1 1 1 0.5750
0 0 1 0 0 1 1.3250 1 1 0 0 0 0 0.5625
0 0 1 0 1 0 1.3000 1 1 0 0 0 1 0.5500
0 0 1 0 1 1 1.2750 1 1 0 0 1 0 0.5375
0 0 1 1 0 0 1.2500 1 1 0 0 1 1 0.5250
0 0 1 1 0 1 1.2250 1 1 0 1 0 0 0.5125
0 0 1 1 1 0 1.2000 1 1 0 1 0 1 0.5000
0 0 1 1 1 1 1.1750 1 1 0 1 1 0 0.4875
0 1 0 0 0 0 1.1500 1 1 0 1 1 1 0.4750
0 1 0 0 0 1 1.1250 1 1 1 0 0 0 0.4625
0 1 0 0 1 0 1.1000 1 1 1 0 0 1 0.4500
0 1 0 0 1 1 1.0750 1 1 1 0 1 0 0.4375
0 1 0 1 0 0 1.0500 1 1 1 0 1 1 0.4250
0 1 0 1 0 1 1.0250 1 1 1 1 0 0 0.4125
0 1 0 1 1 0 1.0000 1 1 1 1 0 1 0.4000
0 1 0 1 1 1 0.9750 1 1 1 1 1 0 0.3875
0 1 1 0 0 0 0.9500 1 1 1 1 1 1 0.3750
0 1 1 0 0 1 0.9250
Voltage Regulation
0 1 1 0 1 0 0.9000
The integrating compensation network shown in Figure 6
0 1 1 0 1 1 0.8750 insures that the steady-state error in the output voltage is
0 1 1 1 0 0 0.8500 limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
0 1 1 1 0 1 0.8250
remote-sense and error amplifiers. Intersil specifies the
0 1 1 1 1 0 0.8000 guaranteed tolerance of the ISL6312 to include the
0 1 1 1 1 1 0.7750 combined tolerances of each of these elements.
1 0 0 0 0 0 0.7625 The output of the error amplifier, VCOMP, is compared to the
1 0 0 0 0 1 0.7500 triangle waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
1 0 0 0 1 0 0.7375
and regulate the converter output so that the voltage at FB is
1 0 0 0 1 1 0.7250 equal to the voltage at REF. This will regulate the output
1 0 0 1 0 0 0.7125 voltage to be equal to Equation 8. The internal and external
circuitry that controls voltage regulation is illustrated in
1 0 0 1 0 1 0.7000
Figure 6.
1 0 0 1 1 0 0.6875
FN9289 Rev 6.00 Page 18 of 35

February 1, 2011
ISL6312
negative spike can be sustained without crossing the lower

V OUT = V REF – V OFS – V DROOP (EQ. 8)
limit. By adding a well controlled output impedance, the
The ISL6312 incorporates an internal differential output voltage under load can effectively be level shifted
remote-sense amplifier in the feedback path. The amplifier down so that a larger positive spike can be sustained without
removes the voltage error encountered when measuring the crossing the upper specification limit.
output voltage relative to the controller ground reference As shown in Figure 6, a current proportional to the average
point resulting in a more accurate means of sensing output current of all active channels, IAVG, flows from FB through a
voltage. Connect the microprocessor sense pins to the load-line regulation resistor RFB. The resulting voltage drop
non-inverting input, VSEN, and inverting input, RGND, of the across RFB is proportional to the output current, effectively
remote-sense amplifier. The remote-sense output, VDIFF, is creating an output voltage droop with a steady-state value
connected to the inverting input of the error amplifier through defined as:
an external resistor.
V DROOP = I AVG  R FB (EQ. 9)
EXTERNAL CIRCUIT ISL6312 INTERNAL CIRCUIT
COMP The regulated output voltage is reduced by the droop voltage

VDROOP. The output voltage as a function of load current is
VID DAC derived by combining Equations 7, 8, and 9.
CC
 I OUT DCR 
REF V OUT = V REF – V OFS –  -------------  ------------------  R FB (EQ. 10)
1k  N R ISEN 
RC
CREF + In Equation 10, VREF is the reference voltage, VOFS is the
ERROR
AMPLIFIER programmed offset voltage, IOUT is the total output current
FB - VCOMP
of the converter, RISEN is the internal sense resistor
IOFS connected to the ISEN+ pin, RFB is the feedback resistor, N
is the active channel number, and DCR is the Inductor DCR
IDROOP IAVG
value.
+
RFB (VDROOP + VOFS)
-
Therefore the equivalent loadline impedance, i.e. droop
VDIFF
impedance, is equal to Equation 11:
R FB DCR
R LL = ------------  ------------------ (EQ. 11)
VSEN N R ISEN
VOUT+
+
-
Output-Voltage Offset Programming
VOUT- RGND
The ISL6312 allows the designer to accurately adjust the
DIFFERENTIAL
REMOTE-SENSE offset voltage by connecting a resistor, ROFS, from the OFS
AMPLIFIER pin to VCC or GND. When ROFS is connected between OFS
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE and VCC, the voltage across it is regulated to 1.6V. This
REGULATION WITH OFFSET ADJUSTMENT causes a proportional current (IOFS) to flow into the FB pin.
Load-Line (Droop) Regulation If ROFS is connected to ground, the voltage across it is
regulated to 0.4V, and IOFS flows out of the FB pin. The
Some microprocessor manufacturers require a
offset current flowing through the resistor between VDIFF
precisely-controlled output resistance. This dependence of
and FB will generate the desired offset voltage which is
output voltage on load current is often termed “droop” or
equal to the product (IOFS x RFB). These functions are
“load line” regulation. By adding a well controlled output
shown in Figures 7 and 8.
impedance, the output voltage can effectively be level shifted
in a direction which works to achieve the load-line regulation Once the desired output offset voltage has been determined,
required by these manufacturers. use the following formulas to set ROFS:
In other cases, the designer may determine that a more For Negative Offset (connect ROFS to GND):
cost-effective solution can be achieved by adding droop.
0.4  R FB
Droop can help to reduce the output-voltage spike that R OFS = -------------------------- (EQ. 12)
V OFFSET
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL For Positive Offset (connect ROFS to VCC):
of the output capacitors selected. By positioning the no-load 1.6  R FB
R OFS = -------------------------- (EQ. 13)
voltage level near the upper specification limit, a larger V OFFSET
FN9289 Rev 6.00 Page 19 of 35

February 1, 2011
ISL6312
a new code is established and it remains stable for 3

FB consecutive readings (1ms to 1.33ms), the ISL6312
- E/A recognizes the new code and changes the internal DAC
VOFS RFB IOFS
reference directly to the new level. The Intel processor
+
controls the VID transitions and is responsible for
REF
VDIFF 1:1 incrementing or decrementing one VID step at a time. In
CURRENT
MIRROR VR10 and VR11 settings, the ISL6312 will immediately
change the internal DAC reference to the new requested
value as soon as the request is validated, which means the
IOFS
fastest recommended rate at which a bit change can occur is
once every 2ms. In cases where the reference step is too
large, the sudden change can trigger overcurrent or
VCC overvoltage events.
- In order to ensure the smooth transition of output voltage
ROFS 1.6V
+ during a VR10 or VR11 VID change, a VID step change
smoothing network is required. This network is composed of
OFS
ISL6312
an internal 1k resistor between the DAC and the REF pin,
and the external capacitor CREF, between the REF pin and
VCC
ground. The selection of CREF is based on the time duration
FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE for 1 bit VID change and the allowable delay time.
PROGRAMMING
Assuming the microprocessor controls the VID change at 1
bit every TVID, the relationship between CREF and TVID is
FB
given by Equation 14.
+ E/A
VOFS RFB IOFS C REF = 0.001  S   T VID (EQ. 14)
-
REF As an example, for a VID step change rate of 5ms per bit,
VDIFF VCC the value of CREF is 5600pF based on Equation 14.
AMD DYNAMIC VID TRANSITIONS

1:1
CURRENT IOFS
When running in AMD 5-bit or 6-bit modes of operation, the
MIRROR
ISL6312 responds differently to a dynamic VID change then
when in Intel VR10 or VR11 mode. In the AMD modes the
ISL6312 still checks the VID inputs on the positive edge of
an internal 3MHz clock. In these modes the VID code can be
+ changed by more than a 1-bit step at a time. If a new code is
0.4V established and it remains stable for 3 consecutive readings
-
OFS
(1ms to 1.33ms), the ISL6312 recognizes the change and
ROFS begins slewing the DAC in 6.25mV steps at a stepping
ISL6312
frequency of 330kHz until the VID and DAC are equal. Thus,
GND GND the total time required for a VID change, tDVID, is dependent
FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE only on the size of the VID change (DVVID).
PROGRAMMING
The time required for a ISL6312-based converter in AMD
Dynamic VID 5-bit DAC configuration to make a 1.1V to 1.5V reference
Modern microprocessors need to make changes to their core voltage change is about 194ms, as calculated using
voltage as part of normal operation. They direct the ISL6312 to Equation 15.
do this by making changes to the VID inputs. The ISL6312 is 1 V VID
t DVID = --------------------------   --------------------- (EQ. 15)
required to monitor the DAC inputs and respond to on-the-fly 3  0.00625
330  10
VID changes in a controlled manner, supervising a safe output
voltage transition without discontinuity or disruption. The DAC In order to ensure the smooth transition of output voltage
mode the ISL6312 is operating in determines how the controller during an AMD VID change, a VID step change smoothing
responds to a dynamic VID change. network is required. This network is composed of an internal
1k resistor between the DAC and the REF pin, and the
INTEL DYNAMIC VID TRANSITIONS external capacitor CREF, between the REF pin and ground.
When in Intel VR10 or VR11 mode the ISL6312 checks the For AMD VID transitions CREF should be a 1000pF
VID inputs on the positive edge of an internal 3MHz clock. If capacitor.
FN9289 Rev 6.00 Page 20 of 35

February 1, 2011
ISL6312
User Selectable Adaptive Deadtime Control Once the PHASE is high, the advanced adaptive
Techniques shoot-through circuitry monitors the PHASE and UGATE
The ISL6312 integrated drivers incorporate two different voltages during a PWM falling edge and the subsequent
adaptive deadtime control techniques, which the user can UGATE turn-off. If either the UGATE falls to less than 1.75V
choose between. Both of these control techniques help to above the PHASE or the PHASE falls to less than +0.8V, the
minimize deadtime, resulting in high efficiency from the reduced LGATE is released to turn on.
freewheeling time of the lower MOSFET body-diode Internal Bootstrap Device
conduction, and both help to prevent the upper and lower
All three integrated drivers feature an internal bootstrap
MOSFETs from conducting simultaneously. This is
schottky diode. Simply adding an external capacitor across
accomplished by ensuring either rising gate turns on its
the BOOT and PHASE pins completes the bootstrap circuit.
MOSFET with minimum and sufficient delay after the other has
The bootstrap function is also designed to prevent the
turned off.
bootstrap capacitor from overcharging due to the large
The difference between the two adaptive deadtime control negative swing at the PHASE node. This reduces voltage
techniques is the method in which they detect that the lower stress on the boot to phase pins.
MOSFET has transitioned off in order to turn on the upper 1.6
MOSFET. The state of the DRSEL pin chooses which of the
two control techniques is active. By tying the DRSEL pin 1.4
directly to ground, the PHASE Detect Scheme is chosen,
1.2
which monitors the voltage on the PHASE pin to determine if
the lower MOSFET has transitioned off or not. Tying the 1.0
CBOOT_CAP (µF)
DRSEL pin to VCC though a 50k resistor selects the
LGATE Detect Scheme, which monitors the voltage on the 0.8
LGATE pin to determine if the lower MOSFET has turned off
0.6
or not. For both schemes, the method for determining
QGATE = 100nC
whether the upper MOSFET has transitioned off in order to
0.4
signal to turn on the lower MOSFET is the same. 50nC
0.2
PHASE DETECT 20nC
If the DRSEL pin is tied directly to ground, the PHASE Detect 0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
adaptive deadtime control technique is selected. For the
VBOOT_CAP (V)
PHASE detect scheme, during turn-off of the lower MOSFET,
the PHASE voltage is monitored until it reaches a -0.3V/+0.8V FIGURE 9. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
(forward/reverse inductor current). At this time the UGATE is VOLTAGE
released to rise. An auto-zero comparator is used to correct the
rDS(ON) drop in the phase voltage preventing false detection of
The bootstrap capacitor must have a maximum voltage
the -0.3V phase level during rDS(ON) conduction period. In the
rating above PVCC + 4V and its capacitance value can be
case of zero current, the UGATE is released after 35ns delay of
chosen from Equation 16: where QG1 is the amount of gate
the LGATE dropping below 0.5V. When LGATE first begins to
charge per upper MOSFET at VGS1 gate-source voltage and
transition low, this quick transition can disturb the PHASE node
NQ1 is the number of control MOSFETs. The VBOOT_CAP
and cause a false trip, so there is 20ns of blanking time once
term is defined as the allowable droop in the rail of the upper
LGATE falls until PHASE is monitored.
gate drive.
Once the PHASE is high, the advanced adaptive
Q GATE
shoot-through circuitry monitors the PHASE and UGATE C BOOT_CAP  --------------------------------------
V BOOT_CAP
voltages during a PWM falling edge and the subsequent (EQ. 16)
UGATE turn-off. If either the UGATE falls to less than 1.75V
Q G1  PVCC
above the PHASE or the PHASE falls to less than +0.8V, the Q GATE = ----------------------------------  N Q1
LGATE is released to turn-on. V GS1
LGATE DETECT Gate Drive Voltage Versatility

If the DRSEL pin is tied to VCC through a 50k resistor, the The ISL6312 provides the user flexibility in choosing the
LGATE Detect adaptive deadtime control technique is selected. gate drive voltage for efficiency optimization. The controller
For the LGATE detect scheme, during turn-off of the lower ties the upper and lower drive rails together. Simply applying
MOSFET, the LGATE voltage is monitored until it reaches a voltage from 5V up to 12V on PVCC sets both gate drive
1.75V. At this time the UGATE is released to rise. rail voltages simultaneously.
FN9289 Rev 6.00 Page 21 of 35

February 1, 2011
ISL6312
Initialization In order for the ISL6312 to begin operation, PVCC1 is the

only pin that is required to have a voltage applied that
Prior to initialization, proper conditions must exist on the EN,
exceeds POR. However, for 2 or 3-phase operation
VCC, PVCC and the VID pins. When the conditions are met, PVCC2 and PVCC3 must also exceed the POR
the controller begins soft-start. Once the output voltage is threshold. Hysteresis between the rising and falling
within the proper window of operation, the controller asserts thresholds assure that once enabled, the ISL6312 will not
PGOOD. inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 6).
ISL6312 INTERNAL CIRCUIT EXTERNAL CIRCUIT
For Intel VR10, VR11 and AMD 6-bit modes of operation
VCC these are the only conditions that must be met for the
controller to immediately begin the soft-start sequence. If
PVCC1 running in AMD 5-bit mode of operation there is one more
+12V condition that must be met:
POR
CIRCUIT
5. The VID code must not be 11111 in AMD 5-bit mode. This
ENABLE
COMPARATOR
10.7k code signals the controller that no load is present. The
controller will not allow soft-start to begin if this VID code
EN
+ is present on the VID pins.
- Once all of these conditions are met the controller will begin
1.40k
the soft-start sequence and will ramp the output voltage up
0.85V to the user designated level.
Intel Soft-Start
+ EN_PH4
The soft-start function allows the converter to bring up the
SOFT-START - output voltage in a controlled fashion, resulting in a linear
AND
ramp-up. The soft-start sequence for the Intel modes of
FAULT LOGIC
1.21V operation is slightly different then the AMD soft-start
sequence.
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION For the Intel VR10 and VR11 modes of operation, the
soft-start sequence if composed of four periods, as shown in
Enable and Disable Figure 11. Once the ISL6312 is released from shutdown and
While in shutdown mode, the PWM outputs are held in a soft-start begins (as described in “Enable and Disable” on
high-impedance state to assure the drivers remain off. The page 22), the controller will have fixed delay period TD1.
following input conditions must be met, for both Intel and After this delay period, the VR will begin first soft-start ramp
AMD modes of operation, before the ISL6312 is released until the output voltage reaches 1.1V VBOOT voltage. Then,
from shutdown mode to begin the soft-start start-up the controller will regulate the VR voltage at 1.1V for another
sequence: fixed period TD3. At the end of TD3 period, ISL6312 will
read the VID signals. If the VID code is valid, ISL6312 will
1. The bias voltage applied at VCC must reach the internal initiate the second soft-start ramp until the output voltage
power-on reset (POR) rising threshold. Once this
reaches the VID voltage plus/minus any offset or droop
threshold is reached, proper operation of all aspects of
voltage.
the ISL6312 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the The soft-start time is the sum of the 4 periods as shown in
ISL6312 will not inadvertently turn off unless the bias Equation 17.
voltage drops substantially (see “Electrical
Specifications” on page 6). T SS = TD1 + TD2 + TD3 + TD4 (EQ. 17)
2. The voltage on EN must be above 0.85V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6312 in shutdown until the voltage at EN
rises above 0.85V. The enable comparator has 110mV of
hysteresis to prevent bounce.
3. The voltage on the EN_PH4 pin must be above 1.21V.
The EN_PH4 input allows for power sequencing between
the controller and the external driver.
4. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
FN9289 Rev 6.00 Page 22 of 35

February 1, 2011
ISL6312
.
1 V VID
TDB = --------------------------   --------------------- (EQ. 20)
3  0.00625
330  10
VOUT, 500mV/DIV
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TDC. The typical value
for TDC can range between 1.5ms and 3.0ms.
TD1 TD2 TD3 TD4 TD5
VOUT, 500mV/DIV
EN_VTT
PGOOD
TDA TDB TDC
500µs/DIV
FIGURE 11. SOFT-START WAVEFORMS
EN_VTT
TD1 is a fixed delay with the typical value as 1.40ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
PGOOD
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86µs. 500µs/DIV
During TD2 and TD4, ISL6312 digitally controls the DAC FIGURE 12. SOFT-START WAVEFORMS
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which Pre-Biased Soft-Start
is defined by the resistor RSS from SS pin to GND. The The ISL6312 also has the ability to start up into a
second soft-start ramp time TD2 and TD4 can be calculated pre-charged output, without causing any unnecessary
based on Equations 18 and 19: disturbance. The FB pin is monitored during soft-start, and
1.1  R SS should it be higher than the equivalent internal ramping
TD2 = ------------------------  s  (EQ. 18)
6.25  25 reference voltage, the output drives hold both MOSFETs off.
 V VID – 1.1   R SS OUTPUT PRECHARGED

TD4 = ----------------------------------------------------  s  (EQ. 19) ABOVE DAC LEVEL
6.25  25
For example, when VID is set to 1.5V and the RSS is set at
OUTPUT PRECHARGED
100k, the first soft-start ramp time TD2 will be 704µs and BELOW DAC LEVEL
the second soft-start ramp time TD4 will be 256µs.
NOTE: If the SS pin is grounded, the soft-start ramp in TD2
and TD4 will be defaulted to a 6.25mV step frequency of GND> VOUT (0.5V/DIV)
330kHz.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TD5. The typical value GND> EN (5V/DIV)
for TD5 is 440µs.

T1 T2 T3
AMD Soft-Start
FIGURE 13. SOFT-START WAVEFORMS FOR ISL6312-BASED
For the AMD 5-bit and 6-bit modes of operation, the MULTIPHASE CONVERTER
soft-start sequence is composed of three periods, as shown
in Figure 12. At the beginning of soft-start, the VID code is Once the internal ramping reference exceeds the FB pin
immediately obtained from the VID pins, followed by a fixed potential, the output drives are enabled, allowing the output
delay period TDA. After this delay period the ISL6312 will to ramp from the pre-charged level to the final level dictated
begin ramping the output voltage to the desired DAC level at by the DAC setting. Should the output be pre-charged to a
a fixed rate of 6.25mV per step, with a stepping frequency of level exceeding the DAC setting, the output drives are
330kHz. The amount of time required to ramp the output enabled at the end of the soft-start period, leading to an
voltage to the final DAC voltage is referred to as TDB, and abrupt correction in the output voltage down to the DAC-set
can be calculated as shown in Equation 20: level.
FN9289 Rev 6.00 Page 23 of 35

February 1, 2011
ISL6312
Fault Monitoring and Protection Overvoltage Protection

The ISL6312 actively monitors output voltage and current to The ISL6312 constantly monitors the sensed output voltage
detect fault conditions. Fault monitors trigger protective on the VDIFF pin to detect if an overvoltage event occurs.
measures to prevent damage to a microprocessor load. One When the output voltage rises above the OVP trip level
common power good indicator is provided for linking to actions are taken by the ISL6312 to protect the
external system monitors. The schematic in Figure 14 microprocessor load. The overvoltage protection trip level
outlines the interaction between the fault monitors and the changes depending on what mode of operation the controller
power good signal. is in and what state the OVPSEL and VRSEL pins are in.
Tables 6 and 7 list what the OVP trip levels are under all
conditions.
- 170µA At the inception of an overvoltage event, LGATE1, LGATE2
OCL
and LGATE3 are commanded high, PWM4 is commanded
+ I1
low, and the PGOOD signal is driven low. This turns on the
REPEAT FOR
VDAC EACH CHANNEL
all of the lower MOSFETs and pulls the output voltage below
a level that might cause damage to the load. The LGATE
VRSEL
125µA outputs remain high and PWM4 remains low until VDIFF falls
-
+175mV,
OCP 100mV below the OVP threshold that tripped the overvoltage
+250mV,
+350mV + IAVG protection circuitry. The ISL6312 will continue to protect the
OVPSEL load in this fashion as long as the overvoltage condition
recurs. Once an overvoltage condition ends the ISL6312
SOFT-START, FAULT
AND CONTROL LOGIC
latches off, and must be reset by toggling EN, or through
POR, before a soft-start can be reinitiated.
VOVP
TABLE 6. INTEL VR10 AND VR11 OVP THRESHOLDS
MODE OF OVPSEL PIN OPEN OVPSEL PIN TIED

-
OV OPERATION OR TIED TO GND TO VCC
VSEN
+ Soft-Start 1.280V and 1.280V and
+ PGOOD
x1 (TD1 and TD2) VDAC + 175mV VDAC + 350mV
- - (higher of the two) (higher of the two)
RGND UV
+ Soft-Start VDAC + 175mV VDAC + 350mV
(TD3 and TD4)
VDIFF Normal Operation VDAC + 175mV VDAC + 350mV

0.60 x DAC ISL6312 INTERNAL CIRCUITRY
TABLE 7. AMD OVP THRESHOLDS
FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY MODE OF OVPSEL PIN OPEN OVPSEL PIN TIED
OPERATION OR TIED TO GND TO VCC
Power Good Signal
Soft-Start 2.200V and 2.200V and
The power good pin (PGOOD) is an open-drain logic output VDAC + 250mV VDAC + 350mV
that signals whether or not the ISL6312 is regulating the (higher of the two) (higher of the two)
output voltage within the proper levels, and whether any fault Normal Operation VDAC + 250mV VDAC + 350mV
conditions exist. This pin should be tied to a +5V source
through a resistor.
One exception that overrides the overvoltage protection
During shutdown and soft-start PGOOD pulls low and circuitry is a dynamic VID transition in AMD modes of
releases high after a successful soft-start and the output operation. If a new VID code is detected during normal
voltage is operating between the undervoltage and operation, the OVP protection circuitry is disabled from the
overvoltage limits. PGOOD transitions low when an beginning of the dynamic VID transition, until 50µs after the
undervoltage, overvoltage, or overcurrent condition is internal DAC reaches the final VID setting. This is the only
detected or when the controller is disabled by a reset from time during operation of the ISL6312 that the OVP circuitry is
EN, EN_PH4, POR, or one of the no-CPU VID codes. In the not active.
event of an overvoltage or overcurrent condition, the
controller latches off and PGOOD will not return high until Pre-POR Overvoltage Protection
after a successful soft-start. In the case of an undervoltage Prior to PVCC and VCC exceeding their POR levels, the
event, PGOOD will return high when the output voltage ISL6312 is designed to protect the load from any overvoltage
returns to within the undervoltage. events that may occur. This is accomplished by means of an
internal 10k resistor tied from PHASE to LGATE, which
FN9289 Rev 6.00 Page 24 of 35

February 1, 2011
ISL6312
turns on the lower MOSFET to control the output voltage until

–6
the overvoltage event ceases or the input power supply cuts  125  10  R ISEN  N  R 1 + R 2
I OCP =  ----------------------------------------------------------   --------------------- (EQ. 22)
off. For complete protection, the low side MOSFET should  DCR   R2 
have a gate threshold well below the maximum voltage rating
I OCP  I OCP min
of the load/microprocessor.
The overcurrent trip level of the ISL6312 cannot be set any
In the event that during normal operation the PVCC or VCC lower then the IOCP,min level calculated above. If an
voltage falls back below the POR threshold, the pre-POR overcurrent trip level lower then IOCP,min is desired, then the
overvoltage protection circuitry reactivates to protect from any ISL6312A should be used in the place of the ISL6312.
more pre-POR overvoltage events.
At the beginning of overcurrent shutdown, the controller sets all
Undervoltage Detection of the UGATE and LGATE signals low, puts PWM4 in a high-
The undervoltage threshold is set at 60% of the VID code. impedance state, and forces PGOOD low. This turns off all of
When the output voltage (VSEN-RGND) is below the the upper and lower MOSFETs. The system remains in this
undervoltage threshold, PGOOD gets pulled low. No other state for fixed period of 12ms. If the controller is still enabled at
action is taken by the controller. PGOOD will return high if the the end of this wait period, it will attempt a soft-start. If the fault
output voltage rises above 70% of the VID code. remains, the trip-retry cycles will continue indefinitely until
either the controller is disabled or the fault is cleared. Note that
Open Sense Line Prevention the energy delivered during trip-retry cycling is much less than
In the case that either of the remote sense lines, VSEN or during full-load operation, so there is no thermal hazard.
GND, become open, the ISL6312 is designed to prevent the
controller from regulating. This is accomplished by means of a
small 5µA pull-up current on VSEN, and a pull-down current on
OUTPUT CURRENT, 50A/DIV
RGND. If the sense lines are opened at any time, the voltage
difference between VSEN and RGND will increase until an
overvoltage event occurs, at which point overvoltage protection
activates and the controller stops regulating. The ISL6312 will
be latched off and cannot be restarted until the controller is reset. 0A
Overcurrent Protection
The ISL6312 takes advantage of the proportionality between OUTPUT VOLTAGE,
the load current and the average current, IAVG, to detect an 500mV/DIV
overcurrent condition. See “Continuous Current Sampling” on

page 12 for more detail on how the average current is
measured. The average current is continually compared with a 0V
3ms/DIV
constant 125µA OCP reference current as shown in Figure 14.
FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE
Once the average current exceeds the OCP reference current,
a comparator triggers the converter to begin overcurrent
protection procedures. Individual Channel Overcurrent Limiting
The ISL6312 has the ability to limit the current in each
This method for detecting overcurrent events limits the
individual channel without shutting down the entire regulator.
minimum overcurrent trip threshold because of the fact the
This is accomplished by continuously comparing the sensed
ISL6312 uses set internal RISEN current sense resistors. The
currents of each channel with a constant 170A OCL reference
minimum overcurrent trip threshold is dictated by the DCR of
current as shown in Figure 14. If a channel’s individual sensed
the inductors and the number of active channels. To calculate
current exceeds this OCL limit, the UGATE signal of that
the minimum overcurrent trip level, IOCP,min, use Equation 21,
channel is immediately forced low, and the LGATE signal is
where N is the number of active channels, DCR is the
forced high. This turns off the upper MOSFET(s), turns on the
individual inductor’s DCR, and RISEN is the 300 internal
lower MOSFET(s), and stops the rise of current in that
current sense resistor.
channel, forcing the current in the channel to decrease. That
125  10  R ISEN  N
–6 channel’s UGATE signal will not be able to return high until the
I OCP min = ---------------------------------------------------------
- (EQ. 21)
DCR sensed channel current falls back below the 170µA reference.
If the desired overcurrent trip level is greater then the minimum

overcurrent trip level, IOCP,min, then the resistor divider R-C
circuit around the inductor shown in Figure 5 should be used to
set the desired trip level.
FN9289 Rev 6.00 Page 25 of 35

February 1, 2011
ISL6312
General Design Guide The total maximum power dissipated in each lower MOSFET is
approximated by the summation of PLOW,1 and PLOW,2.
This design guide is intended to provide a high-level explanation
of the steps necessary to create a multiphase power converter. It UPPER MOSFET POWER CALCULATION
is assumed that the reader is familiar with many of the basic skills In addition to rDS(ON) losses, a large portion of the
and techniques referenced below. In addition to this guide, Intersil upper-MOSFET losses are due to currents conducted across
provides complete reference designs that include schematics, the input voltage (VIN) during switching. Since a substantially
bills of materials, and example board layouts for all common higher portion of the upper-MOSFET losses are dependent on
microprocessor applications. switching frequency, the power calculation is more complex.
Power Stages Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times, the
The first step in designing a multiphase converter is to
lower-MOSFET body-diode reverse-recovery charge, Qrr, and
determine the number of phases. This determination depends
the upper MOSFET rDS(ON) conduction loss.
heavily on the cost analysis which in turn depends on system
constraints that differ from one design to the next. Principally, When the upper MOSFET turns off, the lower MOSFET does
the designer will be concerned with whether components can not conduct any portion of the inductor current until the voltage
be mounted on both sides of the circuit board, whether at the phase node falls below ground. Once the lower
through-hole components are permitted, the total board space MOSFET begins conducting, the current in the upper MOSFET
available for power-supply circuitry, and the maximum amount falls to zero as the current in the lower MOSFET ramps up to
of load current. Generally speaking, the most economical assume the full inductor current. In Equation 25, the required
solutions are those in which each phase handles between 25A time for this commutation is t1 and the approximated
and 30A. All surface-mount designs will tend toward the lower associated power loss is PUP,1.
end of this current range. If through-hole MOSFETs and
I M I PP  t 1 
inductors can be used, higher per-phase currents are possible. P UP,1  V IN   ----- -   ----   f (EQ. 25)
 N- + --------
2   2 S
In cases where board space is the limiting constraint, current
can be pushed as high as 40A per phase, but these designs
require heat sinks and forced air to cool the MOSFETs, At turn on, the upper MOSFET begins to conduct and this
inductors and heat-dissipating surfaces. transition occurs over a time t2. In Equation 26, the
approximate power loss is PUP,2.
MOSFETS
The choice of MOSFETs depends on the current each MOSFET  I M I PP  t 2 
P UP, 2  V IN   -----
- – ---------   ----   f S (EQ. 26)
will be required to conduct, the switching frequency, the N 2   2
capability of the MOSFETs to dissipate heat, and the availability
and nature of heat sinking and air flow. A third component involves the lower MOSFET reverse-
LOWER MOSFET POWER CALCULATION recovery charge, Qrr. Since the inductor current has fully
commutated to the upper MOSFET before the lower-MOSFET
The calculation for power loss in the lower MOSFET is simple,
body diode can recover all of Qrr, it is conducted through the
since virtually all of the loss in the lower MOSFET is due to
upper MOSFET across VIN. The power dissipated as a result
current conducted through the channel resistance (rDS(ON)). In
is PUP,3.
Equation 23, IM is the maximum continuous output current, IPP
is the peak-to-peak inductor current (see Equation 1), and d is P UP,3 = V IN  Q rr  f S (EQ. 27)
the duty cycle (VOUT/VIN).
 I M 2 I L, 2PP   1 – d  (EQ. 23)

Finally, the resistive part of the upper MOSFET is given in
P LOW 1 = r DS  ON    -----
-   1 – d  + ------------------------------------- Equation 28 as PUP,4.
 N 12
2 2
 I M I PP
An additional term can be added to the lower-MOSFET loss P UP,4  r DS  ON   d   -----
- + ---------- (EQ. 28)
 N 12
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the lower-
MOSFET body diode. This term is dependent on the diode
forward voltage at IM, VD(ON), the switching frequency, fS, and
the length of dead times, td1 and td2, at the beginning and the
end of the lower-MOSFET conduction interval respectively.
 I M I PP I 
P LOW 2 = V D  ON   f S   ------  M I PP  t (EQ. 24)
+ ----------  t d1 +  ------ – ---------
- d2
N 2  N 2 
FN9289 Rev 6.00 Page 26 of 35

February 1, 2011
ISL6312
The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results from PVCC BOOT
Equations 25, 26, 27 and 28. Since the power equations D
depend on MOSFET parameters, choosing the correct
CGD
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and RHI1 G
UGATE
CDS
different switching frequencies. RLO1 RGI1
RG1
Package Power Dissipation CGS
Q1
When choosing MOSFETs it is important to consider the S
amount of power being dissipated in the integrated drivers
PHASE
located in the controller. Since there are a total of three drivers
in the controller package, the total power dissipated by all three FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired PVCC

application is critical to ensure safe operation. Exceeding the D
maximum allowable power dissipation level will push the IC
CGD
beyond the maximum recommended operating junction
RHI2 G
temperature of +125°C. The maximum allowable IC power LGATE CDS
dissipation for the 7x7 QFN package is approximately 3.5W at RLO2 RG2 RGI2
room temperature. See “Layout Considerations” on page 32 for CGS
thermal transfer improvement suggestions. Q2
S
When designing the ISL6312 into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
MOSFETs. The total gate drive power losses, PQg_TOT, due to
the gate charge of MOSFETs and the integrated driver’s The total gate drive power losses are dissipated among the
internal circuitry and their corresponding average driver current resistive components along the transition path and in the
can be estimated with Equations 29 and 30, respectively. bootstrap diode. The portion of the total power dissipated in the
controller itself is the power dissipated in the upper drive path
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q  VCC (EQ. 29)
resistance, PDR_UP, the lower drive path resistance, PDR_UP,
and in the boot strap diode, PBOOT. The rest of the power will
3 be dissipated by the external gate resistors (RG1 and RG2) and
P Qg_Q1 = ---  Q G1  PVCC  F SW  N Q1  N PHASE
2 the internal gate resistors (RGI1 and RGI2) of the MOSFETs.
Figures 16 and 17 show the typical upper and lower gate
P Qg_Q2 = Q G2  PVCC  F SW  N Q2  N PHASE drives turn-on transition path. The total power dissipation in the
controller itself, PDR, can be roughly estimated as:
(EQ. 30) P DR = P DR_UP + P DR_LOW + P BOOT +  I Q  VCC 

3 (EQ. 31)
I DR =  ---  Q G1  N + Q G2  N Q2  N PHASE  F SW + I Q
2 Q1  P Qg_Q1
P BOOT = ---------------------
3
In Equations 29 and 30, PQg_Q1 is the total upper gate drive  R HI1 R LO1  P Qg_Q1
power loss and PQg_Q2 is the total lower gate drive power P DR_UP =  -------------------------------------- + ----------------------------------------  ---------------------
 R HI1 + R EXT1 R LO1 + R EXT1 3
loss; the gate charge (QG1 and QG2) is defined at the
particular gate to source drive voltage PVCC in the  R HI2 R LO2  P Qg_Q2
P DR_LOW =  -------------------------------------- + ----------------------------------------  ---------------------
corresponding MOSFET data sheet; IQ is the driver total  R HI2 + R EXT2 R LO2 + R EXT2 2
quiescent current with no load at both drive outputs; NQ1 and
NQ2 are the number of upper and lower MOSFETs per phase, R GI1 R GI2
R EXT1 = R G1 + ------------- R EXT2 = R G2 + -------------
respectively; NPHASE is the number of active phases. The N Q1 N Q2
IQ*VCC product is the quiescent power of the controller without
capacitive load and is typically 75mW at 300kHz.
FN9289 Rev 6.00 Page 27 of 35

February 1, 2011
ISL6312
Inductor DCR Current Sensing Component 2. Plug the inductor L and DCR component values, and the
Selection value for C1 chosen in step 1, into Equation 33 to calculate
the value for R1.
The ISL6312 senses each individual channel’s inductor current
by detecting the voltage across the output inductor DCR of that L I OCP = I OCP min (EQ. 33)
R 1 = -------------------------
channel (as described in the “Continuous Current Sampling” DCR  C 1
on page 12). As Figure 18 illustrates, an R-C network is
required to accurately sense the inductor DCR voltage and 3. Resistor R2 should be left unpopulated.
convert this information into a current, which is proportional to If the desired overcurrent trip level, IOCP, is greater then the
the total output current. The time constant of this R-C network minimum overcurrent trip level, IOCP,min, then a resistor divider
must match the time constant of the inductor L/DCR. R-C circuit should be used to set the desired trip level. Follow
the steps below to choose the component values for the
VIN
I
L resistor divider R-C current sensing network:
UGATE(n)
1. Choose an arbitrary value for C1. The recommended value
L
MOSFET DCR VOUT is 0.1F.
DRIVER LGATE(n) INDUCTOR COUT 2. Plug the inductor L and DCR component values, the value
VL(s) - for C1 chosen in step 1, the number of active channels N,
+
and the desired overcurrent protection level IOCP into

VC(s) -
+
Equations 34 and 35 to calculate the values for R1 and R2.

R1 C1 L  I OCP
R 1 = --------------------------------------
- I OCP  I OCP min (EQ. 34)
C 1  0.0375  N
R2*
ISL6312 INTERNAL CIRCUIT
L  I OCP
R 2 = ---------------------------------------------------------------------------------
- (EQ. 35)
C 1   I OCP  DCR – 0.0375  N 
In
Due to errors in the inductance or DCR it may be necessary to
adjust the value of R1 and R2 to match the time constants
SAMPLE
correctly. The effects of time constant mismatch can be seen in
+ the form of droop overshoot or undershoot during the initial
ISEN-(n)
VC(s)
-
load transient spike, as shown in Figure 19. Follow the steps
+
-
RISEN ISEN+(n) below to ensure the R-C and inductor L/DCR time constants
are matched accurately.
*R2 is OPTIONAL
ISEN
1. Capture a transient event with the oscilloscope set to about
L/DCR/2 (sec/div). For example, with L = 1H and DCR =
FIGURE 18. DCR SENSING CONFIGURATION 1m, set the oscilloscope to 500s/div.
2. Record V1 and V2 as shown in Figure 19.
The R-C network across the inductor also sets the overcurrent
trip threshold for the regulator. Before the R-C components can
be selected, the desired overcurrent protection level should be
chosen. The minimum overcurrent trip threshold the controller
can support is dictated by the DCR of the inductors and the
number of active channels. To calculate the minimum V2
overcurrent trip level, IOCP,min, use Equation 32, where N is V1
the number of active channels, and DCR is the individual VOUT
inductor’s DCR.
0.0375  N (EQ. 32)
I OCP min = ---------------------------
DCR
ITRAN
The overcurrent trip level of the ISL6312 cannot be set any
I
lower then the IOCP,min level calculated above. If the
minimum overcurrent trip level is desired, follow the steps
below to choose the component values for the R-C current
sensing network:
1. Choose an arbitrary value for C1. The recommended value FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
is 0.1µF.
FN9289 Rev 6.00 Page 28 of 35

February 1, 2011
ISL6312
3. Select new values, R1,NEW and R2,NEW, for the time COMPENSATION WITH LOAD-LINE REGULATION
constant resistors based on the original values, R1,OLD and The load-line regulated converter behaves in a similar manner
R2,OLD, using Equations 36 and 37.
to a peak current mode controller because the two poles at the
V 1 output filter L-C resonant frequency split with the introduction
R 1 NEW = R 1 OLD  ---------- (EQ. 36)
V 2 of current information into the control loop. The final location of
these poles is determined by the system function, the gain of
V 1
R 2 NEW = R 2 OLD  ---------- (EQ. 37) the current signal, and the value of the compensation
V 2 components, RC and CC.
C2 (OPTIONAL)
4. Replace R1 and R2 with the new values and check to see
that the error is corrected. Repeat the procedure if
necessary. CC
RC
COMP
Loadline Regulation Resistor
If loadline regulation is desired, the IDROOP pin should be
FB
shorted to the FB pin in order for the internal average sense
current to flow out across the loadline regulation resistor, ISL6312
IDROOP
labeled RFB in Figure 6. This resistor’s value sets the desired RFB
loadline required for the application. The desired loadline,
VDIFF
RLL, can be calculated by Equation 38 where VDROOP is the
desired droop voltage at the full load current IFL.
V DROOP FIGURE 20. COMPENSATION CONFIGURATION FOR
R LL = ------------------------
- (EQ. 38) LOAD-LINE REGULATED ISL6312 CIRCUIT
I FL
Since the system poles and zero are affected by the values of
Based on the desired loadline, the loadline regulation resistor, the components that are meant to compensate them, the
RFB, can be calculated from Equation 39 or Equation 40, solution to the system equation becomes fairly complicated.
depending on the R-C current sense circuitry being employed. Fortunately, there is a simple approximation that comes very
If a basic R-C sense circuit consisting of C1 and R1 is being close to an optimal solution. Treating the system as though it
used, use Equation 39. If a resistor divider R-C sense circuit were a voltage-mode regulator, by compensating the L-C poles
consisting of R1, R2, and C1 is being used, use Equation 40. and the ESR zero of the voltage mode approximation, yields a
solution that is always stable with very close to ideal transient
R LL  N  300
R FB = ---------------------------------
- (EQ. 39) performance.
DCR
Select a target bandwidth for the compensated system, f0. The
R LL  N  300   R 1 + R 2  target bandwidth must be large enough to assure adequate
R FB = ---------------------------------------------------------------- (EQ. 40) transient performance, but smaller than 1/3 of the per-channel
DCR  R 2
switching frequency. The values of the compensation
components depend on the relationships of f0 to the L-C pole
In Equations 39 and 40, RLL is the loadline resistance; N is the
frequency and the ESR zero frequency. For each of the
number of active channels; DCR is the DCR of the individual
following three, there is a separate set of equations for the
output inductors; and R1 and R2 are the current sense R-C
compensation components.
resistors.
In Equation 41, L is the per-channel filter inductance divided by
If no loadline regulation is required, the IDROOP pin should be
the number of active channels; C is the sum total of all output
left open and not connected to anything. To choose the value
capacitors; ESR is the equivalent series resistance of the bulk
for RFB in this situation, please refer to the “COMPENSATION
output filter capacitance; and VPP is the peak-to-peak
WITHOUT LOAD-LINE REGULATION” on page 30.
sawtooth signal amplitude as described in the “Electrical
Compensation Specifications” on page 6.
The two opposing goals of compensating the voltage regulator Once selected, the compensation values in Equation 41
are stability and speed. Depending on whether the regulator assure a stable converter with reasonable transient
employs the optional load-line regulation as described in Load- performance. In most cases, transient performance can be
Line Regulation, there are two distinct methods for achieving improved by making adjustments to RC. Slowly increase the
these goals. value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equation 41 unless some performance issue is noted.
FN9289 Rev 6.00 Page 29 of 35

February 1, 2011
ISL6312
C2
1
Case 1: -------------------------------- > f 0
2 LC
RC CC
2    f 0  V pp  L  C COMP
R C = R FB  --------------------------------------------------------
0.66  V IN
0.66  V IN FB
C C = ---------------------------------------------------
- C1
2    V PP  R FB  f 0
ISL6312
R1 RFB IDROOP
1 1
--------------------------------  f 0 < ------------------------------------
- VDIFF
Case 2: 2 LC 2    C  ESR
V PP   2    2  f 02  L  C
R C = R FB  ----------------------------------------------------------------- (EQ. 41) FIGURE 21. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
0.66  V IN
REGULATION
0.66  V IN
C C = -------------------------------------------------------------------------------------
 2    2  f 02  V PP  R FB  L  C In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
1
Equation 42, RFB is selected arbitrarily. The remaining
Case 3: f 0 > -------------------------------------
2    C  ESR compensation components are then selected according to
Equation 42.
2    f 0  V pp  L
R C = R FB  ---------------------------------------------
0.66  V IN  ESR In Equation 42, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
0.66  V IN  ESR  C
C C = ---------------------------------------------------------------- capacitors; ESR is the equivalent-series resistance of the bulk
2    V PP  R FB  f 0  L
output-filter capacitance; and VPP is the peak-to-peak
sawtooth signal amplitude as described in “Electrical
The optional capacitor C2, is sometimes needed to bypass
Specifications” on page 6.
noise away from the PWM comparator (see Figure 20). Keep a
position available for C2, and be prepared to install a C  ESR
R 1 = R FB  --------------------------------------------
high-frequency capacitor of between 22pF and 150pF in case L  C – C  ESR
any leading edge jitter problem is noted.
L  C – C  ESR
COMPENSATION WITHOUT LOAD-LINE REGULATION C 1 = --------------------------------------------
R FB
The non load-line regulated converter is accurately modeled as
a voltage-mode regulator with two poles at the L-C resonant 0.75  V IN
C 2 = ------------------------------------------------------------------------------------------------------------
-
frequency and a zero at the ESR frequency. A type III 2
 2     f 0  f HF   L  C   R FB  V  P – P 
controller, as shown in Figure 20, provides the necessary
compensation. 2
V PP   2  f 0  f HF  L  C  R FB
 
R C = ----------------------------------------------------------------------------------------
-
The first step is to choose the desired bandwidth, f0, of the
0.75  V   2    f HF  L  C – 1 
compensated system. Choose a frequency high enough to IN
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, fHF. This pole can be used for 0.75  V IN   2    f HF  L  C – 1 
C C = ------------------------------------------------------------------------------------------------------------
- (EQ. 42)
added noise rejection or to assure adequate attenuation at the  2    2  f 0  f HF   L  C   R FB  V  P – P 
error-amplifier high-order pole and zero frequencies. A good
general rule is to choose fHF = 10f0, but it can be higher if Output Filter Design
desired. Choosing fHF to be lower than 10f0 can cause The output inductors and the output capacitor bank together to
problems with too much phase shift below the system form a low-pass filter responsible for smoothing the pulsating
bandwidth. voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter limits the system transient response. The output
capacitors must supply or sink load current while the current in
the output inductors increases or decreases to meet the
demand.
FN9289 Rev 6.00 Page 30 of 35

February 1, 2011
ISL6312
In high-speed converters, the output capacitor bank is usually addresses the leading edge. Normally, the trailing edge
the most costly (and often the largest) part of the circuit. Output dictates the selection of L because duty cycles are usually less
filter design begins with minimizing the cost of this part of the than 50%. Nevertheless, both inequalities should be
circuit. The critical load parameters in choosing the output evaluated, and L should be selected based on the lower of the
capacitors are the maximum size of the load step, I, the load- two results. In each equation, L is the per-channel inductance,
current slew rate, di/dt, and the maximum allowable output- C is the total output capacitance, and N is the number of active
voltage deviation under transient loading, VMAX. Capacitors channels.
are characterized according to their capacitance, ESR, and ESL
2  N  C  VO
(equivalent series inductance). L  ---------------------------------  V MAX –  I  ESR  (EQ. 45)
 I  2
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage drop 1.25  N  C-  V
L  ----------------------------   (EQ. 46)
 I  2 MAX –  I  ESR    V IN – V O
across the ESL. As the load current increases, the voltage
drop across the ESR increases linearly until the load current
reaches its final value. The capacitors selected must have Switching Frequency
sufficiently low ESL and ESR so that the total output-voltage There are a number of variables to consider when choosing
deviation is less than the allowable maximum. Neglecting the the switching frequency, as there are considerable effects on
contribution of inductor current and regulator response, the the upper MOSFET loss calculation. These effects are outlined
output voltage initially deviates by an amount: in “MOSFETs” on page 26, and they establish the upper limit
for the switching frequency. The lower limit is established by
di
V  ESL  ----- + ESR  I (EQ. 43) the requirement for fast transient response and small output-
dt voltage ripple as outlined in “COMPENSATION WITHOUT
LOAD-LINE REGULATION” on page 30. Choose the lowest
The filter capacitor must have sufficiently low ESL and ESR so switching frequency that allows the regulator to meet the
that V < VMAX. transient-response requirements.
Most capacitor solutions rely on a mixture of high frequency Switching frequency is determined by the selection of the
capacitors with relatively low capacitance in combination with frequency-setting resistor, RT. Figure 22 and Equation 47 are
bulk capacitors having high capacitance but limited high- provided to assist in selecting the correct value for RT.
frequency performance. Minimizing the ESL of the high- 10.61 –  1.035  log  f S    (EQ. 47)
R T = 10
frequency capacitors allows them to support the output voltage
as the current increases. Minimizing the ESR of the bulk
1000
capacitors allows them to supply the increased current with
less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of the
output-voltage ripple. As the bulk capacitors sink and source
the inductor AC ripple current (see “Interleaving” on page 10
RT (k)
and Equation 2), a voltage develops across the bulk capacitor 100
ESR equal to IC,PP (ESR). Thus, once the output capacitors

are selected, the maximum allowable ripple voltage,
VPP(MAX), determines the lower limit on the inductance.
V – N  V 
 IN OUT  V OUT 10
L  ESR  -------------------------------------------------------------------- (EQ. 44)
10 100 1k 10k
f S  V IN  V PP MAX 
SWITCHING FREQUENCY (Hz)
FIGURE 22. RT vs SWITCHING FREQUENCY

Since the capacitors are supplying a decreasing portion of the
Input Capacitor Selection
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output The input capacitors are responsible for sourcing the AC
inductors must be capable of assuming the entire load current component of the input current flowing into the upper
before the output voltage decreases more than VMAX. This MOSFETs. Their RMS current capacity must be sufficient to
places an upper limit on inductance. handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
Equation 45 gives the upper limit on L for the cases when the active phases.
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 46
FN9289 Rev 6.00 Page 31 of 35

February 1, 2011
ISL6312
0.3 0.3
IL(P-P) = 0 IL(P-P) = 0.5 IO
IL(P-P) = 0.25 IO IL(P-P) = 0.75 IO
INPUT-CAPACITOR CURRENT (IRMS/IO)

0.2 0.2
0.1 0.1
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0 0
0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (VO/VIN) DUTY CYCLE (VIN/VO)
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS
vs DUTY CYCLE FOR 4-PHASE CONVERTER CURRENT FOR 2-PHASE CONVERTER
For a four-phase design, use Figure 23 to determine the input-
Layout Considerations
capacitor RMS current requirement set by the duty cycle,
maximum sustained output current (IO), and the ratio of the MOSFETs switch very fast and efficiently. The speed with
peak-to-peak inductor current (IL(P-P)) to IO. Select a bulk which the current transitions from one device to another
capacitor with a ripple current rating which will minimize the causes voltage spikes across the interconnecting impedances
total number of input capacitors required to support the RMS and parasitic circuit elements. These voltage spikes can
current calculated. degrade efficiency, radiate noise into the circuit and lead to
device overvoltage stress. Careful component selection,
The voltage rating of the capacitors should also be at least 1.25x layout, and placement minimizes these voltage spikes.
greater than the maximum input voltage. Figures 24 and 25 Consider, as an example, the turnoff transition of the upper
provide the same input RMS current information for three-phase PWM MOSFET. Prior to turnoff, the upper MOSFET was
and two-phase designs respectively. Use the same approach for carrying channel current. During the turnoff, current stops
selecting the bulk capacitor type and number. flowing in the upper MOSFET and is picked up by the lower
0.3 MOSFET. Any inductance in the switched current path
IL(P-P) = 0 IL(P-P) = 0.5 IO
generates a large voltage spike during the switching interval.
IL(P-P) = 0.25 IO IL(P-P) = 0.75 IO

Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
0.2 magnitude of voltage spikes.
There are two sets of critical components in a DC/DC converter

using a ISL6312 controller. The power components are the
most critical because they switch large amounts of energy.
0.1 Next are small signal components that connect to sensitive
nodes or supply critical bypassing current and signal coupling.
The power components should be placed first, which include the

MOSFETs, input and output capacitors, and the inductors. It is
0 important to have a symmetrical layout for each power train,
0 0.2 0.4 0.6 0.8 1.0
preferably with the controller located equidistant from each.
DUTY CYCLE (VIN/VO)
Symmetrical layout allows heat to be dissipated equally across
FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER all power trains. Equidistant placement of the controller to the
first three power trains it controls through the integrated drivers
Low capacitance, high-frequency ceramic capacitors are needed helps keep the gate drive traces equally short, resulting in equal
in addition to the input bulk capacitors to suppress leading and trace impedances and similar drive capability of all sets of
falling edge voltage spikes. The spikes result from the high MOSFETs.
current slew rate produced by the upper MOSFET turn on and off.
Select low ESL ceramic capacitors and place one as close as When placing the MOSFETs try to keep the source of the upper
possible to each upper MOSFET drain to minimize board FETs and the drain of the lower FETs as close as thermally
parasitics and maximize suppression. possible. Input Bulk capacitors should be placed close to the
FN9289 Rev 6.00 Page 32 of 35

February 1, 2011
ISL6312
drain of the upper FETs and the source of the lower FETs. Routing UGATE, LGATE, and PHASE Traces
Locate the output inductors and output capacitors between the Great attention should be paid to routing the UGATE, LGATE,
MOSFETs and the load. The high-frequency input and output and PHASE traces since they drive the power train MOSFETs
decoupling capacitors (ceramic) should be placed as close as using short, high current pulses. It is important to size them as
practicable to the decoupling target, making use of the shortest large and as short as possible to reduce their overall
connection paths to any internal planes, such as vias to GND impedance and inductance. They should be sized to carry at
next or on the capacitor solder pad. least one ampere of current (0.02” to 0.05”). Going between
The critical small components include the bypass capacitors layers with vias should also be avoided, but if so, use two vias
for VCC and PVCC, and many of the components for interconnection when possible.
surrounding the controller including the feedback network Extra care should be given to the LGATE traces in particular
and current sense components. Locate the VCC/PVCC since keeping their impedance and inductance low helps to
bypass capacitors as close to the ISL6312 as possible. It is significantly reduce the possibility of shoot-through. It is also
especially important to locate the components associated important to route each channels UGATE and PHASE traces
with the feedback circuit close to their respective controller in as close proximity as possible to reduce their inductances.
pins, since they belong to a high-impedance circuit loop,
sensitive to EMI pick-up. Current Sense Component Placement and Trace
Routing
A multi-layer printed circuit board is recommended. Figure 26
One of the most critical aspects of the ISL6312 regulator
shows the connections of the critical components for the
layout is the placement of the inductor DCR current sense
converter. Note that capacitors CxxIN and CxxOUT could each
components and traces. The R-C current sense components
represent numerous physical capacitors. Dedicate one solid
must be placed as close to their respective ISEN+ and
layer, usually the one underneath the component side of the
ISEN- pins on the ISL6312 as possible.
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another The sense traces that connect the R-C sense components to
solid layer as a power plane and break this plane into smaller each side of the output inductors should be routed on the
islands of common voltage levels. Keep the metal runs from the bottom of the board, away from the noisy switching
PHASE terminal to output inductors short. The power plane components located on the top of the board. These traces
should support the input power and output power nodes. Use should be routed side by side, and they should be very thin
copper filled polygons on the top and bottom circuit layers for traces. It’s important to route these traces as far away from
the phase nodes. Use the remaining printed circuit layers for any other noisy traces or planes as possible. These traces
small signal wiring. should pick up as little noise as possible.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
GND pad of the ISL6312 to the ground plane with multiple
vias is recommended. This heat spreading allows the part to
achieve its full thermal potential. It is also recommended
that the controller be placed in a direct path of airflow if
possible to help thermally manage the part.
© Copyright Intersil Americas LLC 2006-2011. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9289 Rev 6.00 Page 33 of 35

February 1, 2011
ISL6312
C2 RFB LOCATE CLOSE TO IC KEY

(MINIMIZE CONNECTION PATH)
C1 HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
+12V
R1 ISLAND ON CIRCUIT PLANE LAYER
FB IDROOP VDIFF
VIA CONNECTION TO GROUND PLANE
COMP CBIN1
CBOOT1
VSEN BOOT1 LOCATE NEAR SWITCHING TRANSISTORS;
RGND (MINIMIZE CONNECTION PATH)
UGATE1
+5V
PHASE1
VCC
(CF1) R1 C1
ROFS LGATE1
OFS ISEN1-
ISEN1+
FS +12V
REF
RT PVCC1_2
CREF (CF2) CBIN2
CBOOT2
BOOT2
SS
UGATE2
RSS
PHASE2
(CHFOUT) CBOUT
R1 C1
LGATE2
OVPSEL
ISEN2- LOAD
ISL6312 ISEN2+
+12V
VID7
VID6 PVCC3
VID5 (CF2) CBIN3
LOCATE NEAR LOAD;
VID4 CBOOT3 (MINIMIZE CONNECTION
VID3 BOOT3 PATH)
VID2
UGATE3
VID1
VID0
PHASE3
VRSEL
R1 C1
PGOOD LGATE3
+12V
ISEN3-
ISEN3+
REN1
+12V
+12V
EN
CBIN4
REN2
BOOT
VCC UGATE
EN_PH4
PVCC
DRSEL PHASE
ISL6612
RDR
LGATE R1 C1
PWM4 PWM
GND
GND
ISEN4-
ISEN4+
FIGURE 26. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
FN9289 Rev 6.00 Page 34 of 35

February 1, 2011
ISL6312
Package Outline Drawing

L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 4/10
4X 5.5
7.00 A
B 44X 0.50 6
37 48 PIN #1 INDEX AREA
6
PIN 1 36 1
INDEX AREA
7.00
4. 30 ± 0 . 15
25 12
(4X) 0.15
24 13
0.10 M C A B
TOP VIEW 48X 0 . 40± 0 . 1
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C C
0 . 90 ± 0 . 1 BASE PLANE
( 6 . 80 TYP )
SEATING PLANE
0.08 C
( 4 . 30 ) SIDE VIEW
( 44X 0 . 5 )
C 0 . 2 REF 5
( 48X 0 . 23 )
( 48X 0 . 60 ) 0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN9289 Rev 6.00 Page 35 of 35

February 1, 2011

Four-Phase Buck PWM Controller With Integrated MOSFET Drivers For Intel VR10, VR11, and AMD Applications

Uploaded by

Copyright:

Available Formats

Four-Phase Buck PWM Controller With Integrated MOSFET Drivers For Intel VR10, VR11, and AMD Applications

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Four-Phase Buck PWM Controller With Integrated MOSFET Drivers For Intel VR10, VR11, and AMD Applications

Uploaded by

Copyright:

Available Formats

DATASHEET

The ISL6312 four-phase PWM control IC provides a Features

FN9289 Rev 6.00 Page 1 of 35

ISL6312 Integrated Driver Block Diagram

FN9289 Rev 6.00 Page 2 of 35

CH1 CH2 CH3 CH4

ISEN1- ISEN1+ ISEN2- ISEN2+ ISEN3- ISEN3+ ISEN4- ISEN4+ GND

FN9289 Rev 6.00 Page 3 of 35

Typical Application - ISL6312 (4-Phase)

FN9289 Rev 6.00 Page 4 of 35

Typical Application - ISL6312 with NTC Thermal Compensation (4-Phase)

VSEN BOOT1 PLACE IN

FN9289 Rev 6.00 Page 5 of 35

Absolute Maximum Ratings Thermal Information

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.

Input Bias Supply Current IVCC; EN = high 15 20 25 mA

Gate Drive Bias Current - PVCC1_2 Pin IPVCC1_2; EN = high 2 4.3 6 mA

Gate Drive Bias Current - PVCC3 Pin IPVCC3; EN = high 1 2.1 3 mA

VCC falling 3.75 3.88 4.00 V

Oscillator Ramp Amplitude, VPP (Note 5) - 1.50 - V

EN Rising Threshold - 0.85 - V

EN_PH4 Rising Threshold 1.160 1.210 1.250 V

COMP Shutdown Threshold COMP falling 0.1 0.2 0.3 V

REFERENCE AND DAC

System Accuracy (1.000V - 1.600V) -0.5 - 0.5 %

System Accuracy (0.600V - 1.000V) -1.0 - 1.0 %

System Accuracy (0.375V - 0.600V) -2.0 - 2.0 %

DAC Input High Voltage (VR10, VR11) 0.8 - - V

FN9289 Rev 6.00 Page 6 of 35

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

DAC Input Low Voltage (AMD) - - 0.6 V

DAC Input High Voltage (AMD) 1.0 - - V

DC Gain RL = 10k to ground, (Note 5) - 96 - dB

Gain-Bandwidth Product CL = 100pF, RL = 10k to ground, (Note 5) - 20 - MHz

Slew Rate CL = 100pF, Load = ±400mA, (Note 5) - 8 - V/s

Maximum Output Voltage Load = 1mA 3.90 4.20 - V

Soft-Start Ramp Rate VR10/VR11, RS = 100k - 1.563 - mV/µs

Adjustment Range of Soft-Start Ramp Rate (Note 5) 0.625 - 6.25 mV/µs

PWM Output Voltage LOW Threshold Iload = ±500µA - - 0.5 V

Current Sense Resistance, RISEN T = +25°C 297 300 303 

Dynamic VID change (Note NOTES:) 209.4 238 266.6 A

Undervoltage Threshold VSEN falling 55 60 65 %VID

Undervoltage Hysteresis VSEN rising - 10 - %VID

AMD 2.13 2.20 2.27 V

AMD, OVPSEL tied to ground, VSEN rising VDAC + VDAC + VDAC + V

Overvoltage Hysteresis VSEN falling - 100 - mV

SWITCHING TIME (Note 5)

FN9289 Rev 6.00 Page 7 of 35

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

UGATE Turn-On Non-Overlap tPDHUGATE; VPVCC = 12V, 3nF load, adaptive - 10 - ns

LGATE Turn-On Non-Overlap tPDHLGATE; VPVCC = 12V, 3nF load, adaptive - 10 - ns

GATE DRIVE RESISTANCE (Note 5)

OVER TEMPERATURE SHUTDOWN (Note 5)

Thermal Shutdown Setpoint - 160 - °C

Thermal Recovery Setpoint - 100 - °C

FN9289 Rev 6.00 Page 8 of 35

Functional Pin Descriptions FB and COMP

FN9289 Rev 6.00 Page 9 of 35

PHASE1, PHASE2, and PHASE3 Operation