DATASHEET

ISL6545, ISL6545A FN6305

5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller Rev 7.00
October 7, 2015

The ISL6545, ISL6545A makes simple work out of Features

implementing a complete control and protection scheme for a
DC/DC stepdown converter driving N-Channel MOSFETs in a • Operates from +5V or +12V Supply Voltage (for bias)
synchronous buck topology. Since it can work with either 5V or - 1.0V to 12V VIN Input Range (up to 20V possible with
12V supplies, this one IC can be used in a wide variety of restrictions; see Input Voltage Considerations)
applications within a system. The ISL6545, ISL6545A - 0.6V to VIN Output Range
(hereafter referred to as “ISL6545x”, except as needed) - Integrated Gate Drivers use VCC (5V to 12V)
integrates the control, gate drivers, output adjustment, - 0.6V Internal Reference; ±1.0% tolerance
monitoring and protection functions into a single 8 Ld SOIC or • Simple Single-Loop Control Design
10 Ld DFN package.
- Voltage-Mode PWM Control
The ISL6545x provides single feedback loop, voltage-mode - Drives N-Channel MOSFETs
control with fast transient response. The output voltage can be - Traditional Dual Edge Modulator
precisely regulated to as low as 0.6V, with a maximum
• Fast Transient Response
tolerance of ±1.0% over-temperature and line voltage
- High-Bandwidth Error Amplifier
variations. A selectable fixed frequency oscillator (ISL6545 for
300kHz; ISL6545A for 600kHz) reduces design complexity, - Full 0% to 100% Duty Cycle
while balancing typical application cost and efficiency. • Lossless, Programmable Overcurrent Protection
The error amplifier features a 20MHz gain-bandwidth - Uses Lower MOSFET’s rDS(ON)
product and 9V/µs slew rate which enables high converter • Small Converter Size in 8 Ld SOIC or 10 Ld DFN
bandwidth for fast transient performance. The resulting - 300kHz or 600kHz Fixed Frequency Oscillator
PWM duty cycles range from 0% to 100%. - Fixed Internal Soft-Start, Capable into a Pre-biased
Protection from overcurrent conditions is provided by Load
monitoring the rDS(ON) of the lower MOSFET to inhibit PWM - Integrated Boot Diode
operation appropriately. This approach simplifies the - Enable/Shutdown Function on COMP/SD Pin
implementation and improves efficiency by eliminating the - Output Current Sourcing and Sinking
need for a current sense resistor. • Pb-Free (RoHS Compliant)

Pinout Applications
ISL6545, ISL6545A
(8 LD SOIC) • Power Supplies for Microprocessors or Peripherals
TOP VIEW - PCs, Embedded Controllers, Memory Supplies
BOOT 1 8 PHASE
- DSP and Core Communications Processor Supplies
UGATE 2 7 COMP/SD • Subsystem Power Supplies
GND 3 6 FB - PCI, AGP; Graphics Cards; Digital TV
LGATE/OCSET 4 5 VCC - SSTL-2 and DDR/DDR2/DDR3 SDRAM Bus
Termination Supply
• Cable Modems, Set Top Boxes, and DSL Modems
ISL6545, ISL6545A
(10 LD 3x3 DFN) • Industrial Power Supplies; General Purpose Supplies
TOP VIEW
• 5V or 12V-Input DC/DC Regulators
BOOT 1 10 PHASE • Low-Voltage Distributed Power Supplies
UGATE 2 9 COMP/SD
N/C 3 GND 8 FB
GND 4 7 N/C
LGATE/OCSET 5 6 VCC

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October 7, 2015
ISL6545, ISL6545A
ISL6545, ISL6545A
*

Ordering Information
FIXED FREQUENCY
PART NUMBER OSCILLATOR TEMP. RANGE PACKAGE PKG.
(Notes 1, 2, 3) PART MARKING (kHz) (°C) (Pb-Free) DWG. #

ISL6545CBZ 6545 CBZ 300 0 to +70 8 Ld SOIC M8.15

ISL6545ACBZ 6545 ACBZ 600 0 to +70 8 Ld SOIC M8.15

ISL6545IBZ 6545 IBZ 300 -40 to +85 8 Ld SOIC M8.15

ISL6545AIBZ 6545 AIBZ 600 -40 to +85 8 Ld SOIC M8.15

ISL6545CRZ 545Z 300 0 to +70 10 Ld DFN L10.3x3C

ISL6545ACRZ 45AZ 600 0 to +70 10 Ld DFN L10.3x3C

ISL6545AIRZ 5ARZ 600 -40 to +85 10 Ld DFN L10.3x3C

NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6545, ISL6545A. For more information on MSL please see
techbrief TB363.

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ISL6545, ISL6545A
ISL6545, ISL6545A

Block Diagram
VCC

DBOOT
POR AND INTERNAL BOOT
SAMPLE + SOFT-START REGULATOR
AND -
OC UGATE
HOLD
COMPARATOR 5V int.

21.5µA PHASE
20k
ERROR PWM
TO AMP COMPARATOR INHIBIT
LGATE/OCSET 0.6V + GATE
- + CONTROL
- PWM LOGIC
VCC
FB
DIS
5V int. LGATE/OCSET
0.4V DIS
+
-
20A OSCILLATOR
COMP/SD
FIXED 300 (or 600)kHz

GND

Typical Application
VCC VIN
5V OR 12V 1V TO 12V

CBULK
CHF

VCC
CDCPL
5 BOOT
1 CBOOT
ISL6545, PHASE
8
COMP/SD ISL6545A
7 UGATE
2 LOUT
RF +VO

CI LGATE/OCSET
6 3 4 COUT
CF
FB GND ROCSET

Type II
ROFFSET compensation RS
shown

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ISL6545, ISL6545A
ISL6545, ISL6545A

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V Thermal Resistance JA (°C/W) JC (°C/W)
BOOT Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 36V SOIC Package (Note 4) . . . . . . . . . . . . . . 95 N/A
UGATE Voltage VUGATE . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V DFN Package (Notes 5, 6). . . . . . . . . . . . 44 5.5
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT +0.3V Maximum Junction Temperature
LGATE/OCSET Voltage, VLGATE/OCSET GND - 0.3V to VCC + 0.3V (Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
GND - 5V (<100ns Pulse Width, 2µJ) to VCC + 0.3V Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
PHASE Voltage, VPHASE . . . . . . . . . .GND - 0.3V to VBOOT + 0.3V Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND <36V) http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . . .15V
-0.3V to 16V (<10ns, 10µJ) Operating Conditions
Clamp Voltage, VBOOT - VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
Supply Voltage, VCC . . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V
FB, COMP/SD Voltage. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6V
Ambient Temperature Range
ESD Ratings
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV ISL6545C, ISL6545AC. . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6545I, ISL6545AI . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150V
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air, with “direct attach” features. See
Tech Brief TB379 for details.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications VCC = 12V, TJ = 0 to +85°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
VCC SUPPLY CURRENT
Input Bias Supply Current IVCC VCC = 12V; disabled 4 5.2 7 mA
POWER-ON RESET
Rising VCC POR Threshold VPOR 3.9 4.1 4.3 V
VCC POR Threshold Hysteresis 0.30 0.35 0.40 V
OSCILLATOR
Switching Frequency fOSC ISL6545C 270 300 330 kHz
ISL6545I 240 300 330 kHz
fOSC ISL6545AC 540 600 660 kHz
ISL6545AI 510 600 660 kHz
Ramp Amplitude VOSC 1.5 VP-P
REFERENCE
Reference Voltage Tolerance ISL6545C -1.0 - +1.0 %
ISL6545I -1.5 - +1.5 %
Nominal Reference Voltage VREF 0.600 V
ERROR AMPLIFIER
DC Gain GAIN 96 dB
Gain-Bandwidth Product GBWP 20 MHz
Slew Rate SR 9 V/µs
GATE DRIVERS
Upper Gate Source Impedance RUG-SRCh VCC = 14.5V; I = 50mA 3.0 
Upper Gate Sink Impedance RUG-SNKh VCC = 14.5V; I = 50mA 2.7 
Lower Gate Source Impedance RLG-SRCh VCC = 14.5V; I = 50mA 2.4 
Lower Gate Sink Impedance RLG-SNKh VCC = 14.5V; I = 50mA 2.0 

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ISL6545, ISL6545A

Electrical Specifications VCC = 12V, TJ = 0 to +85°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
Upper Gate Source Impedance RUG-SRCl VCC = 4.25V; I = 50mA 3.5 
Upper Gate Sink Impedance RUG-SNKl VCC = 4.25V; I = 50mA 2.7 
Lower Gate Source Impedance RLG-SRCl VCC = 4.25V; I = 50mA 2.75 
Lower Gate Sink Impedance RLG-SNKl VCC = 4.25V; I = 50mA 2.1 
PROTECTION/DISABLE
OCSET Current Source IOCSET ISL6545C; LGATE/OCSET = 0V 19.5 21.5 23.5 µA
ISL6545I; LGATE/OCSET = 0V 18.0 21.5 23.5 µA
Disable Threshold (COMP/SD pin) VDISABLE 0.375 0.400 0.425 V
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Functional Pin Description (SOIC, DFN) suitable to drive an N-channel MOSFET (equal to VCC minus
the on-chip BOOT diode voltage drop), with respect to PHASE.
VCC (SOIC Pin 5, DFN Pin 6)
This pin provides the bias supply for the ISL6545x, as well COMP/SD (SOIC Pin 7, DFN Pin 9)
as the lower MOSFET’s gate, and the BOOT voltage for the This is a multiplexed pin. During soft-start and normal converter
upper MOSFET’s gate. An internal 5V regulator will supply operation, this pin represents the output of the error amplifier.
bias if VCC rises above 6.5V (but the LGATE/OCSET and Use COMP/SD, in combination with the FB pin, to compensate
BOOT will still be sourced by VCC). Connect a well- the voltage-control feedback loop of the converter.
decoupled 5V or 12V supply to this pin. Pulling COMP/SD low (VDISABLE = 0.4V nominal) will
FB (SOIC Pin 6, DFN Pin 8) shut-down (disable) the controller, which causes the
oscillator to stop, the LGATE and UGATE outputs to be held
This pin is the inverting input of the internal error amplifier. Use
low, and the soft-start circuitry to re-arm. The external
FB, in combination with the COMP/SD pin, to compensate the
pull-down device will initially need to overcome up to 5mA of
voltage-control feedback loop of the converter. A resistor divider
COMP/SD output current. However, once the IC is disabled,
from the output to GND is used to set the regulation voltage.
the COMP output will also be disabled, so only a 20µA
GND (SOIC Pin 3, DFN Pin 4) current source will continue to draw current.
This pin represents the signal and power ground for the IC. When the pull-down device is released, the COMP/SD pin
Tie this pin to the ground island/plane through the lowest will start to rise, at a rate determined by the 20µA charging
impedance connection available. For the DFN package, up the capacitance on the COMP/SD pin. When the
Pin 4 MUST be connected for electrical GND; the metal pad COMP/SD pin rises above the VDISABLE trip point, the
under the package should also be connected to the GND ISL6545x will begin a new Initialization and soft-start cycle.
plane for thermal conductivity.
LGATE/OCSET (SOIC Pin 4, DFN Pin 5)
PHASE (SOIC Pin 8, DFN Pin 10)
Connect this pin to the gate of the lower MOSFET; it provides
Connect this pin to the source of the upper MOSFET, and the PWM-controlled gate drive (from VCC). This pin is also
the drain of the lower MOSFET. It is used as the sink for the monitored by the adaptive shoot-through protection circuitry to
UGATE driver, and to monitor the voltage drop across the determine when the lower MOSFET has turned off.
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry During a short period of time following Power-On Reset
to determine when the upper MOSFET has turned off. (POR) or shut-down release, this pin is also used to
determine the overcurrent threshold of the converter.
UGATE (SOIC Pin 2, DFN Pin 2) Connect a resistor (ROCSET) from this pin to GND. See
Connect this pin to the gate of upper MOSFET; it provides “Overcurrent Protection (OCP)” on page 7 for equations. An
the PWM-controlled gate drive. It is also monitored by the overcurrent trip cycles the soft-start function, after two
adaptive shoot-through protection circuitry to determine dummy soft-start time-outs. Some of the text describing the
when the upper MOSFET has turned off. LGATE function may leave off the OCSET part of the name,
when it is not relevant to the discussion.
BOOT (SOIC Pin 1, DFN Pin 1)
This pin provides ground referenced bias voltage to the upper N/C (DFN only; Pin 3, Pin 7)
MOSFET driver. A bootstrap circuit is used to create a voltage These two pins in the DFN package are No Connect.

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ISL6545, ISL6545A
ISL6545, ISL6545A

Functional Description soft-start operation is initiated, and the output voltage ramps
up between t4 and t5.
Initialization (POR and OCP Sampling)
Figure 1 shows a simplified timing diagram. The
LGATE
Power-On-Reset (POR) function continually monitors the STARTS
bias voltage at the VCC pin. Once the rising POR threshold SWITCHING
is exceeded (VPOR ~4V nominal), the POR function initiates
COMP/SD (0.25V/DIV)
the Overcurrent Protection (OCP) sample and hold
operation (while COMP/SD is ~1V). When the sampling is
complete, VOUT begins the soft-start ramp.
0.4V
If the COMP/SD pin is held low during power-up, that will just
delay the initialization until it is released, and the COMP/SD
LGATE/OCSET (0.25V/DIV) VOUT
voltage is above the VDISABLE trip point. (0.5V/DIV)

GND>
VCC (2V/DIV) 3.4ms 3.4ms 0 - 3.4ms 6.8ms

t0 t1 t2 t3 t4 t5
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION

Soft-Start and Pre-Biased Outputs

~4V POR
Functionally, the soft-start internally ramps the reference on
VOUT (1V/DIV)
the non-inverting terminal of the error amp from 0V to 0.6V in
COMP/SD (1V/DIV)
a nominal 6.8ms The output voltage will thus follow the
ramp, from zero to final value, in the same 6.8ms (the actual
ramp seen on the VOUT will be less than the nominal time,
GND> due to some initialization timing, between t3 and t4).

The ramp is created digitally, so there will be 64 small

FIGURE 1. POR AND SOFT-START OPERATION discrete steps. There is no simple way to change this ramp
rate externally, and it is the same for either frequency
Figure 2 shows a typical power-up sequence in more detail. version of the IC (300kHz or 600kHz).
The initialization starts at T0, when either VCC rises above
VPOR, or the COMP/SD pin is released (after POR). The After an initialization period (t3 to t4), the error amplifier
COMP/SD will be pulled up by an internal 20µA current (COMP/SD pin) is enabled, and begins to regulate the
source, but the timing will not begin until the COMP/SD converter’s output voltage during soft-start. The oscillator’s
exceeds the VDISABLE trip point (at t1). The external triangular waveform is compared to the ramping error
capacitance of the disabling device, as well as the amplifier voltage. This generates PHASE pulses of
compensation capacitors, will determine how quickly the increasing width that charge the output capacitors. When the
20µA current source will charge the COMP/SD pin. With internally generated soft-start voltage exceeds the reference
typical values, it should add a small delay compared to the voltage (0.6V), the soft-start is complete, and the output
soft-start times. The COMP/SD will continue to ramp to ~1V. should be in regulation at the expected voltage. This method
provides a rapid and controlled output voltage rise; there is
From t1, there is a nominal 6.8ms delay, which allows the no large inrush current charging the output capacitors. The
VCC pin to exceed 6.5V (if rising up towards 12V), so that entire start-up sequence from POR typically takes up to
the internal bias regulator can turn on cleanly. At the same 17ms; up to 10.2ms for the delay and OCP sample, and
time, the LGATE/OCSET pin is initialized, by disabling the 6.8ms for the soft-start ramp.
LGATE driver and drawing IOCSET (nominal 21.5µA)
through ROCSET. This sets up a voltage that will represent Figure 3 shows the normal curve in blue; initialization begins
the OCSET trip point. At t2, there is a variable time period for at t0, and the output ramps between t1 and t2. If the output is
the OCP sample and hold operation (0ms to 3.4ms nominal; pre-biased to a voltage less than the expected value, as
the longer time occurs with the higher overcurrent setting). shown by the magenta curve, the ISL6545x will detect that
The sample and hold uses a digital counter and DAC to save condition. Neither MOSFET will turn on until the soft-start
the voltage, so the stored value does not degrade, for as ramp voltage exceeds the output; VOUT starts seamlessly
long as the VCC is above VPOR. See “Overcurrent Protection ramping from there. If the output is pre-biased to a voltage
(OCP)” on page 7 for more details on the equations and above the expected value, as in the red curve, neither
variables. Upon the completion of sample and hold at t3, the MOSFET will turn on until the end of the soft-start, at which

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ISL6545, ISL6545A

time it will pull the output voltage down to the final value. Any Following POR (and 6.8ms delay), the ISL6545x initiates the
resistive load connected to the output will help pull down the Overcurrent Protection sample and hold operation. The
voltage (at the RC rate of the R of the load and the C of the LGATE driver is disabled to allow an internal 21.5µA current
output capacitance). source to develop a voltage across ROCSET. The ISL6545x
samples this voltage (which is referenced to the GND pin) at
the LGATE/OCSET pin, and holds it in a counter and DAC
combination. This sampled voltage is held internally as the
VOUT OVERCHARGED Overcurrent Set Point, for as long as power is applied, or
until a new sample is taken after coming out of a shut-down.

The actual monitoring of the lower MOSFET’s on-resistance

starts 200ns (nominal) after the edge of the internal PWM
logic signal (that creates the rising external LGATE signal).
VOUT PRE-BIASED
This is done to allow the gate transition noise and ringing on
the PHASE pin to settle out before monitoring. The
monitoring ends when the internal PWM edge (and thus
VOUT NORMAL LGATE) goes low. The OCP can be detected anywhere
GND>
within the above window.

t0 t1 t2
If the regulator is running at high UGATE duty cycles (around
FIGURE 3. SOFT-START WITH PRE-BIAS 75% for 600kHz or 87% for 300kHz operation), then the
LGATE pulse width may not be wide enough for the OCP to
If the VIN to the upper MOSFET drain is from a different properly sample the rDS(ON). For those cases, if the LGATE
supply that comes up after VCC, the soft-start would go is too narrow (or not there at all) for 3 consecutive pulses,
through its cycle, but with no output voltage ramp. When VIN then the third pulse will be stretched and/or inserted to the
turns on, the output would follow the ramp of the VIN (at 425ns minimum width. This allows for OCP monitoring every
close to 100% duty cycle, with COMP/SD pin >4V), from third pulse under this condition. This can introduce a small
zero up to the final expected voltage. If VIN is too fast, there pulse-width error on the output voltage, which will be
may be excessive inrush current charging the output corrected on the next pulse; and the output ripple voltage will
capacitors (only the beginning of the ramp, from zero to have an unusual 3-clock pattern, which may look like jitter.
VOUT matters here). If this is not acceptable, then consider This is not necessarily a problem; it is more of a compromise
changing the sequencing of the power supplies, or sharing to maintain OCP at the higher duty cycles. If the OCP is
the same supply, or adding sequencing logic to the disabled (by choosing a too-high value of ROCSET, or no
COMP/SD pin to delay the soft-start until the VIN supply is resistor at all), then the pulse stretching feature is also
ready (see “Input Voltage Considerations” on page 9). disabled. Figure 4 illustrates the LGATE pulse width
stretching, as the width gets smaller.
If the IC is disabled after soft-start (by pulling COMP/SD pin
low), and then enabled (by releasing the COMP/SD pin),
> 425 ns
then the full initialization (including OCP sample) will take
place. However, that there is no new OCP sampling during
overcurrent retries.
= 425 ns
If the output is shorted to GND during soft-start, the OCP will
handle it, as described in the next section.

Overcurrent Protection (OCP) < 425 ns

The overcurrent function protects the converter from a
shorted output by using the lower MOSFET’s on-resistance,
rDS(ON), to monitor the current. A resistor (ROCSET)
<< 425 ns
programs the overcurrent trip level (see “Typical Application”
on page 3). This method enhances the converter’s efficiency
and reduces cost by eliminating a current sensing resistor. If
overcurrent is detected, the output immediately shuts off, it FIGURE 4. LGATE PULSE STRETCHING
cycles the soft-start function in a hiccup mode (2 dummy
soft-start time-outs, then up to one real one) to provide fault
protection. If the shorted condition is not removed, this cycle
will continue indefinitely.

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The overcurrent function will trip at a peak inductor current

(IPEAK) determined by Equation 1:

2  I OCSET xR OCSET
I PEAK = ----------------------------------------------------------
-
r DS  ON  (EQ. 1)
INTERNAL SOFT-START RAMP

where IOCSET is the internal OCSET current source (21.5µA

typical). The scale factor of 2 doubles the trip point of the VOUT
MOSFET voltage drop, compared to the setting on the (0.5V/DIV)
ROCSET resistor. The OC trip point varies in a system mainly
due to the MOSFET’s rDS(ON) variations (over process,
current and temperature). To avoid overcurrent tripping in
the normal operating load range, find the ROCSET resistor
GND>
from Equation 1 with:
6.8ms 6.8ms 0ms to 6.8ms 6.8ms
1. The maximum rDS(ON) at the highest junction
temperature. t0 t1 t2 t0 t1

2. The minimum IOCSET from the specification table. FIGURE 5. OVERCURRENT RETRY OPERATION
 I 
3. Determine IPEAK for I PEAK > I OUT  MAX  + ---------- Figure 5 shows the output response during a retry of an
2
whereI is the output inductor ripple current. output shorted to GND. At time t0, the output has been
For an equation for the ripple current see “Output Inductor turned off, due to sensing an overcurrent condition. There
Selection” on page 12. are two internal soft-start delay cycles (t1 and t2) to allow the
The range of allowable voltages detected MOSFETs to cool down, to keep the average power
(2*IOCSET*ROCSET) is 0mV to 475mV; but the practical dissipation in retry at an acceptable level. At time t2, the
range for typical MOSFETs is typically in the 20mV to 120mV output starts a normal soft-start cycle, and the output tries to
ballpark (500 to 3000). If the voltage drop across ramp. If the short is still applied, and the current reaches the
ROCSET is set too low, that can cause almost continuous OCSET trip point any time during soft-start ramp period, the
OCP tripping and retry. It would also be very sensitive to output will shut off, and return to time t0 for another delay
system noise and inrush current spikes, so it should be cycle. The retry period is thus two dummy soft-start cycles
avoided. The maximum usable setting is around 0.2V across plus one variable one (which depends on how long it takes to
ROCSET (0.4V across the MOSFET); values above that trip the sensor each time). Figure 5 shows an example
might disable the protection. Any voltage drop across where the output gets about half-way up before shutting
ROCSET that is greater than 0.3V (0.6V MOSFET trip point) down; therefore, the retry (or hiccup) time will be around
will disable the OCP. The preferred method to disable OCP 17ms. The minimum should be nominally 13.6ms and the
is simply to remove the resistor; that will be detected that as maximum 20.4ms. If the short condition is finally removed,
no OCP. the output should ramp up normally on the next t2 cycle.

Note that conditions during power-up or during a retry may Starting up into a shorted load looks the same as a retry into
look different than normal operation. During power-up in a that same shorted load. In both cases, OCP is always
12V system, the IC starts operation just above 4V; if the enabled during soft-start; once it trips, it will go into retry
supply ramp is slow, the soft-start ramp might be over well (hiccup) mode. The retry cycle will always have two dummy
before 12V is reached. So with lower gate drive voltages, the time-outs, plus whatever fraction of the real soft-start time
rDS(ON) of the MOSFETs will be higher during power-up, passes before the detection and shutoff; at that point, the
effectively lowering the OCP trip. In addition, the ripple logic immediately starts a new two dummy cycle time-out.
current will likely be different at lower input voltage. Output Voltage Selection
Another factor is the digital nature of the soft-start ramp. On The output voltage can be programmed to any level between
each discrete voltage step, there is in effect a small load the 0.6V internal reference, up to the VIN supply. The
transient, and a current spike to charge the output ISL6545x can run at near 100% duty cycle at zero load, but
capacitors. The height of the current spike is not controlled; it the rDS(ON) of the upper MOSFET will effectively limit it to
is affected by the step size of the output, the value of the something less as the load current increases. In addition, the
output capacitors, as well as the IC error amp compensation. OCP (if enabled) will also limit the maximum effective duty
So it is possible to trip the overcurrent with in-rush current, in cycle.
addition to the normal load and ripple considerations.
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See “Typical

FN6305 Rev 7.00 Page 8 of 17

October 7, 2015
ISL6545, ISL6545A
ISL6545, ISL6545A

Application” on page 3 for more detail; RS is the upper open-collector) so as not to interfere with the COMP output.
resistor; ROFFSET (shortened to RO below) is the lower one. Q2 should also be placed near the COMP/SD pin.
The recommended value for RS is 1k to 5k (±1% for VIN VCC
accuracy) and then ROFFSET is chosen according to the
equation below. Since RS is part of the compensation circuit R3
R1 to COMP/SD
(see “Feedback Compensation” on page 10), it is often
easier to change ROFFSET to change the output voltage;
that way the compensation calculations do not need to be R2
Q1 Q2
repeated. If VOUT = 0.6V, then ROFFSET can be left open.
Output voltages less than 0.6V are not available as shown in
Equation 2. FIGURE 6. SEQUENCER CIRCUIT

 RS + RO 
V OUT = 0.6V  --------------------------- The VIN range can be as low as ~1V (for VOUT as low as the
RO
0.6V reference). It can be as high as 20V (for VOUT just
R S  0.6V below VIN). There are some restrictions for running high VIN
R O = ----------------------------------
V OUT – 0.6V (EQ. 2) voltage.

Input Voltage Considerations The first consideration for high VIN is the maximum BOOT
voltage of 36V. The VIN (as seen on PHASE) plus VCC (boot
The Typical Application diagram on page 3 shows a
voltage - minus the diode drop), plus any ringing (or other
standard configuration where VCC is either 5V (±10%) or
transients) on the BOOT pin must be less than 36V. If VIN is
12V (±20%); in each case, the gate drivers use the VCC
20V, that limits VCC plus ringing to 16V.
voltage for LGATE and BOOT/UGATE. In addition, VCC is
allowed to work anywhere from 6.5V up to the 14.4V The second consideration for high VIN is the maximum
maximum. The VCC range between 5.5V and 6.5V is NOT (BOOT - VCC) voltage; this must be less than 24V. Since
allowed for long-term reliability reasons, but transitions BOOT = VIN + VCC + ringing, that reduces to (VIN + ringing)
through it to voltages above 6.5V are acceptable. must be <24V. So based on typical circuits, a 20V maximum
VIN is a good starting assumption; the user should verify the
There is an internal 5V regulator for bias; it turns on between
ringing in their particular application.
5.5V and 6.5V; some of the delay after POR is there to allow
a typical power supply to ramp up past 6.5V before the Another consideration for high VIN is duty cycle. Very low
soft-start ramps begins. This prevents a disturbance on the duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)
output, due to the internal regulator turning on or off. If the require component selection compatible with that choice
transition is slow (not a step change), the disturbance should (such as low rDS(ON) lower MOSFET, and a good LC output
be minimal. So while the recommendation is to not have the filter). At the other extreme (for example, 20V in to 12V out),
output enabled during the transition through this region, it the upper MOSFET needs to be low rDS(ON). In addition, if
may be acceptable. The user should monitor the output for the duty cycle gets too high, it can affect the overcurrent
their application, to see if there is any problem. sample time. In all cases, the input and output capacitors
and both MOSFETs must be rated for the voltages present.
The VIN to the upper MOSFET can share the same supply
as VCC, but can also run off a separate supply or other Switching Frequency
sources, such as outputs of other regulators. If VCC powers The switching frequency is either a fixed 300kHz or 600kHz,
up first, and the VIN is not present by the time the depending on the part number chosen (ISL6545 is 300kHz;
initialization is done, then the soft-start will not be able to ISL6545A is 600kHz). However, all of the other timing
ramp the output, and the output will later follow part of the mentioned (POR delay, OCP sample, soft-start, etc.) is
VIN ramp when it is applied. If this is not desired, then independent of the clock frequency, unless otherwise noted.
change the sequencing of the supplies, or use the
COMP/SD pin to disable VOUT until both supplies are ready. BOOT Refresh
In the event that the UGATE is on for an extended period of
Figure 6 shows a simple sequencer for this situation. If VCC
time, the charge on the boot capacitor can start to sag,
powers up first, Q1 will be off, and R3 pulling to VCC will turn
raising the rDS(ON) of the upper MOSFET. The ISL6545x
Q2 on, keeping the ISL6545x in shut-down. When VIN turns
has a circuit that detects a long UGATE on-time (nominal
on, the resistor divider R1 and R2 determines when Q1 turns
100µs), and forces the LGATE to go high for one clock cycle,
on, which will turn off Q2, and release the shut-down. If VIN
which will allow the boot capacitor some time to recharge.
powers up first, Q1 will be on, turning Q2 off; so the
Separately, the OCP circuit has an LGATE pulse stretcher
ISL6545x will start-up as soon as VCC comes up. The
(to be sure the sample time is long enough), which can also
VDISABLE trip point is 0.4V nominal, so a wide variety of
help refresh the boot. But if OCP is disabled (no current
NFET’s or NPN’s or even some logic IC’s can be used as Q1
or Q2; but Q2 must be low leakage when off (open-drain or

FN6305 Rev 7.00 Page 9 of 17

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ISL6545, ISL6545A
ISL6545, ISL6545A

sense resistor), the regular boot refresh circuit will still be capacitors. For best results, locate the ISL6545x within 1 inch of
active. the MOSFETs, Q1 and Q2 . The circuit traces for the MOSFET
gate and source connections from the ISL6545x must be sized to
Current Sinking
handle up to 1A peak current.
The ISL6545x incorporates a MOSFET shoot-through
protection method which allows a converter to sink current as +VIN
BOOT
well as source current. Care should be exercised when
Q1 LO
designing a converter with the ISL6545x when it is known that CBOOT
VOUT
the converter may sink current. PHASE
ISL6545,

LOAD
When the converter is sinking current, it is behaving as a boost ISL6545A VCC CO
+VCC Q2
converter that is regulating its input voltage. This means that LGATE/OCSET

ROCSET
the converter is boosting current into the VCC rail, which
CVCC
supplies the bias voltage to the ISL6545x. If there is nowhere
for this current to go, such as to other distributed loads on the GND

VCC rail, through a voltage limiting protection device, or other

methods, the capacitance on the VCC bus will absorb the
FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL
current. This situation will allow voltage level of the VCC rail to
LAYOUT GUIDELINES
increase. If the voltage level of the rail is boosted to a level that
exceeds the maximum voltage rating of the ISL6545x, then the Figure 8 shows the circuit traces that require additional layout
IC will experience an irreversible failure and the converter will consideration. Use single point and ground plane construction
no longer be operational. Ensuring that there is a path for the for the circuits shown. Minimize any leakage current paths on
current to follow other than the capacitance on the rail will the COMP/SD pin and locate the resistor, ROSCET close to the
prevent this failure mode. COMP/SD pin because the internal current source is only
20µA. Provide local VCC decoupling between VCC and GND
Application Guidelines pins. Locate the capacitor, CBOOT as close as practical to the
Layout Considerations BOOT and PHASE pins. All components used for feedback
compensation (not shown) should be located as close to the IC
As in any high frequency switching converter, layout is very
as practical.
important. Switching current from one power device to another
can generate voltage transients across the impedances of the Feedback Compensation
interconnecting bond wires and circuit traces. These
This section highlights the design consideration for a
interconnecting impedances should be minimized by using wide,
voltage-mode controller requiring external compensation. To
short printed circuit traces. The critical components should be
address a broad range of applications, a type-3 feedback
located as close together as possible, using ground plane
network is recommended, as shown in the top part of Figure 9.
construction or single point grounding.
Figure 9 also highlights the voltage-mode control loop for a
VIN synchronous-rectified buck converter, applicable to the ISL6545x
ISL6545, circuit. The output voltage (VOUT) is regulated to the reference
ISL6545A voltage, VREF. The error amplifier output (COMP pin voltage) is
UGATE Q1 compared with the oscillator (OSC) modified sawtooth wave to
LO
PHASE VOUT provide a pulse-width modulated wave with an amplitude of VIN at
the PHASE node. The PWM wave is smoothed by the output filter
Q2 CIN (L and C). The output filter capacitor bank’s equivalent series
LOAD

LGATE/OCSET CO resistance is represented by the series resistor E.

RETURN
FIGURE 7. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS

Figure 7 shows the critical power components of the converter. To

minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown should be
located as close together as possible. Please note that the
capacitors CIN and CO may each represent numerous physical

FN6305 Rev 7.00 Page 10 of 17

October 7, 2015
ISL6545, ISL6545A
ISL6545, ISL6545A

C2 V OSC  R1  F 0
R2 = ---------------------------------------------
d MAX  V IN  F LC (EQ. 4)

R3 C3
COMP
R2 C1 2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at
0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired
- number). The higher the quality factor of the output filter and/or
FB R1 the higher the ratio FCE/FLC, the lower the FZ1 frequency (to
+ Ro
E/A maximize phase boost at FLC).
VREF 1
C1 = ------------------------------------------------
2  R2  0.5  F LC (EQ. 5)

3. Calculate C2 such that FP1 is placed at FCE.

OSCILLATOR VOUT
C1
VIN C2 = ---------------------------------------------------------
2  R2  C1  F CE – 1 (EQ. 6)
PWM VOSC
CIRCUIT
4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such
L that FP2 is placed below FSW (typically, 0.5 to 1.0 times
UGATE D
HALF-BRIDGE FSW). FSW represents the switching frequency. Change the
DRIVE numerical factor to reflect desired placement of this pole.
PHASE C
Placement of FP2 lower in frequency helps reduce the gain
of the compensation network at high frequency, in turn
E
LGATE reducing the HF ripple component at the COMP pin and
minimizing resultant duty cycle jitter.
R1 1
ISL6545x EXTERNAL CIRCUIT R3 = ---------------------- C3 = -------------------------------------------------
F SW 2  R3  0.7  F SW
------------ – 1
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER F LC (EQ. 7)
COMPENSATION DESIGN
It is recommended a mathematical model is used to plot the
The modulator transfer function is the small-signal transfer loop response. Check the loop gain against the error
function of VOUT /VCOMP. This function is dominated by a DC amplifier’s open-loop gain. Verify phase margin results and
gain, given by dMAXVIN /VOSC , and shaped by the output filter, adjust as necessary. The equations shown in Equations 8 and
with a double pole break frequency at FLC and a zero at FCE . 9 describe the frequency response of the modulator (GMOD),
For the purpose of this analysis, L and D represent the channel feedback compensation (GFB) and closed-loop response
inductance and its DCR, while C and E represent the total output (GCL):
capacitance and its equivalent series resistance.
d MAX  V IN 1 + sf  E  C
G MOD  f  = ------------------------------  ----------------------------------------------------------------------------------------
1 1 V OSC 2
F LC = --------------------------- F CE = ------------------------ 1 + sf  E + D  C + s f  L  C
2  L  C 2  C  E (EQ. 3)

1 + s  f   R2  C1
G FB  f  = ------------------------------------------------------ 
The compensation network consists of the error amplifier (internal s  f   R1   C1 + C2  (EQ. 8)
to the ISL6545x) and the external R1-R3, C1-C3 components. 1 + s  f    R1 + R3   C3
 -----------------------------------------------------------------------------------------------------------------------------
C1  C2
The goal of the compensation network is to provide a closed loop  1 + s  f   R3  C3    1 + s  f   R2   ---------------------- 
  C1 + C2 
transfer function with high 0dB crossing frequency (F0; typically
0.1 to 0.3 of FSW) and adequate phase margin (better than 45°).
G CL  f  = G MOD  f   G FB  f  where s  f  = 2  f  j
Phase margin is the difference between the closed loop phase at
F0dB and 180°. The equations that follow relate the compensation
network’s poles, zeros and gain to the components (R1, R2, R3, COMPENSATION BREAK FREQUENCY EQUATIONS
C1, C2, and C3) in Figure 9. Use the following guidelines for 1
1 F P1 = -----------------------------------------------
locating the poles and zeros of the compensation network: F Z1 = -------------------------------- C1  C2
2  R2  C1 2  R2  ----------------------
C1 + C2 (EQ. 9)
1. Select a value for R1 (1k to 5k, typically). Calculate
value for R2 for desired converter bandwidth (F0). If setting 1 1
F Z2 = --------------------------------------------------- F P2 = --------------------------------
the output voltage via an offset resistor connected to the FB 2   R1 + R3   C3 2  R3  C3
pin, Ro in Figure 9, the design procedure can be followed
as presented.

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ISL6545, ISL6545A
ISL6545, ISL6545A

Figure 10 shows an asymptotic plot of the DC/DC converter’s load transient requirements are a function of the slew rate
gain vs frequency. The actual Modulator Gain has a high gain (di/dt) and the magnitude of the transient load current. These
peak dependent on the quality factor (Q) of the output filter, which requirements are generally met with a mix of capacitors and
is not shown. Using the above guidelines should yield a careful layout.
compensation gain similar to the curve plotted. The open loop
Modern components and loads are capable of producing
error amplifier gain bounds the compensation gain. Check the
transient load rates above 1A/ns. High frequency capacitors
compensation gain at FP2 against the capabilities of the error
initially supply the transient and slow the current load rate seen
amplifier. The closed loop gain, GCL, is constructed on the log-log
by the bulk capacitors. The bulk filter capacitor values are
graph of Figure 10 by adding the modulator gain, GMOD (in dB),
generally determined by the ESR (Effective Series Resistance)
to the feedback compensation gain, GFB (in dB). This is
and voltage rating requirements rather than actual capacitance
equivalent to multiplying the modulator transfer function and the
requirements.
compensation transfer function and then plotting the resulting
gain. High frequency decoupling capacitors should be placed as
FZ1 FZ2 FP1 FP2 MODULATOR GAIN close to the power pins of the load as physically possible. Be
COMPENSATION GAIN
GAIN

CLOSED LOOP GAIN careful not to add inductance in the circuit board wiring that
OPEN LOOP E/A GAIN could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.

Use only specialized low-ESR capacitors intended for switching-

R2
20 log  -------- d MAX  V regulator applications for the bulk capacitors. The bulk
 R1 IN
20 log --------------------------------- capacitor’s ESR will determine the output ripple voltage and the
0 V
OSC
GFB initial voltage drop after a high slew-rate transient. An aluminum
GCL electrolytic capacitor’s ESR value is related to the case size with
lower ESR available in larger case sizes. However, the
Equivalent Series Inductance (ESL) of these capacitors
LOG

GMOD
LOG increases with case size and can reduce the usefulness of the
FLC FCE F0 FREQUENCY
capacitor to high slew-rate transient loading. Unfortunately, ESL
FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
is not a specified parameter. Work with your capacitor supplier
A stable control loop has a gain crossing with close to a and measure the capacitor’s impedance with frequency to select
-20dB/decade slope and a phase margin greater than 45°. a suitable component. In most cases, multiple electrolytic
Include worst case component variations when determining capacitors of small case size perform better than a single large
phase margin. The mathematical model presented makes a case capacitor.
number of approximations and is generally not accurate at Output Inductor Selection
frequencies approaching or exceeding half the switching
The output inductor is selected to meet the output voltage
frequency. When designing compensation networks, select
ripple requirements and minimize the converter’s response
target crossover frequencies in the range of 10% to 30% of the
time to the load transient. The inductor value determines the
switching frequency, FSW.
converter’s ripple current and the ripple voltage is a function of
This is just one method to calculate compensation the ripple current. The ripple voltage and current are
components; there are variations of Equations 3 through 9. approximated by the equations shown in Equation 10:
The error amp is similar to that on other Intersil regulators, so VIN - VOUT VOUT
existing tools can be used here as well. Special consideration I = x VOUT = I x ESR
Fsw x L VIN (EQ. 10)
is needed if the size of a ceramic output capacitance in parallel
with bulk capacitors gets too large; the calculation needs to Increasing the value of inductance reduces the ripple current
model them both separately (attempting to combine two and voltage. However, the large inductance values reduce the
different capacitors types into one composite component converter’s response time to a load transient.
model may not work properly; a special tool may be needed;
contact Intersil at http://www.intersil.com/contacts/ for One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
assistance.
current. Given a sufficiently fast control loop design, the
Component Selection Guidelines ISL6545x will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
Output Capacitor Selection required to slew the inductor current from an initial current
An output capacitor is required to filter the output and supply value to the transient current level. During this interval the
the load transient current. The filtering requirements are a difference between the inductor current and the transient
function of the switching frequency and the ripple current. The current level must be supplied by the output capacitor.

FN6305 Rev 7.00 Page 12 of 17

October 7, 2015
ISL6545, ISL6545A
ISL6545, ISL6545A

Minimizing the response time can minimize the output converter is sinking current (see the equations in Equation 12).
capacitance required. These equations assume linear voltage-current transitions and do
not adequately model power loss due the reverse-recovery of
The response time to a transient is different for the application
the upper and lower MOSFET’s body diode. The gate-charge
of load and the removal of load. The equations in Equation 11
losses are dissipated by the ISL6545x and do not heat the
give the approximate response time interval for application and
MOSFETs. However, large gate-charge increases the switching
removal of a transient load:
interval, tSW which increases the MOSFET switching losses.
L x ITRAN L x ITRAN Ensure that both MOSFETs are within their maximum junction
tRISE = tFALL = (EQ. 11)
VIN - VOUT VOUT temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
where: ITRAN is the transient load current step, tRISE is the specifications. A separate heatsink may be necessary depending
response time to the application of load, and tFALL is the upon MOSFET power, package type, ambient temperature and
response time to the removal of load. The worst case response air flow.
time can be either at the application or removal of load. Be Losses while Sourcing Current
sure to check both of these equations at the minimum and 2 1
P UPPER = Io  r DS  ON   D + ---  Io  V IN  t SW  F S
maximum output levels for the worst case response time. 2
PLOWER = Io2 x rDS(ON) x (1 - D)
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage Losses while Sinking Current (EQ. 12)
overshoot across the MOSFETs. Use small ceramic capacitors PUPPER = Io2 x rDS(ON) x D
for high frequency decoupling and bulk capacitors to supply the 2 1
P LOWER = Io  r DS  ON    1 – D  + ---  Io  V IN  t SW  F S
current needed each time Q1 turns on. Place the small ceramic 2
Where: D is the duty cycle = VOUT / VIN ,
capacitors physically close to the MOSFETs and between the
tSW is the combined switch ON and OFF time, and
drain of Q1 and the source of Q2 .
FSW is the switching frequency.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable When operating with a 12V power supply for VCC (or down to a
operation, select the bulk capacitor with voltage and current minimum supply voltage of 6.5V), a wide variety of N-MOSFETs
ratings above the maximum input voltage and largest RMS can be used. Check the absolute maximum VGS rating for both
current required by the circuit. The capacitor voltage rating MOSFETs; it needs to be above the highest VCC voltage allowed
should be at least 1.25x greater than the maximum input in the system; that usually means a 20V VGS rating (which
voltage and a voltage rating of 1.5x is a conservative guideline. typically correlates with a 30V VDS maximum rating). Low
The RMS current rating requirement for the input capacitor of a threshold transistors (around 1V or below) are not recommended,
buck regulator is approximately 1/2 the DC load current. for the reasons explained in the next paragraph.

For a through-hole design, several electrolytic capacitors may be For 5V only operation, given the reduced available gate bias
needed. For surface mount designs, solid tantalum capacitors can voltage (5V), logic-level transistors should be used for both N-
also be used, but caution must be exercised with regard to the MOSFETs. Look for rDS(ON) ratings at 4.5V. Caution should be
capacitor surge current rating. These capacitors must be capable exercised with devices exhibiting very low VGS(ON)
of handling the surge current at power-up. Some capacitor series characteristics. The shoot-through protection present aboard
available from reputable manufacturers are surge current tested. the ISL6545x may be circumvented by these MOSFETs if they
have large parasitic impedences and/or capacitances that
MOSFET Selection/Considerations would inhibit the gate of the MOSFET from being discharged
The ISL6545x requires two N-Channel power MOSFETs. These below its threshold level before the complementary MOSFET is
should be selected based upon rDS(ON) , gate supply turned on. Also avoid MOSFETs with excessive switching
requirements, and thermal management requirements. times; the circuitry is expecting transitions to occur in under
50ns or so.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design factors.
The power dissipation includes two loss components; conduction
loss and switching loss. The conduction losses are the largest
component of power dissipation for both the upper and the lower
MOSFETs. These losses are distributed between the two
MOSFETs according to duty factor. The switching losses seen
when sourcing current will be different from the switching
losses seen when sinking current. When sourcing current, the
upper MOSFET realizes most of the switching losses. The
lower switch realizes most of the switching losses when the

FN6305 Rev 7.00 Page 13 of 17

October 7, 2015
ISL6545, ISL6545A
ISL6545, ISL6545A

+VCC +VIN

VCC
+ VD -
BOOT
CBOOT
ISL6545x Q1
UGATE
PHASE
VG-S  VCC - VD

VCC
Q2
-
+
LGATE/OCSET
VG-S  VCC

GND

FIGURE 11. UPPER GATE DRIVE BOOTSTRAP

BOOTSTRAP Considerations
Figure 11 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from VCC . The boot capacitor, CBOOT,
develops a floating supply voltage referenced to the PHASE pin.
The supply is refreshed to a voltage of VCC less the boot diode
drop (VD) each time the lower MOSFET, Q2 , turns on. Check
that the voltage rating of the capacitor is above the maximum
VCC voltage in the system; a 16V rating should be sufficient for a
12V system. A value of 0.1µF is typical for many systems driving
single MOSFETs.

If VCC is 12V, but VIN is lower (such as 5V), then another

option is to connect the BOOT pin to 12V, and remove the
BOOT cap (although, you may want to add a local cap from
BOOT to GND). This will make the UGATE VGS voltage equal
to (12V - 5V = 7V). That should be high enough to drive most
MOSFETs, and low enough to improve the efficiency slightly.
Do NOT leave the BOOT pin open, and try to get the same
effect by driving BOOT through VCC and the internal diode;
this path is not designed for the high current pulses that will
result.

For low VCC voltage applications where efficiency is very

important, an external BOOT diode (in parallel with the internal
one) may be considered. The external diode drop has to be
lower than the internal one; the resulting higher VG-S of the
upper FET will lower its rDS(ON). The modest gain in efficiency
should be balanced against the extra cost and area of the
external diode.

FN6305 Rev 7.00 Page 14 of 17

October 7, 2015
ISL6545, ISL6545A
ISL6545, ISL6545A

Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.

DATE REVISION CHANGE

October 7, 2015 FN6305.7 - Updated Ordering Information Table on page 2.

- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD L10.3X3C to latest revision changes are as follow:
Removed package outline and included center to center distance between lands on recommended land
pattern.
Tiebar Note 4 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
- Updated POD M8.15 to latest revision changes are as follow:
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Changed Note 1 "1982" to "1994"

About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
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FN6305 Rev 7.00 Page 15 of 17

October 7, 2015
ISL6545, ISL6545A
ISL6545, ISL6545A

Package Outline Drawing

L10.3x3C
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 4, 3/15
5
3.00 A PIN #1 INDEX AREA
B

10 1
5
2
PIN 1
INDEX AREA

2.38
3.00

0.50
10 x 0.25
6
(4X) 0.10 C B

1.64
TOP VIEW 10x 0.40
BOTTOM VIEW
(4X) 0.10 M C B

(10 x 0.60) SEE DETAIL "X"

(10x 0.25) 0.10 C

MAX
0.90

C
BASE PLANE
0.20 SEATING PLANE
2.38

0.08 C
SIDE VIEW

(8x 0.50)

1.64
2.80 TYP

0.20 REF 4
C
TYPICAL RECOMMENDED LAND PATTERN
0.05

DETAIL "X"

NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).

5. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6. Compliant to JEDEC MO-229-WEED-3 except for E-PAD
dimensions.

FN6305 Rev 7.00 Page 16 of 17

October 7, 2015
ISL6545, ISL6545A
ISL6545, ISL6545A

Package Outline Drawing

M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12

DETAIL "A"
1.27 (0.050)
0.40 (0.016)

INDEX 6.20 (0.244)

AREA 5.80 (0.228)
0.50 (0.20)
x 45°
4.00 (0.157) 0.25 (0.01)
3.80 (0.150)

8°
1 2 3 0°

0.25 (0.010)
0.19 (0.008)
TOP VIEW SIDE VIEW “B”

2.20 (0.087)

1 8
SEATING PLANE

1.75 (0.069) 0.60 (0.023)

5.00 (0.197) 2 7
4.80 (0.189) 1.35 (0.053)
1.27 (0.050)

3 6
-C-

4 5
1.27 (0.050) 0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013) 5.20(0.205)

SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN

NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

FN6305 Rev 7.00 Page 17 of 17

October 7, 2015