1501-102 - Circuit Pack Description

323-1501-102
Nortel Networks
OPTera Connect DX Connection
Manager
Circuit Pack Descriptions
Standard Rel 1 August 2000
What’s inside...
Circuit pack descriptions
Copyright  2000 Nortel Networks, All Rights Reserved
The information contained herein is the property of Nortel Networks and is strictly confidential. Except as expressly authorized in
writing by Nortel Networks, the holder shall keep all information contained herein confidential, shall disclose it only to its employees
with a need to know, and shall protect it, in whole or in part, from disclosure and dissemination to third parties with the same degree
of care it uses to protect its own confidential information, but with no less than reasonable care. Except as expressly authorized in
writing by Nortel Networks, the holder is granted no rights to use the information contained herein.
Nortel Networks, the Nortel Networks logo, the Globemark, How the world shares ideas, and Unified Networks are trademarks of
Nortel Networks.
Printed in Canada and in the United Kingdom

i
Contents 0
About this document iii
Circuit pack descriptions 1-1

Quad T/R interfaces (NTCA33, NTCA36) 1-4
OC-12 half-height T/R interface (NTCA31) 1-10
OC-48 T/R interface (NTCA30) 1-13
STS-48 T/R electrical interface (NTCA34) 1-16
OC-192 T/R interface (NTCA06) 1-18
TRDA 1-18
OTR 1-20
OC-192 XR (NTCA04) 1-24
Support circuits 1-25
OC-192 DWDM transmit interface (NTCA01) 1-28
OC-192 DWDM regenerator/transmit interface (NTCA03) 1-32
OC-192 short reach receive interface (NTCA02) 1-35
OC-192 demultiplexer (NTCA05) 1-38
Switch module (NTCA26, NTCA24) 1-41
MOR (NTCA11) 1-47
MOR Plus (NTCA11) 1-52
Partitioned operations controller 1-57
OPC controller (NTCA50) 1-59
OPC interface (NTCA52) 1-62
OPC storage (NTCA51AA and NTCA51AB) 1-65
OPC removable media (NTCA53) 1-68
Orderwire (NTCA47) 1-69
Shelf controller (NTCA41) 1-69
Maintenance interface (NTCA42) 1-73
External synchronization interface (NTCA44) 1-77
Message exchange (NTCA48) 1-79
Parallel telemetry (NTCA45) 1-83
Breaker/filter module (NTCA40) 1-86
Fan module (NTCA85) 1-89
Filler card (NTCA49/59) 1-92
Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

ii Contents
OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

iii
About this document

This document describes the circuit packs used in the network elements (NEs)
for the Nortel Networks OPTera Connect DX Connection Manager (referred
to as OPTera Connect DX in this document). In addition to the OPTera
Connect DX bays, this document also covers the OPTera Connect DX product
in the OC-192 bays. Topics covered include the following:
• bay
• shelves
• fibre management hardware
• circuit packs
Audience
This document is for the following members of the operating company:
• planners
• provisioners
• network administrators
• transmission standards engineers
• maintenance engineers

iv About this document
OPTera Connect DX SONET NTP Library

(OPTera Connect DX & OC-192 Platforms)
Supporting
Installing, Managing and Maintaining and
Planning a Commissioning and Provisioning Troubleshooting
documentation for
Network Testing a Network a Network
the OPTera Connect
a Network
DX SONET Library
OC-3/OC-12 NE
TBM NTP Library
(323-1111-XXX)
OC-48 NTP Library

(323-1201-XXX)
Planning Guide Installation User Interface Performance
(NTRR10DA) Procedures Connection Procedures Monitoring Procedures
(323-1521-201) (323-1501-301) (323-1521-520)
About the OPTera Installation External Interface Performance
Connect DX SONET Procedures Configuration Monitoring Procedures OC-192 NTP Library
NTP Library (323-1541-201) Procedures (323-1541-520) (323-1301-XXX)
(DX Platform) (323-1501-302)
(323-1521-090) Powering up and Fault Detection
Commissioning Software Administration
(323-1521-541)
Procedures Procedures
About the OPTera (323-1501-303)
Connect DX SONET (323-1521-220) Optical Networks
NTP Library Fault Detection
Data Administration (323-1541-541) Applications Library
(323-1521-090 or Powering up and Procedures (NTCA66BA)
323-1541-090 or Commissioning (323-1501-304)
323-1521/1541-090) Procedures Alarm Reference
(323-1541-220) Security Management Guide
Circuit (323-1521-542)
Procedures
Pack Descriptions Site Testing (323-1501-305)
Procedures Alarm Reference OPTera Long Haul
(323-1501-102) (323-1521-221) Guide 1600 NTP Library
Provisioning and (323-1541-542) (NTCA65EC)
Ordering Operations Procedures
Information Site Testing (323-1521-310)
Procedures Trouble Clearing and
(323-1521-151)
(323-1541-221) Module Replacement
Provisioning and
Ordering (323-1521-543)
Operations Procedures
Information System Commissioning (323-1541-310) Orderwire User
(323-1541-151) and Testing Procedures Trouble Clearing and Guide
(323-1521-222) Protection Module Replacement (NTCA66CA)
TL1 Interface Switching Description (323-1541-543)
Description System Commissioning and Procedures
(323-1521-190) and Testing Procedures (323-1521-311) Log Reference
(323-1541-222) (323-1501-840)
TL1 Interface Protection
Switching Description Preside NTP
Description Library
(323-1541-190) and Procedures
(323-1541-311) (450-3101-XXX)
NE User Interface
Description
(323-1501-195)
NE User Interface
Description References for NTP 102
(323-1521-195)
Ordering Information 323-1521/-1541-151 (OPTera Connect DX) / (OC-192)
OPC User Interface
Description
(323-1501-196)

1-1
Circuit pack descriptions 1-

This chapter describes the circuit packs that are used in both the OPTera
Connect DX equipment bay and the OC-192 bays. Each description includes
a functional block diagram and a mechanical view of the circuit pack.
Note 1: In the circuit pack descriptions contained in this chapter, the

‘receive direction’ is from line to tributary. The ‘transmit direction’ is from
tributary to line.
Note 2: References to ‘OC-192 bays’ in this chapter are to the OPTera
Connect DX product in OC-192 bays.
Table 1-1
Summary of circuit pack usage
Circuit pack identity PEC OPTera OC-192 Regen. Page
Connect DX
Tributaries
Quad OC-3 optical T/R interface NTCA33 ü 1-4
Quad OC-12 optical T/R interface NTCA36 ü ü 1-4
For variants see Ordering Information,
323-1521-151 (OPTera Connect DX) or
323-1541-151 (OC-192)
OC-12 half-height T/R interface NTCA31BA ü 1-10
NTCA31BB ¸
NTCA31BC ü
OC-48 T/R interface NTCA30 ü ü 1-13
For variants see Ordering Information, ü ü
323-1521-151 (OPTera Connect DX) or ü ü
323-1541-151 (OC-192) ü ü
STS-48 electrical T/R interface NTCA34 ü ü 1-16
Line
OC-192 T/R interface NTCA06 ü 1-18
323-1521-151 (OPTera Connect DX)
OC-192 XR NTCA04 ü 1-24

1-2 Circuit pack descriptions
Table 1-1 (continued)

Connect DX
OC-192 DWDM transmit interface NTCA01 ü 1-28
323-1541-151 (OC-192)
OC-192 DWDM Regenerator/Transmit interface NTCA03 ü 1-32
323-1541-151 (OC-192)
OC-192 short reach receive interface NTCA02 ü 1-35
323-1541-151 (OC-192)
OC-192 demultiplexer NTCA05 ü 1-38
Switch
DX65 Switch module NTCA26 ü 1-41
DOS Switch module NTCA24 ü 1-41
MOR NTCA11AK ü ü 1-47
NTCA11BK ü ü
NTCA11CK ü ü
MOR plus NTCA11NK ü ü 1-47
NTCA11PK ü ü
NTCA11JK ü ü
NTCA11KK ü ü
Control shelf
OPC controller NTCA50 ü ü ü 1-59
OPC interface NTCA52 ü ü ü 1-62
OPC storage NTCA51AA ü ü ü 1-65
NTCA51AB ü
OPC removable media NTCA53 ü ü ü 1-68
Orderwire NTCA47AA ü ü 1-69
Shelf controller NTCA41BA ü ü 1-69
NTCA41CA ü ü ü
Maintenance interface NTCA42 ü ü ü 1-73
External synchronization interface (ESI):1.5 MHz NTCA44AA ü ü 1-77
Message exchange (MI) NTCA48 ü ü ü 1-79
Parallel telemetry NTCA45 ü ü ü 1-83
Breaker/filter module NTCA40 ü ü 1-86
ü
Fan module NTCA85 ü 1-89
ü ü

Table 1-1 (continued)

Connect DX
Filler card (transport shelf - tributary or line) NTCA49AA ü ü 1-92
Filler card (double-width Switch module slot) NTCA49AB ü ü 1-92
Filler card (single, half-height) NTCA49AC ü 1-92
Filler card (Control shelf) NTCA59AA ü ü ü 1-92
Note: The PEC consists of the letters NTCA, followed by two digits and
two letters. The two digits of the PEC represent the circuit pack type. The
last two letters represent the variant of the circuit pack. Only some variants
are covered in Table 1-1. For full details of all the variants of each circuit
pack, refer to Ordering Information, 323-1521-151 for OPTera Connect
DX bays, or 323-1541-151, for OPTera Connect DX (OC-192) bays.

Quad T/R interfaces (NTCA33, NTCA36)

The Quad transmit/receive (T/R) interfaces include:
• four low-speed interface circuits for processing SONET based traffic
• a backplane interface circuit, which interfaces the tributaries with the
Switch modules
• a distributed processing control architecture
The shelf can contain two types of Quad circuit pack:
• Quad OC-3 optical interface (NTCA33)
• Quad OC-12 optical interface (NTCA36)
Note: Of the two Quad circuit packs listed above, the OPTera Connect DX
shelf supports only the Quad OC-12 optical interface.
The NTCA33 and NTCA36 interfaces have a vertically mounted handling tray
that provides access to the optical fiber connections for connector cleaning.
The Quad T/R interface circuit packs perform the following functions:
• provide OC-12 or OC-3 transmit and receive facility terminations
• process overhead
• perform performance monitoring
• synchronize data to shelf timing
Figure 1-1 and Figure 1-2 show functional block diagrams for the Quad optical
interface circuit packs. Figure 1-3 shows a view of a Quad optical interface
circuit pack. Except for the identification label, both types of Quad optical
interface circuit pack have the same external appearance.
Transmit direction
The bidirectional backplane interface (BIBI) receives data inputs from Switch
Module A or Switch Module B, depending on which is active. Each input
consists of four 622 Mbit/s data streams. Switch Modules A and B form a
working and protection pair.
The BIBI divides the 311 MHz backplane clock down to 19 MHz and uses this
as reference for the phase-locked loop (PLL). The PLL contains a 155 MHz
voltage-controlled crystal oscillator (VCXO) that provides 19 MHz and
39 MHz timing for the circuit pack. The BIBI demultiplexes the 622 Mbit/s
serial data streams down to byte wide 78 Mbit/s data streams for four STS-3
or STS-12 channels.
The BIBI passes the byte wide 78 Mbit/s data to each of the four overhead
processor and synchronizer (OOPS) circuits, together with a 78 MHz clock.
The OOPS inserts the line and section overhead.

Following overhead processing, the OOPS scrambles and outputs the data as:
• eight 78 Mbit/s data streams (STS-12 interface circuit packs)
• eight 19 Mbit/s data streams (STS-3 interface circuit packs).
Each OOPS passes the tributary data to an associated tributary interface
circuit.
The electro-optical interface (EOI) circuits perform electrical to optical

conversion. Each EOI contains the following circuits:
• A SONET transmit interface (STX) multiplexes the parallel data from the
OOPS into a serial data stream. The serial output is:
— 622 Mbit/s for the OC-12 interface circuit packs
— 155 Mbit/s for the OC-3 interface circuit packs
• A laser driver accepts the data stream and generates a modulation current
to drive the laser diode module (LDM). The laser driver provides a bias
current to maintain the LDM at the correct bias threshold.
• The LDM converts the electrical data stream into an amplitude modulated
optical output for transmission.
Receive direction
A photodiode module (PDM) in the EOI converts the incoming optical signal
into an electrical signal. For OC-3 interfaces, the incoming signal is
155 Mbit/s. For OC-12 interfaces the input is at 622 Mbit/s. The PDM drives
a post amplifier through a low pass filter, which limits the bandwidth of the
receive channel. The SONET receive interface (SRX) demultiplexes the signal
into a byte wide parallel output with a recovered clock and parity. For the
OC-3 optical interfaces the byte-wide parallel output is at 19 Mbit/s. For the
OC-12 optical interfaces, the parallel output is at 78 Mbit/s.
Each OOPS receives the signal from the EOI. The main functions of the OOPS
are to:
• synchronize the incoming optical fiber data to system (shelf) timing,
• terminate and process the transport overhead,
• monitor the path overhead.
• pass the output as 78 Mbit/s byte wide data to the BIBI.
Note: This output is 78 Mbit/s byte wide for all versions of the circuit
pack. The Quad OC-3 interfaces use only 25% of the data.

The BIBI multiplexes the incoming byte wide data from the four OOPS
circuits to four 622 Mbit/s serial data streams. The BIBI produces two groups
of four 622 Mbit/s outputs. One group goes to Switch Module A and the other
to Switch Module B. The OOPS then sends the data to the Switch Modules by
way of the shelf backplane.
Support circuits
Four circuits support the Quad OC-12 and Quad OC-3 T/R interfaces:
• the EOI controller
• the transport control subsystem, second generation (TCS+)
• the phase-locked loop (PLL)
• the point-of-use power supply (PUPS)
The EOI controller subsystem monitors control signals from the Rx and Tx
channels. The EOI controller also provides status and alarm information to the
TCS+ processor through a synchronous serial peripheral interface (SPI).
The TCS+ provides performance monitoring, fault handling, propagation of

status information to the shelf controller, and circuit pack provisioning.
The PLL uses the backplane clock to the BIBI to produce the 19 MHz clock.
The PLL provides system timing to the circuit pack. The PUPS uses the –48 V
battery voltage from the shelf to produce the supplies required by the Quad
OC-12 T/R interface.

Figure 1-1
Quad OC-3 T/R optical interface block diagram
DX1382_SONET
To
backplane
TCS+ SPI EOI controller
Analog MUX
155 Mbit/s
OC-3
622Mbit/s data from the Switch Modules
Laser
78 Mbit/s 19 Mbit/s Laser diode
Tx data 1 Tx data STX driver
Data 1 8 8 module
A Data 3 OOPS 1 EOI 1
Data 2 OC-3
Data 4 78 Mbit/s 19 Mbit/s Post 155 Mbit/s LP Photo
Rx data 1 Rx data SRX diode
311 MHz 8 8 amp filter
CLK1 module
155 Mbit/s
OC-3
Laser
Data 1 8 8 module
B Data 3 OOPS 2 EOI 2
Data 2 OC-3
Data 4 19 Mbit/s Photo
78 Mbit/s Post LP
Rx data 2 Rx data 8 SRX amp diode
8 filter module
311 MHz
CLK2
BIBI
155 Mbit/s
Laser OC-3
19 Mbit/s Laser
Tx data 3 78 Mbit/s STX diode
622Mbit/s data to the Switch Modules
Tx data driver
Data 1 8 8 module
A Data 3 OOPS 3
Data 2 EOI 3 OC-3
Rx data 3
78 Mbit/s
Rx data SRX Post 155 Mbit/s LP diode
8 amp
311 MHz 8 filter module
CLK1
311 MHz 155 Mbit/s OC-3

CLK2 Laser
78 Mbit/s Laser diode
Tx data 4 Tx data 19 Mbit/s STX driver
Data 1 8 module
8
Data 2 OC-3
19 Mbit/s SRX Post 155 Mbit/s LP
Rx data 4 Rx data diode
8 8 amp filter module
PLL Clamp
155 MHz +5.0V

VCXO -48V
Board
PUPS +3.3V power
Legend: rails
BATRET
BIBI = Bi-directional Backplane Interface DC to DC
EOI = Electro-Optical Interface -4.5V
converter
OOPS = OC-12 Overhead Processor and Synchronizer
PLL = Phase-locked loop
PUPS = Point of use power supply
SRX = SONET Receive interface
STX = SONET Transmit interface
TCS = Transport Control Subsystem, 2nd generation
VCXO = Voltage controller crystal oscillator

Figure 1-2
Quad OC-12 T/R optical interface block diagram
DX1381_SONET
To
backplane
SPI
TCS+ EOI controller
Analog MUX
622 Mbit/s
OC-12
622Mbit/s data from the Switch Modules
Laser
Data 1 8 8 module
A Data 3 OOPS 1 EOI 1
Data 2 OC-12
Data 4 78 Mbit/s 78 Mbit/s Post 622 Mbit/s LP Photo
Rx data 1 Rx data SRX diode
311 MHz 8 8 amp filter
CLK1 module
622 Mbit/s
OC-12
Laser
8 module
Data 1 8
Data 2 OC-12
78 Mbit/s Post 622 Mbit/s LP
Rx data 2 Rx data 8 SRX amp diode
8 filter module
311 MHz
CLK2
BIBI 622 Mbit/s

Laser OC-12
78 Mbit/s Laser
Tx data 3 78 Mbit/s STX diode
622Mbit/s data to the Switch Modules
Tx data driver
Data 1 8 8 module
A Data 3 OOPS 3
Data 2 EOI 3 OC-12
Rx data 3
78 Mbit/s
Rx data SRX Post 622 Mbit/s LP diode
8 amp
311 MHz 8 filter module
CLK1
311 MHz 622 Mbit/s OC-12

CLK2 Laser
78 Mbit/s Laser diode
Tx data 4 Tx data 78 Mbit/s STX driver
Data 1 8
8
module
Data 2 OC-12
78 Mbit/s SRX Post 622 Mbit/s LP
Rx data 4 Rx data diode
8 8 amp filter module
PLL Clamp
155 MHz +5.0V

VCXO -48V
Board
PUPS +3.3V power
Legend: rails
BATRET
BIBI = Bi-directional Backplane Interface DC to DC
EOI = Electro-Optical Interface -4.5V
converter
OOPS = OC-12 Overhead Processor and Synchronizer
SRX = SONET Receive interface
STX = SONET Transmit interface
TCS = Transport Control Subsystem, 2nd generation
VCXO = Voltage controller crystal oscillator

Figure 1-3
Quad T/R optical interface circuit pack
F5378-192_R60
Fiber carrier
Latch Carrier
handles
Optical
connectors
A-B C-D
QUAD
OC-12
STM-4
D
QUA 2 T/R
1
OC- 4
T M -
S
T/R
C D
OUT IN OUT IN
OUT C
IN
Carrier
OUT D
IN
handle
1
1 2
2 3
3 4
4
Latch
Dual fiber Side view Front view

cables

OC-12 half-height T/R interface (NTCA31)

Note: The half-height T/R interface is used in the OC-192 bays only. It is
not used in the OPTera Connect DX bays.
The OC-12 transmit/receive (T/R) interface is a low-speed T/R tributary

interface. The main functions of the circuit pack are to:
• provide OC-12 transmit and receive facility terminations
• process overhead
Figure 1-4 shows a functional block diagram. Figure 1-5 shows a view of the
OC-12 T/R interface circuit pack.
Transmit direction
In the transmit direction, the backplane receive (BPR) interface receives
622 Mbit/s data from the Switch Module and demultiplexes it to byte wide
78 Mbit/s. The overhead processor and synchronizer (OOPS) receives the
data, and processes line and section overhead.
The BPR divides the 311 MHz backplane clock to 19 MHz and uses this as a
reference for the phase-locked loop (PLL) in the backplane driver (BPD).
The electro-optical interface (EOI) receives the signal from the overhead
processor and synchronizer (OOPS). The EOI contains the following circuits:
• SONET transmit (STX) multiplexes the 78 Mbit/s byte wide data from the
OOPS into a 622 Mbit/s, STS-12 data stream.
• A laser driver in the laser module accepts the data stream and generates a
modulation current to drive a laser diode. The laser driver provides a bias
current to maintain the laser diode at the correct threshold.
• The LDM converts the electrical data stream into an amplitude modulated
OC-3 optical output for transmission.
Receive direction
In the receive direction, the photodiode module in the EOI converts the
incoming OC-12 optical signal into an STS-12 electrical signal at 622 Mbit/s.
The SONET receive (SRX) demultiplexes the signal into byte wide 78 Mbit/s
parallel output with a recovered clock and parity.
The OOPS receives the byte wide data from the EOI, processes transport
overhead, and passes the signal to the backplane driver (BPD). The BPD
multiplexes the data to 622 Mbit/s and sends it to the Switch Module by way
of the shelf backplane.

Figure 1-4
OC-12 T/R interface block diagram
DX1374_SONET
From switch
modules A and B
622 Mbit/s
A
311 MHz Clk 78 Mbit/s 78 Mbit/s 622 Mbit/s Laser OC-12
STX module
BPR 8 8
622 Mbit/s
B
311 MHz Clk OOPS EOC
To switch 19 MHz ref EOI

modules A and B
622 Mbit/s
78 Mbit/s 78 Mbit/s 622 Mbit/s Photo
A SRX diode OC-12
311 MHz Clk
8 module
8
BPD
622 Mbit/s
B 311 MHz Clk To/from EOC
TCS Active (green)

Optical signal
fail (yellow)
Fail (red)
To/from
shelf controller
Legend: +3.3 V
-48 V PUPS
BPD = Backplane Driver +5 V
BPR = Backplane Receive
EOC = Electro-Optical Controller
EOI = Electro-Optical Interface
OOPS = Overhead Processor and Synchronizer
PUPS = Point-of-Use Power Supply
SRX = SONET Receive
STX = SONET Transmit
TCS = Transport Control Subsystem

Support circuits
Three circuits support the OC-12 T/R interface:
• the electro-optical controller (EOC)
• the transport control subsystem (TCS)
The EOC monitors control signals from the Rx and Tx channels. The EOC
also interfaces with the TCS processor through a serial interface.
The TCS provides communication between the shelf controller and the OC-12
T/R interface. The TCS also generates alarms and activates the light-emitting
diodes (LEDs) on the circuit pack faceplate.
The PUPS generates all the voltages required by the OC-12 T/R interface.
Figure 1-5
OC-12 T/R interface circuit pack
F3480-192
Optical signal
fail (Yellow)
Fail (Red)
Active(Green)

OC-48 T/R interface (NTCA30)

The OC-48 transmit/receive (T/R) interface is a low-speed tributary T/R
interface, which combines transmit, receive and demultiplex functions in one
circuit pack. The main functions of the circuit pack are to:
• provide OC-48 transmit and receive facility terminations
• process the overhead
This circuit pack features a bottom latch release sensor. The sensor alerts the
system of circuit pack removal, and switches the traffic if the circuit pack is
active and protection is available. Figure 1-6 shows a functional block
diagram. Figure 1-7 shows a view of the OC-48 T/R interface circuit pack.
Transmit direction
In the transmit direction, the backplane receive (BPR) interface receives
OC-48 data in the form of four 622 Mbit/s data streams from each Switch
Module and demultiplexes it. The transmit overhead processor (TOHP)
receives the data and then multiplexes it.
The parallel to serial (P/S) module multiplexes the signal again to provide an
STS-48 serial signal for the laser module. The laser module converts the
OC-48 electrical signal into an OC-48 optical signal and launches it through
optical fiber.
Receive direction
In the receive direction, the avalanche photodiode (APD) converts the
incoming OC-48 optical signal into an electrical signal. The automatic gain
control (AGC) module receives the STS-48 signal and maintains a constant
output level.
The data regenerator module receives the STS-48 serial signal and
demultiplexes it into a parallel STS-48 signal. The receive overhead processor
(ROHP) receives the STS-48 signal. The ROHP finds the SONET frame and
extracts overhead and demultiplexes the data. The synchronizer (SYNC)
module receives and aligns the data with the shelf clock and then passes it to
the backplane driver (BPD). The BPD multiplexes the incoming data then
sends it to the Switch module by way of the shelf backplane.
Support circuits
Three circuits support the OC-48 T/R interface:
• the receive (Rx) controller

The Rx controller samples the quality of the data streams and controls the
phase adjustment of the data and the APD bias. The Rx controller also
provides the TCS with status information.
The TCS controls the operation of the OC-48 T/R interface. The TCS provides
communication between the shelf controller and the OC-48 T/R interface. The
TCS also generates alarms and activates the LEDs on the circuit pack
faceplate.
Figure 1-6
OC-48 T/R interface block diagram
DX1375_SONET
From Switch Modules

A and B
A
P/S STS-48 Laser
4 x 622 Mbit/s BPR TOHP module module OC-48
B
Active
(green)
TCS+ Optical signal fail
(yellow)
Fail
(red)
Rx
Control
To/from
shelf controller
A
Data To Switch
APD AGC SYNC BPD Modules
OC-48 regenerator ROHP module
module module module A and B
module B
STS-48
Legend:
APD = Avalanche Photo-Detector +12V
AGC = Automatic Gain Control -12V
BPD = Backplane Driver -48 V PUPS +3.3V
BPR = Backplane Receive +5V
PUPS = Point-of-Use Power Supply -5.2V
ROHP = Receive OverHead Processor
TOHP = Transmit Overhead Processor
SYNC = Synchronizer

Figure 1-7
F5275-MOR_R70
LOS blue band (yellow)
LOS red band (yellow)
Fail (red)
Active (green)
Optical connector
(Output)
Optical connector
(Intput)

STS-48 T/R electrical interface (NTCA34)

The STS-48 T/R electrical interface is a low-speed tributary transmit/receive
(T/R) interface which combines STS-48 transmit, receive and demultiplex
functions into one circuit pack. The main functions of the circuit pack are to:
• provide STS-48 transmit and receive facility terminations
• process the overhead
Figure 1-8 shows a functional block diagram. Apart from the external label,
the Tx/Rx interface circuit pack looks identical to the OC-48 T/R interface
circuit pack shown in Figure 1-7.
Transmit direction
In the transmit direction, the backplane receive (BPR) interface receives data
from the DX65 Switch module and demultiplexes it. The transmit overhead
processor (TOHP) receives multiplexes and the data. The P/S module
multiplexes the signal again to provide an STS-48 serial signal which it sends
through a coaxial link.
Receive direction
The automatic gain control module (AGC) receives the STS-48 signal and
maintains a constant output level. The data regenerator module receives this
serial signal and demultiplexes it to a parallel signal. The ROHP receives the
STS-48 signal and finds the SONET frame. The ROHP also extracts overhead
and demultiplexes the data. The SYNC module receives and aligns the data
with the shelf clock, then passes the data to the BPD. The BPD multiplexes
the incoming data before sending it to the DX65 Switch module by way of the
shelf backplane.
Support circuits
Three circuits support the STS-48 T/R interface:
• the Rx controller
• the TCS
• the PUPS
The Rx controller samples the quality of the data streams and controls the
phase adjustment of the data. The Rx controller also provides the TCS with
status information.
The TCS controls the operation of the STS-48 T/R interface and TCS provides
communication with the shelf controller. The TCS also generates alarms and
activates the LEDs on the circuit pack faceplate.
The PUPS generates all the voltages required by the STS-48 T/R interface.

Figure 1-8
STS-48 T/R interface block diagram
DX1369_SONET
4
A
4 x 622 Mbit/s
from Switch BPR P/S STS-48
TOHP module
modules A and B
B
4
Active
(green)
TCS+ Optical signal fail

(yellow)
Fail
(red)
RX
control
To/from
shelf controller
4
A
STS-48 Data 4 x 622 Mbit/s
AGC ROHP SYNC BPD to Switch
module regenerator module module
module modules A and B
B
4
Legend:
AGC = Automatic Gain Control
BPD = Backplane Driver
BPR = Backplane Receive
FEC = Forward Error Correction +12V
P/S = Parallel to Serial -12V
PUPS = Point-of-Use Power Supply -48 V PUPS +3.3V
ROHP = Receive Overhead Processor +5V
TCS = Transport Control Subsystem -5.2V
TOHP = Transmit Overhead Processor
SYNC = Synchronizer

OC-192 T/R interface (NTCA06)

Note: The OC-192 T/R circuit pack is used in OPTera Connect DX bays
only.
The OC-192 transmit/receive (T/R) interface circuit pack transmits and

receives aggregate OC-192 traffic signals. 40 different variants of the circuit
pack provide 40 optical wavelength options (see “Variants”).
In the receive direction, the main functions of the OC-192 T/R are to:
• receive optical OC-192 traffic from the line and convert the traffic data to
an STS-192 electrical signal
• remove the overhead bytes and demultiplex the electrical traffic data into
16 STS-12 (622 Mbit/s) data streams
• pass the 16 data streams through the backplane to the Switch modules.
In the transmit direction, the main functions of the circuit pack are to:
• receive 16 STS-12 data streams through the backplane from the Switch
modules
• multiplex the data streams up to the STS-192 data rate and insert the
overhead bytes
• convert the signal from electrical to optical form and transmit the signal as
OC-192 to the line
A microcontroller performs the control and monitoring functions for the T/R
circuit pack and communicates with the shelf controller. An electro-optical
controller (EOC) controls the electrical and optical functions in the circuit
pack.
The circuit pack contains a motherboard and daughterboard. The motherboard

is the transmitter receiver digital assembly (TRDA). The daughterboard is the
optical transmit receive (OTR) circuit. Figure 1-9 shows a block diagram of
the OC-192 T/R circuit pack. Figure 1-10 shows an external view of the circuit
pack.
TRDA
The TRDA contains the following functional blocks:
• Synchronization driver receiver (SYDR)
• Transmit receive overhead processor (TROHP)
• 622 MHz voltage controlled crystal oscillator (VCXO)
• System clock generator (SCG)
• Transmit control subsystem (TCS)
• modulator

SYDR
Four SYDR circuits provide a total of 16 STS-12 (622 Mbit/s) T/R interfaces,
each SYDR containing four interfaces.
In the transmit direction, the function of the SYDR is to:

• receive data through the backplane bus from either of the DX65 Switch
modules A or B,
• locate the frame in the incoming data and descramble the data streams,
• perform forward error correction (FEC) and arrange the overhead (OH)
bytes.
• pass the data to the TROHP as 32 311 Mbit/s data streams with a clock
signal.
In the receive direction, the SYDR:
• accept 32 311 Mbit/s data streams from the TROHP with a 311 MHz
clock.
• locate the frame in the incoming data and descramble the data streams
• perform error correction and arrange the OH bytes
• arrange the data into 16 622 Mbit/s data streams and pass the data to the
backplane bus to the DX65 Switch modules.
TROHP
The TROHP performs overhead processing in both the transmit and receive
directions.
In the transmit direction the function of the TROHP is to:

• receive 32 311 Mbit/s data streams from the four SYDRs and perform
frame location and parity checking
• descramble the incoming data streams and convert the data from STS-12
to STS-192 format.
• generate and insert line and section overhead information and scramble the
data
• convert the data to eight 1.2 Gbit/s data streams and pass the data to the
multiplexer driver on the OTR circuit.
In the receive direction the function of the TROHP is to:
• receive eight 1.2 Gbit/s data streams from the multiplexer driver on the
OTR circuit.
• perform frame location and parity checking
• descramble the data streams
• calculate line and section errors and extract the K-bytes
• extract the overhead bytes

• format the data into 32 311 Mbit/s data streams and pass the data to the
SYDR circuits
• generate a 39 MHz clock which drives a phase detector.
VCXO
The VCXO provides the master clock signal for the system clock generator.
System clock generator (SCG)
The SCG functions as a transmit clock generator. The SCG receives a 39 MHz
clock signal from each of the Switch modules and a 622 MHz clock from the
VCXO. The circuit provides a differential phase output to lock the VCXO.
The SCG also provides clock signals of 39 MHz and 622 MHz for the SYDRs.
Clock selection circuit
In this application, the clock selection circuit defaults to selection of the
39 MHz clock signal from the SCG. The output from the circuit drives a phase
detector, which provides a control output for the 10 GHz PLL on the OTR.
OTR
The OTR contains the following functional blocks:
• T/R optical assembly
• 1:8 demultiplexer
• Electro-optical controller (EOC)
• 8:1 multiplexer
• phase-locked loop (PLL)
• Continuous wave (CW) laser
T/R optical assembly
The T/R optical assembly receives an optical OC-192 signal from the line and
converts it to an electrical signal using a photodiode. A low noise preamplifier
then amplifies the signal to provide the STS-192 output to the demultiplexer
module.
Demultiplexer module
The demultiplexer module receives STS-192 traffic data from the T/R optical
assembly and recovers a clock signal from the incoming data. The recovered
clock signal clocks the 1:8 demultiplexer, producing 8-bit wide data at
1.2 Gbit/s. The module passes the eight data streams to the TROHP on the
TRDA motherboard. The module also performs automatic gain control (AGC)
on the incoming data.
Multiplexer driver
The multiplexer driver module contains a multiplexer and a driver. The
multiplexer part multiplexes the 8-bit wide data from the TROHP into a single
10 Gbit/s (STS-192) data stream. The driver part of the module then amplifies
the signal and passes it to the modulator.

Modulator
The modulator receives the output signal from the multiplexer driver module
and modulates this signal onto the light source from a CW laser. The optical
wavelength of the laser depends on the variant of OC-192 T/R circuit pack
fitted. The modulator transmits the signal with enough power to launch the
signal through 80 km of optical fiber.
PLL
The PLL circuit provides the 10 GHz line timing for the multiplexer driver
module. The control input for the PLL is from the phase detector circuit on the
TRDA.
Dither
The analog maintenance (AM) dither signal is a low frequency signal which is
modulated into the laser output. The signal consists of a transmitted pattern
representing the optical power level. The AM dither signal is recovered at the
receiving end, where it is used to set the optical power of the outgoing signal
to the correct level.
To reduce the occurrence of crosstalk with certain optical frequencies, two AM

dither frequency options are provided: designated AM1 and AM2.
Support circuits
Three circuits support the OC-192 T/R circuit pack:
• electro-optical controller (EOC)
• the TCS
• the PUPS
EOC
The EOC circuit monitors the optical and electrical performance of the
receiver modules and generates alarms. The EOC communicates its status and
the condition of the input signal with the transport control subsystem (TCS)
through a serial link. The TCS monitors this information and reports to the
shelf controller (SC) if necessary. The EOC also stores calibration data.
PUPS
TCS
The TCS controls the operation of the OC-192 T/R circuit pack and allows it
to communicate with the shelf controller. The TCS also generates alarms and
Variants
For information on the variants of this circuit pack and their associated
wavelengths, refer to Ordering Information, 323-1521-151 (OPTera Connect
DX) or 323-1541-151 (OC-192)

Figure 1-9
OC-192 T/R - block diagram
DX0632_SONET
OTR
TCS
CW
EOC Laser
Control
Control
Photo-
OC-192 diode, STS-192 1:8 STS-192 OC-192
8:1 Driver Modulator
preamp, demux mux
AGC
10 GHz
Clock clock (rec)
recovery PLL
d.c. 8 8 EOC
1.2 Gbit/s data
supplies
1.2 GHz clock
1.2 Gbit/s data

1.2 GHz clock
d.c. supplies TRDA
PUPS Phase TCS SC

TROHP
detector
8 8 8 8 8 8 8 8
311 Mbit/s 311 Mbit/s 311 Mbit/s 311 Mbit/s
data data data data
SYDR SYDR SYDR SYDR SCG VCXO
48V d.c. 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
A B A B A B A B
A B
39 MHz
16 x 622 Mbit/s data + 311MHz clocks
to/from Switch Modules A and B
Legend
CW = Continuous wave
EOC = Electro-optical controller
OTR = Optical Transmit Receive
SC = Shelf Controller
SCG = System clock generator
SYDR = Sync driver/receiver
TCS = Transport control subsystem
TRDA = Transmitter receiver digital assembly
TROHP = Transmit/receive overhead processor
VCXO = Voltage controlled crystal oscillator

Figure 1-10
DX0631

OC-192 XR (NTCA04)
Note: The XR circuit pack can only be used in OC-192 regenerator bays.
The OC-192 XR is a single regenerator interface which receives an OC-192

optical signal and processes the section overhead. The circuit also inserts the
overheads into the outgoing payload. The XR multiplexes the data to a single
serial STS-192 data stream and then converts this data stream to an optical
OC-192 signal. The XR transmits the signal with enough power to drive
80 km of stream mode, seamless messaging (SM) optical fiber.
The function of the OC-192 XR circuit pack is to:

• receive OC-192 optical signals and demultiplex to 1.2 Gbit/s buses to the
transmit receive overhead processor (TROHP)
• extract section overhead bytes
• transmit overhead bytes through the second generation transport control
subsystem (TCS+) to the regenerator in the opposite direction
• insert the section overhead into the outgoing data
• support through timing
• multiplex 311 MHz, 32-bit wide data to serial STS-192
• convert serial STS-192 to optical OC-192 with 1528 nm to 1560 nm
wavelengths, positive or negative chirp
• transmit the optical output signal with enough power to drive 80 km of
optical fiber
The XR circuit pack also provides the following features:
• support downloadable firmware and software
• generate alarm indication signal (AIS) under input failure
conditions—green, red and yellow faceplate LEDs
• provide unit control and maintenance at the TCS+, that also has a bottom
latch release sensor
• provide software provisionable output power and chirp polarity using the
Equipment menu of the NE UI
• provide editable circuit pack wavelength using the Equipment menu of the
NE UI
See Figure 1-11 for a functional block diagram of the OC-192 XR. See
Figure 1-12 for a diagram of the OC-192 XR.

Support circuits
The following circuits support the OC-192 XR:
• separate electro-optical controllers (EOCs) for electro-optical and
high-speed module control
• the second generation transport control subsystem (TCS+)
• point-of-use power supply (PUPS)
The EOC controls the operation of both the electro-optical module and the
multiplexer driver.
The TCS+ controls the operation of the OC-192 XR. The TCS+ provides
communication between the shelf controller and the XR. The TCS+ also
generates alarms and activates the LEDs on the circuit pack faceplate.
The PUPS generates all the voltages required by the OC-192 XR. The TCS+
monitors the supply voltage levels for lower than normal conditions.

Figure 1-11
OC-192 XR block diagram
DX1383_SONET
10 GHz VCO
Super 1.2 Gbit/s 1.2 Gbit/s MUXDriver STS-192 Electro- OC-192

OC-192 STS-192
ROA Demux TROHP optic
8 8 module
module module
EOC
Active
(green)
TCS+
Fail
(red)
To/from
Legend: Shelf controller
EOC = Electro-Optic Controller +12 V
PUPS = Point-of-Use Power Supply -12V
TCS = Transport Control Subsystem +3.3V
TROHP = Transmit Receive OverHead Processor -48 V PUPS
+5V
ROA = Receive Optical Amplifier
-5V
VCO = Voltage Controlled Oscillator
-12V

Figure 1-12
OC-192 XR circuit pack
F5512-192_R60
LOS (yellow)
Fail (red)
Active (green)
Optical connector
(Output)
Optical connector
(Intput)

OC-192 DWDM transmit interface (NTCA01)

Note: The OC-192 DWDM transmit interface circuit pack is used in the
OC-192 bays only.
The OC-192 DWDM transmit interface aligns with a 100 GHz optical
frequency grid, which is a subset of the complete ITU-T grid. The DWDM
transmit interface receives traffic as sixteen STS-12 serial links from both
Switch modules and transmit these as an OC-192 signal.
The OC-192 DWDM transmit interface is available in 32 different

wavelengths.
The function of the OC-192 DWDM transmit interface is to:

• insert section and line overhead bytes
• encode the overhead for forward error correction (FEC)
• select the data and clock coming from Switch module A or B
• synchronize the data with the system clock
• transmit the OC-192 signal with enough power to drive 80 km of optical
fiber
The OC-192 DWDM transmit interface also provides the following features:
• software provisionable output power and chirp polarity using the
Equipment menu of the NE UI.
• editable circuit pack wavelength using the Equipment menu of the NE UI
screen
See Figure 1-13 for a functional block diagram of the OC-192 DWDM
transmit interface. See Figure 1-14 for a figure of the OC-192 DWDM
transmit interface circuit pack.
Each backplane receiver (BPR) interface receives four groups of four data
streams of 622 Mbit/s STS-12 data from Switch module A or B. The forward
error correction (FEC) circuit receives the sixteen data signals and encodes the
overhead for FEC.

The function of the transmit overhead processor (TOHP) is to:

• descramble the incoming data,
• generate and insert line and section framing bytes
• insert overhead bus information
• scramble the data.
The TOHP then passes the data to the transmit intermediate multiplexer (TIM)
which outputs eight data lines. The multiplexer driver module then converts
the eight data lines to one STS-192 electrical signal. The electro-optical
module then converts the STS-192 electrical signal to an OC-192 optical
signal, and launches the signal through optical fiber.
This circuit pack also features a bottom latch release sensor, which alerts the
system of circuit pack removal.
OC-192 DWDM transmitter wavelengths

For information on the variants of this circuit pack refer to Ordering
Information, 323-1541-151 (OC-192)
For information on the plan of DWDM wavelength allocation, refer to the

Optical Networks Applications documentation suite Issue 9.0 (NTCA66BA).
Support circuits
Three circuits also support the OC-192 DWDM transmit interface:
The EOC controls the operation of both the electro-optical module and
multiplexer driver.
The TCS controls the operation of the OC-192 DWDM transmit interface. The
TCS provides communication between the shelf controller and the OC-192
DWDM transmit interface. The TCS also generates alarms and activates the
LEDs on the circuit pack faceplate.
The PUPS generates all the voltages required by the OC-192DWDM transmit
interface.

Figure 1-13
OC-192 DWDM transmit interface block diagram
DX1370_SONET
4
A 10 GHz VCO
BPR
B
4
16 x 622 Mbit/s from Switch module A
16 x 622 Mbit/s from Switch module B
4
A
BPR
B
4 OC-192
Electro-
MUXDriver STS-192 optic
FEC TOHP TIM module
module
4
A
BPR
B
4
4
A
BPR EOC
B
4
Active
(green)
TCS+ Fail
(red)
Legend:
BPR = BackPlane Receiver
EOC = Electro-Optical Controller
FEC = Forward Error Correction
PUPS = Point-of-Use Power Supply To/from
TCS = Transport Control Subsystem Shelf controller +12 V
TOHP = Transmit OverHead Processor -12V
TIM = Transmit Intermediate Multiplexer +3.3V
VCO = Voltage Controlled Oscillator -48 V PUPS
+5V
-5V
-8V

Figure 1-14
OC-192 DWDM Tx circuit pack
F5514-192_R60
Fail (red)
Active (green)
Optical connector
(Output)

OC-192 DWDM regenerator/transmit interface (NTCA03)

Note: The OC-192 regenerator/transmit interface circuit pack is used in
the OPTera Connect DX (OC-192) regenerator bays only.
The OC-192 DWDM regenerator/transmit (RgTx) interface receives an

STS-192 electrical signal from the OC-192 receive interface and transmits an
OC-192 optical signal. The OC-192 DWDM RgTx interfaces are available
with the same wavelengths as the OC-192 DWDM transmit interfaces.
The function of the OC-192 DWDM RgTx interface is to:

• process the section overhead
• convert the serial STS-192 electrical signal into an optical signal
The OC-192 DWDM RgTx interface also makes available the following
features:
• software provisionable output power and chirp polarity using Equipment
menu of the NE UI.
Note: Only Release 3.0 and above of the OC-192 software load provide
this feature.
• editable circuit pack wavelength using the Equipment menu of the NE UI.
Note: Only Release 3.0 and above of the OC-192 software load provide
this feature.
See Figure 1-15 for a functional block diagram of the OC-192 DWDM RgTx
interface. Except for the external label, the OC-192 DWDM RgTx circuit pack
looks identical to the OC-192 DWDM transmit interface circuit pack shown in
Figure 1-14.
The OC-192 DWDM RgTx interface receives a 32-bit wide 311 Mbit/s
electrical signal from the OC-192 receiver through the shelf backplane. The
circuit outputs the data as sixteen STS-12 data streams.
The TOHP:
• descrambles the incoming data
• generates and inserts section framing bytes,
• inserts overhead information,
• scrambles the data again
• passes the data to the TIM, which outputs eight data lines.
The multiplexer driver module converts the eight data lines to one STS-192
serial signal. The electro-optical module converts the STS-192 electrical
signal to an optical signal, and launches the optical signal through optical fiber.

This circuit pack also has a bottom latch release sensor, which alerts the system
of circuit pack removal.
Support circuits
Three support circuits are also part of the OC-192 DWDM RgTx interface:
The EOC controls the operation of the electro-optical module and multiplexer
driver.
The TCS controls the operation of the OC-192 DWDM RgTx interface. The
TCS provides communication between the shelf controller and the OC-192
DWDM RgTx interface. The TCS also generates alarms and activates the
LEDs on the circuit pack faceplate.
The PUPS generates all the voltages required by the OC-192 DWDM RgTx
interface.
Variants
For information on the variants of this circuit pack refer to Ordering
Information, 323-1541-151 (OC-192)

Figure 1-15
OC-192 DWDM regenerator/transmit interface block diagram
DX1371_SONET
10 GHz VCO
OC-192
311 Mbit/s Electro-
ROHP TOHP MUXDriver STS-192 optic
TIM module
32 module
EOC
Active
(green)
TCS+ Fail
(red)
To/from +12 V
Shelf controller -12V
+3.3V
-48 V PUPS
Legend: +5V
-5V
EOC = Electro-Optic Controller
PUPS = Point-of-Use Power Supply -12V
ROHP = Receive OverHead Processor
TIM = Transmit Intermediate Multiplexer
TOHP = Transmit OverHead Processor
VCO = Voltage Controlled Oscillator

OC-192 short reach receive interface (NTCA02)

Note: The OC-192 short reach interface is used in the OC-192 bays only.
The OC-192 short reach (SR) receive units act as the interface between the
incoming optical signal and the OC-192 demultiplexer.
The OC-192 SR receive interfaces perform the following functions:

• amplify the incoming optical signal
Note: For the SR receive interface, the signal goes into the
positive-intrinsic-negative (PIN) preamplifier module.
• convert the OC-192 optical signal into an STS-192 electrical signal

• demultiplex the STS-192 into a 32-bit wide signal
• provide optical performance information
See Figure 1-16 for a functional block diagram of the OC-192 SR receive
interface. Figure 1-17 shows a view of the OC-192 SR receive interface circuit
pack.
The incoming OC-192 optical signal first goes to the PIN preamplifier module
where the signal converts to an STS-192 electrical signal. The equalizer and
demultiplexer convert the STS-192 signal into eight data streams and transmit
them to the receiver intermediate demultiplexer (RID). The RID accepts these
signals and demultiplexes them to a 32-bit wide STS-192 output. This signal
then goes to the OC-192 demultiplexer through the shelf backplane.
The OC-192 SR also has a bottom latch release sensor, which alerts the system
of circuit pack removal. If the circuit pack is active and protection is available,
the circuit pack switches the traffic.
Support circuits
The following circuits support the OC-192 SR receive interfaces:
• the EOC
• the TCS
• the PUPS
The main functions of the EOC are to:
• generate the alarms, optimize the parameters of the received STS-192
signal (overall gain, clock and data timing, and threshold level),
• monitor the optical and electrical performances of the receiver modules.
The TCS is the on board computer for the supervision of the OC-192 SR
receive interfaces. The TCS provides communication between the shelf
controller and the EOC.

The TCS receives information about the module status, the condition of the
input signal from the EOC and other information. The TCS sends this
information to the shelf controller. The TCS also generates alarms and
The PUPS generates all the voltages required by the OC-192 SR receive
interfaces.
Figure 1-16
OC-192 SR receive interface block diagram
DX1372_SONET
STS-192
to OC-192 Demux
SR Rx Super 32
OC-192 PIN/ STS-192
preamp Equalizer demux RID
module
Active
(green)
EOC TCS+ LOS
(yellow)
Fail
(red)
To/from
Shelf controller
Legend:
EOC = Electro-Optic Controller +12 V
LR Rx = Long Reach Receiver
-12V
RID = Receive Interface Demultiplexer -48 V PUPS +5V
SR Rx = Short Reach Receiver -5V
TCS = Transport Controlled Subsystem -6.5V

Figure 1-17
OC-192 SR receive interface circuit pack
F5513-192_R60
LOS (yellow)
Fail (red)
Active (green)
Optical connector
(Intput)

OC-192 demultiplexer (NTCA05)

Note: The OC-192 demultiplexer is used in the OC-192 bays only.
The OC-192 demultiplexer processes the STS-192 data sent by the receive
interface and sends it to the Switch modules.
The main functions of the OC-192 demultiplexer are to:

• extract the transport overhead and send it to the shelf backplane
• synchronize the incoming signal with the shelf clock
• transmit section data communications channel (SDCC) and line data
communications channel (LDCC) to the shelf backplane.
See Figure 1-18 for a functional block diagram of the OC-192 demultiplexer.
Figure 1-19 shows a view of the OC-192 demultiplexer circuit pack.
Incoming STS-192 data from the OC-192 receive interface goes through the
receive overhead processor (ROHP) which reads and processes the overhead.
The STS-192 signal then splits into STS-48 data streams and goes to the FEC
which performs forward error correction. The synchronization (SYNC)
module receives the data streams and synchronizes them to the shelf clock
before passing them to the BPD. Two identical signals (each equivalent to an
STS-48) from each of the four BPDs, go to the Switch modules through the
shelf backplane.
This circuit pack also features a bottom latch release sensor. The sensor alerts
the system of circuit pack removal, and switches the traffic if the circuit pack
is active and protection is available.
Support circuits
The following circuits support the OC-192 demultiplexer:
• the TCS
• the PUPS
The TCS controls the operation of the OC-192 demultiplexer. The TCS
provides communication between the shelf controller and the different
modules on the OC-192 demultiplexer. The TCS also generates alarms and
The PUPS generates all the voltages required by the OC-192 demultiplexer.

Figure 1-18
OC-192 demultiplexer block diagram
DX1260_SONET
4
A
FEC SYNC BPD
B
4
4
A
FEC SYNC BPD 16 x 622 Mbit/s to
Parallel B
4 Switch module A
STS-192 from
Rx Interface ROHP 16 x 622 Mbit/s to
32 4
A Switch module B
FEC SYNC BPD
B
4
4
A
FEC SYNC BPD
B
4
Active
(green)
TCS+ Fail
(red)
LDCC/SDCC
To/from to OC-192
Shelf controller
Legend:
BPD = Backplane Driver
FEC = Forward Error Correction
LDCC = Line Data Communications Channel
+3.3 V
ROHP = Receive OverHead Processor -48 V +5V
PUPS
SCG = System Clock Generation -5V
SDCC = Section Data Communications Channel -2V
SYNC = Synchronization Module
TCS = Transport Controlled Subsystem

Figure 1-19
OC-192 demultiplexer circuit pack
F3183-2-192
Latch
Fail (Red)
Active (Green)
Latch

Switch module (NTCA26, NTCA24)

The Switch module supports the OC-192 optical units required in add/drop
multiplexer (ADM) configurations. The Switch module performs all the
switching functions required for the OC-192 system. The two Switch
modules, A and B, operate as a working and protection pair in a 1+1
configuration.
This section describes the following Switch modules:

• DX65 Switch module (NTCA26) - this circuit pack is used only in OPTera
Connect DX bays
• Data overhead switch (DOS) Switch module (NTCA24) - this circuit pack
is used only in OPTera Connect DX (OC-192) bays.
Note: The functional architectures of the DX65 and DOS Switch modules
are common to each other and their throughput is the same.
The DX65 Switch module NTCA26 is used with the following circuit pack:
• OC-192 T/R interface (NTCA06)
The DOS Switch module NTCA24 is used in the OC-192 NEs with the
following circuit pack:
• OC-192 DWDM transmit interface (NTCA01)
• OC-192 short reach receive interface (NTCA02)
• OC-192 demultiplexer (NTCA05)
• MOR (NTCA11)
• MOR Plus (NTCA11)
The Switch modules perform the following functions:
• synchronization
• traffic handling
• protection switching
• overhead switching
• other control functions
This circuit pack features a bottom latch release sensor. The sensor alerts the
system of circuit pack removal, and switches the traffic if the circuit pack is
active and protection is available.
A block diagram for the DX65 Switch module and the standard DOS Switch
module is shown in Figure 1-20. Figure 1-21 shows a view of the circuit pack.

Data overhead switch

The main switch processing circuit consists of three data overhead switch
(DOS) stages: first, mid and third (see Figure 1-20). All outputs from the first
DOS stage cross-connect to all inputs of the second stage. The connections
between the mid and third stages are a mirror image of those between the first
and mid stages. The first and third DOS stages perform timeslot interchange
functions, the required interchange pattern being programmed into the
memory of the stage. The mid stage performs the main routing and switching
function.
Synchronization
The Switch module receives three different reference clock signals: two come
from the external synchronization interface (ESI), and one from the other
Switch module. From these three clock signals, the Switch module selects a
reference and locks its local voltage-controlled crystal oscillator (VCXO) to
that clock signal.
The Switch module provides clock and frame signals for the OC-192
demultiplexers and OC-192 transmit interfaces of the main shelf. The Switch
module also performs clock and frame handoff at each input port to align the
data before time slot interchange (TSI). The Switch module also performs
reference switches while maintaining the least possible phase error between
the VCXOs of the two Switch modules.
Traffic handling
The Switch module handles the traffic data passing between the OC-192 T/R
circuit pack and the tributaries. The DX65 Switch has a maximum bandwidth
capacity of 65 Gbit/s of traffic:
• four OC-192 (total 40 Gbit/s) line traffic
• ten OC-48 tributaries (total 25 Gbit/s).
Only a maximum of eight OC-48tributaries are used in this application, so
that the maximum usage is 60 Gbit/s total.
All circuit packs in the main transport shelf operate as working and protection
pairs. There are no unprotected tributaries.
Tributaries
The following rules state the maximum number of working and protection
tributaries for which the Switch module handles traffic:
• a maximum of four working and four protection Quad OC-3 T/R optical
interfaces with no other tributary interfaces present (OPTera Connect DX
bays only)
• a maximum of four working and four protection Quad OC-12 T/R optical
interfaces with no other tributary interfaces present

• a maximum of eight working and eight protection half-height OC-12 T/R

optical interfaces with no other tributary interfaces present (OC-192 NEs
only)
• a maximum of four working and four protection OC-48 T/R optical
interfaces with no other tributary interfaces present
• combinations of working and protection circuit packs, adding up to a
maximum bandwidth of 192 STS-1 signals:
– Quad OC-3 optical (OPTera Connect DX only),
– Quad OC-12 T/R
– OC-12 optical T/R half-height (OC-192 only)
– OC-48 optical T/R
– STS-48 T/R electrical
Note 1: Each working circuit pack of any type must have the same type of
protection circuit pack in the adjacent slot in the shelf.
Note 2: The circuit packs used depend on the shelf configuration.
The data from the tributaries arrives as differential serial STS-12. Each
STS-12 data stream demultiplexes to STS-1 data streams and calculates the
appropriate connection map to perform time slot interchange on the data.
The data multiplexes to its original format before transmitting to the

appropriate transmit interface.
Protection switching
The Switch module calculates and stores appropriate connection map contents
for each possible line or tributary protection switch scenario, according to the
network element configuration. If a line or tributary equipment protection
switch is necessary, the system writes the appropriate DOS connection
memory locations to perform the required protection switch.
When a network protection switch is necessary, the Switch module performs

K-byte processing and insertion. The Switch module also calculates
connection map changes, and updates the connection memories within
SONET protection switching time limits.
Overhead switching
The Switch module also performs overhead switching. To perform overhead
switching, the DOS array uses an overhead connection map instead of a data
connection map. During the overhead time slots, the circuit routes some
internal overhead bytes in the STS-12 data streams along separate paths
through the DOS. Some overhead bytes then arrive at a different destination
to that of the data with which they arrived.

The overhead connection map forms a pair of internal Rx buffers and a pair of
internal Tx buffers. Each frame transmits the content of the Rx buffers over a
pair of receive overhead (RXOH) links. The frame also receives the content of
the Tx buffers over a pair of transmit overhead (TXOH) links. The Switch
module sets up the overhead connection map to switch each set of overhead
bytes of any STS-1 output exiting the DOS.
Other control functions

The Switch module provides other control functions such as to:
• illuminate the front panel green LED when carrying traffic, and extinguish
the LED when traffic fails
• communicate with the microcontroller on the second Switch module
through a dedicated link to exchange status and control information
• communicate with the control shelf through a GraceLAN link
• monitor DOS circuits, phase-locked loop (PLL) and PUPS for failure
• provide an RS-232 debug port for testing and background debug mode
(BDM) port for initial programming
Support circuits
The following circuits support the OC-192 Switch modules:
• the TCS
• the PUPS
The TCS controls the operation of the OC-192 Switch module. The TCS
provides communication between the shelf controller and other circuits on the
Switch module. The TCS also generates alarms and activates the LEDs on the
circuit pack faceplate.
The PUPS generates all the voltages required by the OC-192 Switch module.

Figure 1-20
DX65 and DOS Switch modules functional block diagram
DX1478_SONET
RXOH TXOH
TSI ARRAY
64 x 622 Mbit/s 64 x 622 Mbit/s

from Line interfaces 64 to Line interfaces
(= 4 x STS-192) 64 (= 4 x STS-192)
FIRST MID THIRD

DOS DOS DOS
STAGE STAGE STAGE
32 x 622 Mbit/s 32 x 622 Mbit/s
from Trib interfaces to Trib interfaces
= 8 x STS-48 (max) 32 32 = 8 x STS-48 (max)
= 32 x STS-12 (max) = 32 x STS-12 (max)
= 32 x STS-3 (max) = 32 x STS-3 (max)
(Max available = 64 x STS-12) (Max available = 64 x STS-12)
622 MHz
VCXO
622 MHz, frame
PLL
622 MHz,
frame
ESI A 622 MHz, frame
ESI B
Primary 622 MHz,
From 39 MHz SCG
partner 622 MHz Secondary frame
Switch Timing
interlock SCG 39 MHz To main shelf,
extension shelf
shelf (if used)
Active (green)
PUPS
monitors TCS
Optical signal fail

(yellow)
+12V
+5V Fail (red)
-48V PUPS +3.3V
To/from
-5 V Shelf controller via MX
-12V

Figure 1-21
Switch module circuit pack
F4472-192_R40
Loss of signal (Yellow)
Circuit pack fail (Red)
Active(Green)

MOR (NTCA11)
The multiwavelength optical repeater (MOR) operates in bidirectional
DWDM line amplified systems. Figure 1-24 shows a view of the MOR circuit
pack.
MOR and optical service channel module options

There are three versions of the MOR amplifier circuit pack supported (see
Figure 1-22)
• MOR with 1510 nm optical service channel (OSC), NTCA11AK
• MOR without OSC, NTCA11BK
• 1625 nm OSC, NTCA11CK
Figure 1-22
MOR and OSC unit options
F3752
NTCA11Bx NTCA11Ax NTCA11Cx
λ1B Ch λ1B Ch
• •
• •
• λ4B Ch • λ4B Ch
OSC OSC
λ1510 λ1625
λ1R Ch λ1R Ch λ OSC 1625

• •
• •
• λ4R Ch • λ4R Ch
λ OSC 1510
Description
The MOR contains the following components.
MOR with 1510 nm OSC - NTCA11AK
The MOR with 1510 nm OSC optically amplifies counter-propagating optical
signals which are symmetrically allocated into two wavelength bands: the Red
band and the Blue band. The MOR can amplify a total of sixteen wavelengths
(16 λ), with eight wavelengths (8 λ) assigned to co-propagate in each
wavelength band.
The MOR unit also supports a unidirectional out-of-band 1510 nm OSC for
supervisory purposes. The 1510 nm supervisory channel co-propagates with
the Red band channel.

Add/drop wavelength division multiplexing (WDM) couplers embedded into

the MOR Red band amplifier path provide optical access to the 1510 nm OSC.
Because the OSC integrates into the MOR amplifier gain block, you do not
require external add/drop couplers and optical fiber patches. Support of
integrated 1510 nm OSC option on MOR does not erode loss budgets between
sites. Figure 1-23 shows the functional block diagram of the MOR with
1510 nm OSC.
MOR without OSC - NTCA11BK
This MOR optically amplifies counter-propagating optical signals which are
symmetrically allocated into two wavelength bands: the Red band and the Blue
band. The MOR can amplify a total of sixteen wavelengths (16 λ), with eight
wavelengths (8 λ) assigned to co-propagate in each wavelength band.
The MOR does not include the OSC option.
The block diagram is identical to that of the MOR with 1510 nm OSC
amplifier as shown in Figure 1-23, with the exception that it does not include
the OSC module assembly.
1625 nm OSC - NTCA11CK
The 1625 nm OSC supports a unidirectional out-of-band optical service
channel at 1625 nm for supervisory purposes. You must configure the
1625 nm service channel to co-propagate with the Blue Band channels. The
1625 nm OSC module uses the same platform as the MOR unit, but does not
support the optical amplifier gain blocks provided on the MOR. This unit
version does not support optical amplification or power monitoring
functionality as provided with the MOR circuit pack.
Use the 1625 nm OSC module in conjunction with the MOR with 1510 nm
OSC on limited fiber, route diverse or ring applications where all channels
need to propagate through a single line amplified path. You require external
1550/1625 nm WDM couplers for optical access to OSC at 1625 nm.
The block diagram is identical to that of the MOR with OSC amplifier
(Figure 1-23), except there is no erbium-doped fiber amplifier (EDFA) gain
block module.
MOR EDFA gain block module
The MOR unit is based on a two pump, bidirectional optical amplifier
architecture.
Connectors located on the MOR circuit pack faceplate provide optical signal
access. The connector assignments are Blue In/Red Out and Red In/Blue Out.
The counter-propagating Red and Blue band channels route between the
EDFA module and optical connectors located on the circuit pack faceplate.
The 1510 nm OSC signal designment is to co-propagate with Red Band
channels. Access to the 1510 nm OSC is internal to the MOR.

The EDFA module is the core of the MOR amplifier. The main functions of
the EDFA module are to:
• amplify bidirectional optical signals,
• extract received optical supervisory traffic,
• insert transmitted optical supervisory traffic
• monitor bidirectional input and output signal power.
Each direction of a transmission routes through separate amplifier gain
regions. The input optical signals get energy from a dedicated 980 nm pump
source, producing amplification in both directions. Each optical path includes
WDM splitters and combiners for the pump laser and signal, optical isolator,
and optical gain flattening filters. The Red band gain path also includes a
WDM splitter and combiner for OSC access.
Four PIN photodiodes at the input/output ports of the EDFA gain block module
monitor the power.
MOR motherboard
The motherboard includes a transport control subsystem (TCS), point of use
power supplies (PUPS), and different digital processing components. The
motherboard monitors and controls all MOR functions and acts as the
communication bridge with the OC-192 shelf controller installed in the same
bay.
OSC module
The optional OSC module includes a 1510 nm or 1625 nm transmitter,
receiver, and a service channel overhead processor. This module performs
electro-optical conversion of optical supervisory traffic and routes optical
overhead based data.
Support circuits
The following circuits also support MOR circuit packs and the 1625 nm OSC
circuit pack:
• TCS
• PUPS
The TCS controls the operation of the MOR circuit packs and the 1625 nm
OSC circuit pack. The TCS provides communication between the shelf
processor and other circuits on the MOR circuit packs and the 1625 nm OSC
circuit pack. The TCS also generates alarms and activates the LEDs on the
circuit pack faceplate.
The PUPS generates all the voltages required by the MOR circuit packs and
the 1625 nm OSC circuit pack.

Figure 1-23
MOR block diagram
F3733
EDFA Module
Blue Band Out/ EDFA Red Band Out/

Red Band In & Blue Band In
components
Red Red
Blue Blue Red Blue Red Blue

OSC
λ1510
Out In In Out OSC
λ1510
Optical Optical
Service Service PUPS
Channel Tx Channel Rx
LOS (yellow)
LOS (yellow) TCS Optical Overhead

Faceplate
LED control & DSP Processor
Active (green) -48 V
OOH Bus
Fail (red)
LAN Backplane Interface

Figure 1-24
Typical MOR circuit pack
F5275-MOR_R70
Fail (red)
Active (green)
Optical connector
(Output)
Optical connector
(Intput)

MOR Plus (NTCA11)

MOR Plus provides access to each signal band directly at the faceplate of the
circuit pack. MOR Plus has three optical connectors: input, output, and
common. MOR Plus also has one less WDM coupler than the normal MOR.
Figure 1-29 shows a view of the MOR Plus circuit pack.
The MOR Plus, in comparison to the original MOR, has the following
advantages:
• improved performance in preamplifier and post amplifier applications
• increase in wavelength capacity and reach
• per band dispersion compensation
• improvement in compatibility with future optical networking devices that
includes wavelength add/drop multiplexers (ADM) at line amplifier sites
• optical components can insert into the link without reducing the maximum
supported system reach
MOR Plus circuit pack options
There are four versions of the MOR Plus amplifier circuit pack supported:
• MOR Plus with Blue-Pre/Red-Post amplifier and unidirectional 1510 nm
OSC, NTCA11NK
• MOR Plus with Red-Pre/Blue-Post amplifier and unidirectional 1510 nm
OSC, NTCA11PK
• MOR Plus with Blue-Pre/Red-Post amplifier without unidirectional OSC,
NTCA11JK
• MOR Plus with Red-Pre/Blue-Post amplifier without unidirectional OSC,
NTCA11KK
Description
The MOR Plus amplifier includes the following components:
MOR Plus with Blue-Pre/Red-Post amplifier with 1510 nm OSC - NTCA11NK
The MOR Plus circuit pack provides:
• one bidirectional port (the common port for Blue Input and Red Output
signals)
• two unidirectional ports (Blue Output and Red Input).
The MOR Plus circuit pack also supports a unidirectional out-of-band
1510 nm OSC for supervisory purposes. The 1510 nm supervisory channel
co-propagates with the Red band channel. Add/drop WDM couplers
embedded into the MOR Red band amplifier path provide optical access to the
1510 nm OSC.

As the OSC integrates into the MOR amplifier gain block, you do not require
external add/drop WDM couplers and associated optical fiber patches.
Support of the integrated 1510 nm OSC option on MOR does not erode the
inter-site loss budget. Figure 1-25 shows the block diagram of the MOR Plus.
MOR Plus with Red-Pre/Blue-Post amplifier with 1510 nm OSC - NTCA11PK
This MOR Plus circuit pack provides:
• one bidirectional port (common port for Red Input, Blue Output signals)
• two unidirectional ports (Red Output and Blue Input).
This version of the MOR Plus circuit pack also supports a unidirectional
out-of-band 1510 nm OSC for supervisory purposes. The 1510 nm
supervisory channel co-propagates with the Red band channel. Add/drop
WDM couplers embedded into the MOR Red band amplifier path provide
optical access to the 1510 nm OSC. As the OSC integrates into the MOR
amplifier gain block, you do not require external add/drop WDM couplers and
associated optical fiber patches. Support of the integrated 1510 nm OSC
option on MOR does not erode the inter-site loss budget. Figure 1-26 shows a
block diagram for this type of MOR Plus.
MOR Plus with Blue-Pre/Red-Post amplifier without OSC - NTCA11JK
• one bidirectional port (common port for Blue Input, Red Output signals)
• two unidirectional ports (Blue Output and Red Input).
This version of the MOR Plus does not include the OSC option. The block
diagram is identical to that of the MOR Plus with Blue-Pre/Red-Post and OSC,
except that there is no OSC module assembly. Figure 1-27 shows a block
diagram for this type of MOR Plus.
MOR Plus with Red-Pre/Blue-Post amplifier without OSC - NTCA11KK
• one bidirectional port (common port used for Red Input and Blue Output
signals)
• two unidirectional ports (Red Output and Blue Input).
This version of the MOR Plus does not include the OSC option. The block
diagram is identical to that of the MOR Plus with Red-Pre/Blue-Post and OSC,
except that there is no OSC module assembly. Figure 1-28 shows a block
diagram for this type of MOR Plus.
EDFA gain block module, OSC module, motherboard, and support circuits
MOR Plus internal circuits such as the motherboard, OSC module, and support
circuit packs are like that of the normal MOR circuit pack. The main
difference is that MOR Plus has one less WDM coupler than the normal MOR.

Figure 1-25
MOR Plus with Blue-Pre/Red-Post amplifier and 1510 nm OSC
DX1379
OSC
1510 nm Tx
Red band
Red band post amplifier
input
Red band and

Red 1510 nm OSC
output
Blue
Blue band
input
Blue band
output Blue band
pre amplifier
Legend:
= MOR Plus faceplate connector.
= WDM optical coupler
Figure 1-26
MOR Plus with Red-Pre/Blue-Post amplifier and 1510 nm OSC
DX1380
OSC
1510 nm Rx
Red band
pre amplifier
Red band
Red band and output
1510 nm OSC Red
input
Blue
Blue band
output Blue band
input
Blue band
post amplifier
Legend:

Figure 1-27
MOR Plus with Blue-Pre/Red-Post amplifier and no OSC
DX1378
Red band
Red band post amplifier
input
Red band
output
Red
Blue
Blue band
input
Blue band Blue band
output pre amplifier
Legend:
Figure 1-28
MOR Plus with Red-Pre/Blue-Post amplifier and no OSC
DX1377
Red band
pre amplifier Red band
output
Red band
input
Red
Blue
Blue band
output
Blue band
Blue band input
post amplifier
Legend:

Figure 1-29
Typical MOR Plus circuit pack
F5142-MOR_R70
Fail (red)
Active (green)
Optical connector (blue output)
Optical connector (red input)
Optical connector (common)

Partitioned operations controller

The partitioned operations controller (OPC) has three separate circuit packs:
• OPC controller (NTCA50)
• OPC interface (NTCA52)
• OPC storage (NTCA51AA and NTCA51AB)
If you install a partitioned OPC, the network element control shelf must
contain all three of these circuit packs.
Together, these three circuit packs:

• provide storage and upgrades of software loads
• communicate with the shelf controller circuit pack and maintenance
interface circuit pack
• provide operations, administration, maintenance, and provisioning
(OAM&P) functionality
• allow the control shelf to communicate with the outside world
The OPC storage circuit pack provides one interface for the OPC removable
media (NTCA53).
Figure 1-30 shows the functional block diagram of the OPC.

Figure 1-30
Partitioned operations controller (OPC) block diagram
F3746-192_R21
SCSI bus
OPC To/from
LED driver storage OPC removable
circuit media
OPC storage pack
card presence
Serial Signals 9-pin

OPC RS-232 I/F
NM Ethernet I/F 9-pin
circuit 10 Base T Ethernet I/F
pack 25-pin
LED driver
RS-232
To/from Ethernet
back-plane OPC
controller Maintenance
circuit I/F
pack card presence
Legend:
I/F = Interface
LED = Light emitting
diode
MX = Maintenance
card presence SC exchange
A and B circuit pack
NM = Network
Manager
OPC = Operations
controller
SC = Shelf controller
GraceLan circuit pack
OPC controller MX A SCSI = Small Computer
card presence and System Interface
MX B

OPC controller (NTCA50)

The OPC controller circuit pack provides OAM&P functionality. The OPC
controller communicates with the OPC interface circuit pack, the OPC storage
circuit pack, the shelf controller circuit pack, and the maintenance interface
circuit pack.
Figure 1-31 shows a functional block diagram of the OPC controller.

Figure 1-32 shows a view of the OPC controller circuit pack.
The OPC controller contains the following components:
External communications
The OPC controller circuit pack has one 10BaseT Ethernet connection (using
the backplane) for external communications through the OPC interface circuit
pack.
Internal communications
The OPC controller circuit pack has one 10BaseT Ethernet connection (using
the backplane) for internal shelf controller communications through the
maintenance interface circuit pack. The OPC controller circuit pack also has
buses to communicate with the OPC storage circuit pack and the OPC interface
circuit pack.
LED control
The OPC controller circuit pack drives the LEDs for all three OPC circuit
packs: the OPC controller, the OPC interface, and the OPC storage circuit
pack. The OPC storage circuit pack controls the hard drive activity LED on
the OPC storage circuit pack only.
Point-of-use power supply (PUPS)

The OPC controller circuit pack comes with a point-of-use power supply
(PUPS) that generates all the voltages required for the correct operation of the
unit.

Figure 1-31
OPC controller circuit pack block diagram
F3750-192_R21
Flash
memory
NM
DRAM CPU SC
Port A & B
Green
(active)
Red
(fail)
+3.3V
-48V PUPS
+5V
Legend:
CPU = Central Processor Unit
DRAM = Dynamic Random Access Memory
NM = Network Manager
PUPS = Point of Use Power Supply

Figure 1-32
OPC controller circuit pack
F3757_R21
Fail (Red)
Active(Green)

OPC interface (NTCA52)

The OPC interface circuit pack provides the external customer interfaces for
the control shelf. The OPC also communicates with the maintenance interface
circuit pack, and with the OPC controller circuit pack. Figure 1-33 shows a
functional block diagram. Figure 1-34 shows a view of the OPC interface
circuit pack.
The OPC interface contains the following components:
External communications
The OPC interface circuit pack has three ports on its faceplate:
• one 9-pin RS-232 interface for X.25 communication
• one 25-pin RS-232 interface for printer, terminal, and modem support
• one 10BaseT Ethernet port
The OPC controller has an Ethernet bus and a serial processor extension bus to
communicate through the backplane with the OPC controller circuit pack.
LED control
The OPC controller circuit pack controls the faceplate LEDs of the OPC
interface circuit pack.
Point-of-use power supply

The OPC interface circuit pack is equipped with a point-of-use power supply
(PUPS) that generates all the voltages required for the correct operation of the
unit.

Figure 1-33
OPC interface block diagram
F3748-192_R21
9-pin
RS-232
Tx/Rx 25-pin
To/from
backplane Transformer RS-232
9-pin
10BaseT Ethernet
Tx/Rx
control
Green To/from
From (active) OPC controller
LED
OPC FPGA
input Red To/from
controller
(fail) MI
-48V PUPS +5V
Legend:
FPGA = Field Programmable Gate Array
LED = Light Emitting Diode
MI = Maintenance Interface
OPC = Operations Controller
Rx = Receive
Tx = Transmit

Figure 1-34
OPC interface circuit pack
F3760_R21
9-Pin X.25 RS-232

connector
25-Pin RS-232
connector
9-Pin 10 Base T
Ethernet connector
Fail (Red)
Active (Green)

OPC storage (NTCA51AA and NTCA51AB)

The OPC storage circuit pack includes a small computer system interface
(SCSI) drive, electrically erasable programmable read-only memory
(EEPROM), and a removable media interface. There are two types of OPC
storage circuit pack:
• Hard disk drive (NTCA51AA)
• Solid state disk drive (NTCA51AB)
Both types of circuit pack support the OPC removable media NTCA53.
Figure 1-35 shows a functional block diagram of the OPC storage.

Figure 1-36 shows a view of the OPC storage circuit pack.
The OPC storage contains the following components:
Removable media interface

The OPC storage circuit pack provides one interface for the removable media.
The removable media interface provides software download, save, and restore
capabilities for the network element.
The OPC storage circuit pack has a processor bus and a SCSI bus to
communicate through the backplane with the OPC controller circuit pack.
Hard disk drive

The SCSI hard disk drive comes as part of the OPC storage circuit pack for
UNIX applications.
EEPROM
The EEPROM contains information about the OPC storage circuit pack, such
as flash memory size, circuit pack serial number, hardware or software
interface vintage. The EEPROM also contains the product engineering code
(PEC) and Common Language Equipment Identifier (CLEI) code bytes.
LED control
The OPC controller circuit pack controls the faceplate LEDs of the OPC
storage circuit pack. The OPC storage circuit pack controls the hard drive
activity LED on the OPC storage circuit pack only.
Point of use power supply (PUPS)

The OPC storage circuit pack comes with a PUPS that generates all the
voltages required for the correct operation of the unit.

Figure 1-35
OPC storage block diagram
DX1561
OPC storage circuit pack
NVS
Removable To/from
media removable
I/F media
Hard drive Green

OPC (Hard drive
or solid-state
controller activity)
drive
circuit
pack
Green
(active)
LED Yellow
input (card shutdown
in progress)
Red
(card fail)
+5V
-48V PUPS +12V
-12V
Legend:
I/F = InterFace
NVS = Non Volatile Storage
OPC = OPerations Controller

Figure 1-36
OPC storage circuit pack
F3759-192_R60
N
IO
UT
CA
CT
PA R CT ac
k
IM CTO DU it p
cu d
TE PRO this chirandle
DE IVE IT d, is
pe m
NS trip ise
SE en erw ced.
be oth
as or epla
t o r h ped be r
tec op st
de en dr d mu
he n
If t as be a
h
Removable media
interface
Re
m
CA
sh ovin
u UT
th t-d g
Do e o ownOPC IO
no per wil pr N
Ha t re atin l coior to
Sh rd Dmov g sy rrup
utd isk e O ste t
ow Ac PC m.
n
LE In tivitywhe
D is Pro o n
r
lit. gres
s
Sh
utd
ow
n In
Ha Pro
rd gre
Dis
kA ss
cti
vit
y
Card shutdown in
progress (Yellow)
Card fail (Red)
Active (Green)

OPC removable media (NTCA53)

The 122 M/byte OPC removable media provides software download, save, and
restore capabilities for network elements under the OPC span of control.
You insert the OPC removable media in the slot on the faceplate of the OPC
storage circuit pack.
Figure 1-37 shows a view of the OPC removable media.

Figure 1-37
OPC removable media
F3758_R21

Orderwire (NTCA47)
The orderwire facility is only supported in OC-192 NEs. For information on
the orderwire facility, please refer to the Orderwire User Guide, NTCA66CA.
Shelf controller (NTCA41)

The shelf controller (SC) is the central processor for the system.
The main functions of the shelf controller are to:

• report alarms
• support the network element user interface (NE UI)
• provide RS-232 and Ethernet communication ports
• handle data communications channel (DCC) routing
• collect performance monitoring data
• coordinate network element software download and upgrade
See Figure 1-38 for a functional block diagram of the shelf controller.
Figure 1-39 shows a view of the shelf controller circuit pack.
The 32 MBytes RAM SC is used in add-drop multiplexer (ADM)

configurations only. The 16 Mbytes RAM is used in regenerators only.
RS-232 and Ethernet ports

The shelf controller supports two RS-232 ports and one Ethernet port. One
RS-232 port is available through a 25-pin D-subminiature connector located
on the local craft access panel (LCAP). The second RS-232 port, and the
Ethernet port, are available through 9-pin D-subminiature connectors located
on the faceplate of the maintenance interface circuit pack.
The shelf controller communicates with all the circuit packs in the OPTera
Connect DX bay and OC-192 bay. The shelf controller controls alarm
reporting, fault detection, protection, performance monitoring data collection,
and software management.
The shelf controller communicates with the following transport control
subsystem (TCS) based circuit packs supported on the OPTera Connect DX
and OC-192 bays through the message exchange circuit pack:
• OC-12 half-height T/R interface (NTCA31) (OC-192 only)
• Quad T/R interfaces (NTCA33, NTCA36)
• OC-48 T/R interface (NTCA30)
• STS-48 T/R electrical interface (NTCA34)
• OC-192 T/R interface (NTCA06) (OPTera Connect DX bay only)

• OC-192 XR (NTCA04) (OC-192 only)

• OC-192 DWDM transmit interface (NTCA01) (OC-192 only)
• OC-192 DWDM regenerator/transmit interface (NTCA03) (OC-192 only)
• OC-192 short reach receive interface (NTCA02) (OC-192 only)
• OC-192 demultiplexer (NTCA05) (OC-192 only)
• Switch module (NTCA26, NTCA24) (NTCA24 is used in OC-192 only)
• External synchronization interface (NTCA44)
• Orderwire (NTCA47) (OC-192 only)
• MOR (NTCA11) (OC-192 only)
• MOR Plus (NTCA11) (OC-192 only)
The shelf controller also communicates with the OPC circuit packs (through
the maintenance interface circuit pack), the message exchange circuit pack,
and the parallel telemetry circuit pack.
Flash memory
The shelf controller flash memory contains one copy of its software, one copy
of the system provisioning data, and a software library.
You use the software library when you replace a circuit pack. The software
library makes sure that the circuit pack you are inserting runs the appropriate
software version, according to the system’s provisioning data.
Support circuits
The PUPS generates all the voltages required by the shelf controller.

Figure 1-38
Shelf controller block diagram
F3236-192_R21
Filters and Ethernet

Transformers
DRAM
RS-232 (MI)
Buffer RS-232 (LCAP)
RS-530 (MI)
CPU (future)
MI LEDs control
Buffer output bit ports
Flash input bit ports
memory
GraceLan to/from MX A
interface
and MX B
Legend:
CPU = Central Processing Unit
DRAM = Dynamic Random Access Memory
LCAP = Local Craft Access Panel
MX = Message eXchange

Figure 1-39
Shelf controller circuit pack
F3192-192
Fail (Red)
Active(Green)

Maintenance interface (NTCA42)

The maintenance interface (MI) works with the shelf processor. The
maintenance interface circuit pack contains the RS-232 and the Ethernet
interfaces.
Two MI versions are available: the 32 MByte (NTCA42AA) and the

128 MByte (NTCA42BA). The OPTera Connect DX bay supports only the
128 Mbyte MI. The OC-192 bay supports both MI types.
The main functions of the maintenance interface are to:

• provide access to RS-232 and Ethernet interfaces
• support circuit pack inventory
• collect status signals
• monitor processor sanity
• provide interface between the LCAP and the shelf controller
• provide flash memory storage
• drive bay level alarm indicators
• support a software library
• communicate with the OPC
See Figure 1-40 for a functional block diagram of the maintenance interface.
Figure 1-41 shows a view of the maintenance interface circuit pack.
RS-232 and Ethernet

The maintenance interface supports two RS-232 interfaces (A and B) that
comes from the shelf controller. Interface A connects to a male 9-pin
D-subminiature connector located on the faceplate of the maintenance
interface. Interface B connects to the LCAP through the control shelf
backplane.
The maintenance interface provides three Ethernet connections for the

Ethernet port provided by the shelf controller circuit pack. You can access this
Ethernet interface through three 9-pin D-subminiature connectors located on
the faceplate of the maintenance interface.
Circuit pack inventory

The maintenance interface reads circuit pack inventory from the circuit packs
that are not connected to the shelf controller. These circuit packs include the
breaker/filter modules, the LCAP, and the synchronization, alarm, and
telemetry terminations (SATT).

Status signals
Status signals go to the maintenance interface (MI) by the fan modules and the
breaker/filter modules. The MI reports these signals to the shelf controller.
Processor sanity
The maintenance interface monitors the status of the shelf controller that uses
a sanity timer. The shelf controller refreshes the timer every 30 seconds. The
maintenance interface activates major visual and audible alarms if the shelf
processor does not refresh the timer.
LCAP interface
The maintenance interface acts as an interface between the shelf controller and
the LCAP. The maintenance interface detects the alarm cutoff (ACO) and
lamp test signals originated by the LCAP and notifies the shelf controller. The
maintenance interface controls and monitors the state of the relays (located on
the LCAP) that control the ACO circuit.
Flash memory
The flash memory located on the maintenance interface stores a second copy
of the network element shelf controller software and provisioning data. The
flash memory also stores the software library. The first copy in the shelf
controller flash memory is only for shelf controller software and provisioning
data.
Data backup and software storage between the shelf controller and MI allows
replacement of both circuit packs while the system is in service. Do not
replace both circuit packs at the same time.
Use the software library when you replace a circuit pack that contains transport
control subsystems (TCS). The software library makes sure that the circuit
packs you are inserting run the appropriate software version, according to the
system software. The software library also updates with a software upgrade.
Bay alarms
The shelf controller controls the critical, major, and minor alarm relays. Both
critical and minor alarm relays appear on the maintenance interface. The
major alarm relay is on the SATT. The relay raises a major alarm if the
maintenance interface (MI) fails or if you remove the MI.
The shelf controller controls the LEDs on the maintenance interface.
The maintenance interface also comes with a PUPS that generates all the
voltages required for the correct operation of the unit.

Figure 1-40
Maintenance interface block diagram
F3237-192_R21
RS-232 to SC RS-232 DB9 connector on faceplate

Interface
Ethernet to SC
Ethernet
Ethernet to 3 DB9 connectors on faceplate
Interfaces
OPC controller
circuit pack
RS-232 DB25 connector on LCAP

RS-232 to SC Interface
Flash
To/from SC
memory
Alarm status to SATT

ACO to SC ACO/Lamp test
Sanity timer from LCAP
Status Bay I/F

Fans alarms
MI
From SC LEDs
+5 V
-48 V PUPS
To/from SC Inventory -5 V
Legend:
ACO = Alarm Cut Off
I/F = Interface
LCAP = Local Craft Access Panel
SATT = Synchronization, Alarms and Telemetry Terminations

Figure 1-41
Maintenance interface circuit pack
DX1562
RS-232
port
Port 1
10BaseT
Ethernet ports Port 2
Port 3
FW-3187

External synchronization interface (NTCA44)

The external synchronization interface (ESI) provides a 38 MHz reference
output for shelf timing or external timing (1.5 MHz or DS-1). The shelf is
fitted with two ESI circuit packs which operate as a working and protection
pair.
The main functions of the ESI are to:

• provide a stable reference timing source for the system
• provide one 1.5 MHz or DS-1 reference output
See Figure 1-42 for a functional block diagram of the ESI. The ESI circuit
pack looks identical to the circuit pack shown in Figure 1-39.
The building-integrated timing supply (BITS) and OC-192 interfaces provide

timing signals for the ESI (at different rates). The ESI reduces all these input
signals to the rate of 8 kHz. The system monitors the input signals for
frequency and forms a timing reference pool. From the pool of timing
references the ESI selects a reference for timing distribution and generation.
In the event of a source failure, the internal oscillator of the ESI becomes the
reference for timing distribution. The selection does not depend on the source
for the mate ESI.
When the ESI operates in freerun or holdover mode, the internal oscillator of
the ESI generates the timing. If the ESI does not generate the timing it selects
the same reference and both ESIs follow in parallel. The selection of the
timing generation reference does not depend on the selection of the timing
distribution reference.
In freerun or holdover mode, the ESI provides a slave equipment clock (SEC)
output of accuracy 4.6 ppm. The shelf clock located on the Switch module
derives its timing output from the ESI. In the event of failure or removal of
both ESIs, the shelf clock will run in freerun mode with an accuracy of
20 ppm.
The shelf controller controls the LEDs on the ESI through the transport control
subsystem (TCS).
The ESI comes with a PUPS that generates all the voltages required for the
correct operation of the unit.

Figure 1-42
ESI block diagram
F3238
Input from External

input I/F
a BITS
Timing Output DS1 outputs
distribution I/F to SATT
Timing
reference
pool
Timing output to
Input from Backplane Timing Timing switch modules A & B
OC-192 I/F I/F generation filter
Timing output to
mate ESI
Active
(green)
To/from TCS+
mate ESI Fail
(red)
+12 V
-48 V PUPS -12 V
+5 V
-5 V
To/from
shelf controller
Legend:
BITS = Building-Integrated Timing Supply
ESI = External Synchronization Interface
I/F = Interface
SATT = Synchronization, Alarms and Telemetry Terminations
TCS = Transport Controlled Subsystem

Message exchange (NTCA48)

The message exchange (MX) circuit pack routes the data communications
channel (DCC) and enables communications between circuit packs supplied
with a processor. The message exchange also enables communication between
the shelf controller and circuit packs supplied with a processor or transport
control subsystem (TCS). (See Figure 1-43).
Note: You must install at least one MX circuit pack in the control shelf. If
you install two MX circuit packs, one can act as the working circuit pack,
and one can act as the protection circuit pack.
The main functions of the message exchange circuit pack are to:
• support circuit pack presence detection with the shelf controller
• support DCC messaging
• support operations, administration, and maintenance (OAM) messages
between circuit packs supplied with a processor
See Figure 1-44 for a functional block diagram of the MX circuit pack. The
MX circuit pack looks identical to the circuit pack shown in Figure 1-39.
Circuit pack presence

The MX circuit pack stores a CP presence bit for every circuit pack that has a
processor (TCS). The shelf controller reads these bits through the
maintenance interface (MI). If you remove a circuit pack, the shelf controller
detects a change in circuit pack presence and passes this information to the
shelf controller.
The shelf controller controls the LEDs on the message exchange circuit pack.
The message exchange circuit pack also comes with a PUPS that generates all
the voltages required for the correct operation of the unit.
GraceLan/MMSB
GraceLan is the protocol used by the system for both DCC routing and
internal system control messages. System control functions include:
• fault reporting
• performance monitoring
• data collection
• software upgrade
• circuit pack configuration
The GraceLan messaging system connects the SC and the GraceLan nodes
together at the two MX CPs.

The following CPs form GraceLan nodes:

• shelf controller
• ESI
• all CPs in the main shelf
Each GraceLan node has a separate connection to each of the MX CPs
identified by a slot ID number, which identifies its position in the NE.

Figure 1-43
Communications between the MX circuit pack and other circuit packs in the system
F3239-192_R40
MI
OPC-C SC MX G1 MX G2
Circuit Circuit Circuit

OPC-S OPC-I pack 1 pack x pack y
Circuit packs equipped with a processor (TCS)
Legend:
MI = Maintenance Interface module
MX = Message eXchange module
OPC-C = Operations Controller Control module
OPC-I = Operations Controller Input/Output module
OPC-S = Operations Controller Storage module
SC = Shelf Controller module

Figure 1-44
Message exchange block diagram
F3240
Active
To MI S_PEZ
(green)
interface
Fail
(red)
Card 1
GraceLan
interface Selector
Card x
System card
presence to SC
MMSB Control/
To/from SC interface Timing
Timing
To SC distribution
+5 V
Legend:
-48 V PUPS
MI = Maintenance Interface -5 V
MMSB = Multi-Master Serial Bus
S_PEZ = Serial Processor Extension bus

Parallel telemetry (NTCA45)

The parallel telemetry circuit packs provide the interface to the customer’s
central alarm reporting equipment. Relay contact outputs and digital detection
inputs provide access.
The main functions of the parallel telemetry circuit pack are to:
• provide 32 dry contact compatible inputs
• provide eight “Form C” (break before make) relay outputs
Figure 1-45 shows a functional block diagram of the parallel telemetry circuit
pack. Figure 1-46 shows a view of the parallel telemetry circuit pack.
Telemetry input interface

The 32 parallel telemetry inputs connect through a 44-pin D-subminiature
connector located on the circuit pack faceplate. They connect a network
element to the external triggers for events (such as an open door or a high shelf
temperature). The parallel telemetry inputs are active when connected to 0V.
When an open input changes to closed, a trigger trips and the network element
software raises an environmental alarm.
The parallel telemetry circuit pack maps the state of all 32 parallel telemetry
inputs into the shelf controller addressing space.
Telemetry output interface

The parallel telemetry circuit packs access the eight telemetry outputs through
a 25-pin D-subminiature connector located on the circuit pack faceplate. Each
output includes a three wire set: a common connection (COM), normally
opened (NO) signal, and a normally closed (NC) signal.
There are two possible states for each output:

• NC connected to COM and NO floating
• NO connected to COM and NC floating
The parallel telemetry circuit pack maps each of the eight parallel telemetry
outputs into the shelf controller addressing space.
The field programmable gate array (FPGA) controls the circuit pack LEDs.
The parallel telemetry circuit pack also comes with a PUPS that generates all
the voltages required for the correct operation of the unit.

Figure 1-45
Parallel telemetry circuit pack block diagram
F3241
All inputs are

Active Low S_PEZ to/from
shelf controller
input NO
Input Output
I/F I/F COM
1 1
ground NC
FPGA
input NO
Input Output
I/F I/F COM
32 8
ground NC
Active
(green)
Fail
(red)
Legend:
COM = COMmon
FPGA = Field Programmable Gate Array
I/F = InterFace -48 V PUPS +5 V
NC = Normally Closed
NO = Normally Opened
S_PEZ = Serial Processor Extension bus
Note: The parallel telemetry cable has only eight ground pins.
Each input can be grounded to any of the ground pins.

Figure 1-46
Parallel telemetry circuit pack
F3195-192
25-Pin telemetry
output connector
44-Pin telemetry
input connector
Fail (Red)
Active(Green)

Breaker/filter module (NTCA40)

Located in the control shelf, the breaker/filter module accepts three 30 Amp
feeds from the customer power plant. The module provides current limited
power outputs required by the system.
The main functions of the breaker/filter module are to:

• provide low frequency filtering
• balance load for input feeds
• provide seven current limited outputs
• provide a 60 W cooling unit output
See Figure 1-47 for a functional block diagram of the breaker/filter module.
Figure 1-48 shows the breaker/filter module.
Each of the three input feeds has a dedicated filter to prevent battery
oscillation. A low voltage monitor generates an alarm if the voltage of a feed
drops below −41.5 V ± 1.5 V. The three input feeds are current limited by
circuit breakers.
The breaker/filter module can generate filter failures, power losses, trip alarms,
and low voltage warnings. The power on and alarm detection circuits control
the circuit pack LEDs, and communicate with the shelf controller.

Figure 1-47
Breaker module functional block diagram
F3242-192_R40
−48 V to
cooling unit
Circuit
Breaker 2 −48 V to
Low transport shelf
Feed from Filter voltage
power plant monitor
Circuit
transport shelf
Circuit
Low transport shelf
Feed from Filter voltage
power plant monitor
Circuit
transport shelf
Circuit
control shelf
Low
voltage Circuit 48 V to
Feed from Filter Breaker 6
power plant monitor tributary, or dense
regenerator, or line
extension shelf
Circuit
Breaker 7 48 V to
tributary, or dense
regenerator, or line
extension shelf
Active
(green)
Alarm
and Fail
Pwr On (red)
detection
To shelf controller

Figure 1-48
Breaker/filter module
F3191-192
Input feeds
Circuit breaker
switches (7)
Fail (Red)
Active (Green)

Fan module (NTCA85)

The environmental control panel has three fan modules which operate at
approximately 80% of maximum speed under normal conditions. The
temperature threshold set at the factory increases or decreases the speed of the
fan module.
The fan controller monitors all operations of the fan including: speed, state of
the remote temperature sensors, and the reporting of alarms to the shelf
controller. In the event of a failure, the fan controller sends an alarm signal to
the shelf controller and to the other fans.
During normal operation of the unit, a green LED illuminates on the front
panel of the fan. In the event of a failure a Red LED on the front panel of the
fan illuminates.
At low temperatures (below 0ºC), the fan is off. At high temperatures (above
55ºC) the fan operates at a higher speed and signals other fans to increase their
speed. When the sensor temperature exceeds 70ºC, the fan controller sends a
high shelf temperature alarm to the shelf controller.
Figure 1-49 shows a functional block diagram of the fan module. Figure 1-50
shows a view of the fan module.

Figure 1-49
Fan module functional block diagram
F3243
LED control LED control
Fan failed Green/Red

Operations GREEN RED
Fan OK out monitor Fan speed
Control
Fan OK in
High temp (+70°C)

Sensor OK
Sensor Temperature
interface +50oC
0oC
Speed
All fans OK
control
Fan position L
Fan position R
Fan present
Ulog
Supply (-35V -75Vl)
Supply return (GND)

Figure 1-50
Fan module
F3185-2
Fail (Red)
Active (Green)
Lock

Filler card (NTCA49/59)

The filler cards are available in four formats:
• transport shelf, tributary extension shelf, and line extension shelf filler card
(single slot, NTCA49AA)
• transport shelf filler card (double slot, slots 14 and 15 only, NTCA49AB)
• control shelf filler card (single slot, 1 inch, NTCA59AA)
• transport shelf and tributary extension shelf half-height filler card (single
slot, NTCA49AC)
Note: If there is one half-height OC-12 circuit pack in a slot, use a
half-height filler card NTCA49AC for the other half slot. In other cases,
you must use a single slot full-height filler card (NTCA49AA).
All not used, or empty slots in the control shelf, transport shelf, tributary
extension shelf, and line extension shelf must contain the appropriate filler
card. The filler cards have two distinct purposes. The main transport shelf and
the tributary extension shelf require filler cards for correct cooling. The
control shelf requires filler cards to protect against electromagnetic
interference (EMI) emissions.
Filler cards have no LEDs on their faceplate, nor do they contain any internal
circuits. Figure 1-51 shows the four available filler cards.

Figure 1-51
Filler cards
F3526-192_R40
Transport shelf, Transport shelf

tributary extension filler card, double
shelf, dense regenerator slot, slots 14 and 15
extension shelf, and line extension
shelf filler card, single slot
Transport and
Control shelf tributary extension
filler card, shelf half-height filler
single slot card, single slot


Nortel Networks
OPTera Connect DX
Connection Manager
Circuit Pack Descriptions
Copyright ã 2000 Nortel Networks, All Rights Reserved
The information contained herein is the property of Nortel

Networks and is strictly confidential. Except as expressly
authorized in writing by Nortel Networks, the holder shall keep all
information contained herein confidential, shall disclose it only to
its employees with a need to know, and shall protect it, in whole
or in part, from disclosure and dissemination to third parties with
the same degree of care it uses to protect its own confidential
information, but with no less than reasonable care. Except as
expressly authorized in writing by Nortel Networks, the holder is
granted no rights to use the information contained herein.
*Nortel Networks, the Nortel Networks logo, the Globemark, How

the world shares ideas, and Unified Networks are trademarks of
Nortel Networks.
323-1501-102
Standard Rel 1
August 2000
Printed in Canada and in the United Kingdom

1501-102 - Circuit Pack Description

Uploaded by

Copyright:

1501-102 - Circuit Pack Description

Uploaded by

Document Information

Copyright

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

1501-102 - Circuit Pack Description

Uploaded by

Copyright:

323-1501-102

Standard Rel 1 August 2000

Printed in Canada and in the United Kingdom

Circuit pack descriptions 1-1

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

About this document

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

OPTera Connect DX SONET NTP Library

OC-48 NTP Library

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

Circuit pack descriptions 1-

Note 1: In the circuit pack descriptions contained in this chapter, the

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

Table 1-1 (continued)

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

Table 1-1 (continued)

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

Quad T/R interfaces (NTCA33, NTCA36)

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

The electro-optical interface (EOI) circuits perform electrical to optical

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

The TCS+ provides performance monitoring, fault handling, propagation of

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

311 MHz 155 Mbit/s OC-3

155 MHz +5.0V

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

BIBI 622 Mbit/s

311 MHz 622 Mbit/s OC-12

155 MHz +5.0V

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

Dual fiber Side view Front view

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

OC-12 half-height T/R interface (NTCA31)

The OC-12 transmit/receive (T/R) interface is a low-speed T/R tributary

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

To switch 19 MHz ref EOI

TCS Active (green)

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

OC-48 T/R interface (NTCA30)

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

From Switch Modules

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

LOS blue band (yellow)

LOS red band (yellow)

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

STS-48 T/R electrical interface (NTCA34)

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

TCS+ Optical signal fail

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

OC-192 T/R interface (NTCA06)

The OC-192 transmit/receive (T/R) interface circuit pack transmits and

The circuit pack contains a motherboard and daughterboard. The motherboard

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

In the transmit direction, the function of the SYDR is to:

In the transmit direction the function of the TROHP is to:

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

OPTera Connect DX Connection Manager 323-1501-102 Rel 1 Standard Aug 2000

To reduce the occurrence of crosstalk with certain optical frequencies, two AM

Circuit Pack Descriptions 323-1501-102 Rel 1 Standard Aug 2000

1.2 Gbit/s data

d.c. supplies TRDA

PUPS Phase TCS SC