PB0051

Product Brief
RTG4 FPGAs
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55700051. 10.0 7/17

Contents

1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 10.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Revision 9.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Revision 8.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Revision 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.5 Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.6 Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.7 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.8 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.9 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.10 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 RTG4 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Radiation Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 High-Performance FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.3 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.4 High-Speed Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.5 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 RTG4 Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 RTG4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 RTG4 Device Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 High-Performance FPGA Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.1 Dual-Port LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.2 Three-Port uSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.3 uPROM Non-Volatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.4 Mathblocks for DSP Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1 SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 PCI Express (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.3 XAUI/XGXS Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 High-Speed Memory Interfaces: DDR2/3 Memory Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Clock Sources: On-Chip Oscillators, PLLs, and CCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Radiation and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 RTG4 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6.1 Design Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6.2 Design Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.3 IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PB0051 Product Brief Revision 10.0 iii

Figures

Figure 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PB0051 Product Brief Revision 10.0 iv

Tables

Table 1 RTG4 FPGA Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

PB0051 Product Brief Revision 10.0 v

Revision History

1 Revision History

The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.

1.1 Revision 10.0

The following is a summary of changes made in revision 10.0 of this document.
• For the CQ352 package, the MSIO and total number of user I/O are updated. For more information,
see Table 1, page 4.
• Updated the RTG4 FPGA Block Diagram. For more information, see Figure 1, page 5.

1.2 Revision 9.0

The following was a summary of changes made in revision 9.0 of this document.
• Radiation Tolerance, page 3 is updated.
• Added CQ352 package details in Table 1, page 4.
• Added packages and package type entries in Figure 2, page 6.
• High-Performance FPGA Fabric, page 7 is updated for the number of asynchronous resets that are
supported in RTG4 devices.
• Removed the supported rank memory and DRAM burst length of two under High-Speed Memory
Interfaces: DDR2/3 Memory Controllers , page 8.

1.3 Revision 8.0

The following was a summary of changes made in revision 8.0 of this document.
• Removed reference to RT4G075 device (SAR 70694).
• Table 1, page 4 was updated for uPROM kbits (SAR 66983).
• Specifications, page 4 updated for LVDS I/O standards information (SAR 69465).
• RTG4 Device Block Diagram, page 5 was updated (SAR 70694).

1.4 Revision 7.0

Figure 1, page 5 and uPROM Non-Volatile Memory, page 7 were updated (SAR 66992).

1.5 Revision 6.0

The following was a summary of changes made in revision 6.0 of this document.
• Removed all references to the RT4G200 device and the CG/LG2092 package.
• Added User I/Os break-down information to Table 1, page 4.
• Added software, hardware and IP information to the RTG4 Development Tools, page 9.
• Removed the Device Status table (Table 2) and replaced it with the DS0131: RTG4 FPGA Datasheet
as a reference.
• Removed two references to the SII bus.(SAR 65824).

1.6 Revision 5.0

Table 1, page 4 was updated (SAR 62641) and minor language edits were made.

1.7 Revision 4.0

Added TM symbol to RTG4 logo.

1.8 Revision 3.0

Clarified Military temp testing in RTG4 Device Block Diagram, page 5 and space environments in the
RTG4 Device Family Overview, page 7.

PB0051 Product Brief Revision 10.0 1

Revision History

1.9 Revision 2.0

High-Performance FPGA, page 3 updated. Total SRAM information updated in Table 1, page 4.

1.10 Revision 1.0

Revision 1.0 is the first publication of this document.

PB0051 Product Brief Revision 10.0 2

RTG4 FPGAs

2 RTG4 FPGAs

RTG4™ FPGAs integrate Microsemi’s fourth-generation flash-based FPGA fabric and high-performance
interfaces such as SerDes on a single chip while maintaining the resistance to radiation-induced
configuration upsets in the harshest radiation environments such as space flight (LEO, MEO, GEO, HEO,
and deep space); high-altitude aviation, medical electronics, and nuclear power plant control. The RTG4
family offers up to 151,824 registers, which are hardened by design against radiation-induced SEUs.

2.1 Features and Benefits

Following are the features supported in RTG4 FPGAs:

2.1.1 Radiation Tolerance

• Configuration memory upsets immunity to LET > 103 MeV.cm2/mg
• Single-event latch-up (SEL) immunity to LET > 103 MeV.cm2/mg
• SEU-hardened registers eliminate the need for triple-module redundancy (TMR)
• Immune to single-event upsets (SEU) to LET > 37 MeV.cm2/mg
• SEU rate < 10-12 errors/bit-day (GEO Solar Min)
• SRAM has a built-in error detection and correction (EDAC)
• Upset rate < 10-11 errors/bit-day (GEO Solar Min)
• Single error correction and double error detection (SECDED)
• Single-event transient (SET) upset rate < 10-8 errors/bit-day (GEO Solar Min) with optional SET filter
• Total ionizing dose (TID) > 100 Krad

2.1.2 High-Performance FPGA

• Efficient 4-input look-up tables (LUTs) with carry chains for high system performance up to
300 MHz without SET filter
• 209 blocks of dual-port 24.5 kbit SRAM (Large SRAM) with 300 MHz synchronous performance
(512 × 36, 1 kbit × 18, 2 kbit × 9, and 2 kbit × 12)
• 462 DSP mathblocks with 18-bit × 18-bit input signed multiplication and 44-bit output accumulator
• High-performance, 300 MHz (without SET filter) across military temperature: –55 C to 125 C
• Up to 16 spacewire clock and data recovery circuitry instances, allowing high-performance
spacewire interface up to 400 Mbit/sec.
Note: The spacewire interface protocol is not included but can be implemented in the FPGA fabric.

2.1.3 High-Speed Serial Interfaces

Up to 24 Lanes of 3.125 Gbps serialization/deserialization (SerDes) supporting:
• XGXS/XAUI extension (to implement a 10 Gbps XGMII Ethernet PHY interface)
• Native SerDes interface facilitates implementation of serial rapidIO (SRIO) in FPGA fabric or an
SGMII interface to a soft Ethernet MAC
• PCI express (PCIe) Gen1 hard IP core
• ×1, ×2, and ×4 lane(s) PCI express core
• Up to 2 Kbytes maximum payload size
• 64-/32-bit AXI/AHB master and slave interfaces to the application layer

2.1.4 High-Speed Memory Interfaces

Up to two high-speed DDR2/DDR3 memory controllers supporting:
• DDR2 and DDR3 at 333 MHz (667 Mbps) and LPDDR at 266 MHz (533 Mbps) at the maximum clock
rate
• EDAC option with SECDED
• ×9, ×12, ×18, and ×36 bus widths

PB0051 Product Brief Revision 10.0 3

RTG4 FPGAs

2.1.5 Specifications
• 1.2 V nominal core voltage
• Single-ended I/Os—LVCMOS 1.2 V to 3.3 V, LVTTL, and PCI
• Voltage reference I/Os with performance at 600+ Mbps
• SSTL2, SSTL18, SSTL15, HSTL18, HSTL15
• True LVDS (600+ Mbps) differential receiver and true current-mode driver, with a built-in termination
• Clock sources include high-precision 50 MHz embedded RC oscillator
• 8 clock conditioning circuits (CCCs) with PLLs
• Frequency: input 1 to 200 MHz and output 20 to 400 MHz
The following table lists the peripherals and features of RTG4.

Table 1 • RTG4 FPGA Product Family

Peripherals Features RT4G150

Packages CCGA/CLGA1657 CQ352
Logic/DSP Maximum logic elements (LUT4 + TMR flip-flop)1 151,824 151,824
Mathblocks (18-bit × 18-bit) 462 462
Radiation-tolerant PLLs 8 8
Memory LSRAM 24.5 kbit blocks 209 209
uSRAM 1.5 kbit blocks 210 210
Total SRAM Mbits 5.2 5.2
uPROM kbits 374 374
High-Speed Interface SerDes lanes 24 24
PCIe endpoints 2 1
DDR SDRAM controllers With ECC 2 0
SpaceWire clock and data recovery circuits 16 4
User I/Os MSIO (3.3 V) 240 166
MSIOD (2.5 V) 300 0
DDRIO (2.5 V) 180 0
Total User I/Os (Non-SerDes) 720 166
1. The maximum number of logic elements may vary based on the utilization of DSP and memories in the design.

PB0051 Product Brief Revision 10.0 4

RTG4 FPGAs

2.2 RTG4 Device Block Diagram

The following figure shows the RTG4 FPGA block diagram.
Figure 1 • Block Diagram

PB0051 Product Brief Revision 10.0 5

RTG4 FPGAs

2.3 RTG4 Ordering Information

The following figure explains the various ordering codes.
Figure 2 • Ordering Information
RT4G150 _ 1 CG 1657 B

Screening Level
ES = Engineering Sample; not for Space Flight or
Qualification of Space-Flight Hardware
MS = MIL Temp Engineering Sample; not for Space
Flight or Qualification of Space-Flight Hardware
PROTO = Prototype Unit; not for Space Flight or Qualification
of Space-Flight Hardware
B = Military-STD-883 Class B
E = Extended Flow
EV = MIL-PRF-38535 Class V Equivalent
V = MIL-PRF-38535 Class V

Package Lead Count

1657 is available for CB/CG/LG packages
352 is available for CQ package

Package Type
CB = Ceramic Ball Grid Array (Only Available for ES, MS, and PROTO Units)
CG = Ceramic Column Grid Array (1.0 mm pitch)
LG = Ceramic Land Grid Array
CQ = Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
1 = 15 % Faster than Standard Speed

Part Number (Digits Indicate Approximate Number of LUTs in Thousands)

RT4G150

Contact your local Microsemi SoC Products Group representative for device availability. For more
information about device status, see DS0131: RTG4 FPGA Datasheet.

PB0051 Product Brief Revision 10.0 6

RTG4 Device Family Overview

3 RTG4 Device Family Overview

RTG4 FPGAs integrate Microsemi’s fourth-generation flash-based FPGA fabric and high-performance
interfaces such as SERDES on a single chip while maintaining the resistance to radiation-induced
configuration upsets in the harshest radiation environments such as space flight (LEO, MEO, GEO, HEO,
and deep space); high-altitude aviation, medical electronics, and nuclear power plant control. The RTG4
family offers up to 151,824 registers, which are hardened by design against radiation-induced SEUs.
Each RTG4 logic element includes an LUT4 with fast carry chains providing high-performance FPGA
fabric up to 300 MHz. There are multiple embedded memory options and embedded
multiply-accumulate blocks for digital signal processing (DSP) up to 300 MHz. A high-speed serial
interface provides 3.125 Gbps native SerDes communication, while double data rate
DDR2/DDR3/LPDDR memory controllers provide high-speed memory interfaces.

3.1 High-Performance FPGA Fabric

Built on 65nm process technology, the RTG4 FPGA fabric is composed of the logic module, LSRAM,
uSRAM, and mathblocks. The logic module is the basic logic element and supports the following
advanced features:
• A fully permutable 4-input LUT optimized for lowest power
• A dedicated carry chain based on carry look-ahead technique
• A separate SEU-hardened flip-flop that can be used independently from LUT. Each flip-flop has its
own synchronous reset. There are up to 206 asynchronous resets that drive RTG4 flip-flops devices.
The 4-input LUTs can be configured either to implement a 4-input combinatorial function or to implement
an arithmetic function, where the LUT output is XORed with the carry input to generate the sum output.

3.1.1 Dual-Port LSRAM

The LSRAM block is targeted for storing large amounts of data for use with various operations. Each
LSRAM block can store up to 24,576 bits. It contains Port A and Port B data ports. The LSRAM block is
synchronous for both read and write operations. Operations are triggered on the rising edge of the clock.
The data output ports of the LSRAM have pipeline registers, which have control signals that are
independent of the SRAM’s control signals.

3.1.2 Three-Port uSRAM

The uSRAM block is the second type of SRAM block that is embedded in the fabric of the RTG4 devices.
The uSRAM block is a 3-port SRAM; it has Port A and Port B ports for read operations and Port C port for
write operations. The two read ports are independent of each other and can perform read operations in
both synchronous and asynchronous modes. The write port is always synchronous. The uSRAM block
can store up to 1,536 bits. These uSRAM blocks are primarily targeted for building embedded FIFOs to
be used by any embedded fabric master. The uSRAM block can also be used to store DSP coefficients.

3.1.3 uPROM Non-Volatile Memory

uPROM is a non-volatile flash memory, which uses the same flash technology as the FPGA configuration
cells. uPROM is immune to memory upsets and has a TID performance beyond 100 krad, similar to the
FPGA flash configuration cells. RTG4 devices have up to 374 kbits of uPROM memory. uPROM can be
used for power-on initialization of RAMs and embedded IPs, as well as storage for DSP coefficients. The
uPROM has a read performance of 50 MHz.

3.1.4 Mathblocks for DSP Applications

The fundamental building block in any DSP algorithm is the multiply accumulate (MACC) function. The
RTG4 FPGA device implements a custom 18-bit ×18-bit MACC (18 × 18 MACC) block for efficient
implementation of complex DSP algorithms such as finite impulse response (FIR) filters, infinite impulse
response (IIR) filters, and fast fourier transform (FFT) for filtering and image processing applications.

PB0051 Product Brief Revision 10.0 7

RTG4 Device Family Overview

Each mathblock has the following capabilities:

• Supports 18 × 18 signed multiplications natively (A[17:0] × B[17:0])
• Supports dot product; the multiplier computes: (A[8:0] × B[17:9] + A[17:9] × B[8:0]) × 29
• Built-in addition, subtraction, and accumulation units to combine multiplication results efficiently
In addition to the basic MACC function, DSP algorithms typically need small amounts of RAM for
coefficients and larger RAMs for data storage. RTG4 uSRAMs are ideally suited to serve the needs of
coefficient storage while the LSRAMs are used for data storage.

3.2 High-Speed Serial Interfaces

3.2.1 SerDes Interface
RTG4 has up to six 3.125 Gbps quad SerDes transceivers, each supporting the following:
• Four SerDes/EPCS lanes (24 total SerDes lanes)
• The native SerDes interface facilitates implementation of SRIO in fabric or a 10 Gigabit media
independent interface (SGMII) for a soft Ethernet MAC.

3.2.2 PCI Express (PCIe)

PCIe is a high-speed, packet-based, point-to-point, low pin count, and serial interconnect bus. The RTG4
family has embedded high-speed serial interface blocks. Each SerDes block contains a PCIe system
block. The PCIe system is connected to the SerDes block and following are the main features supported:
• Supports ×1, ×2, and ×4 lane configuration
• Endpoint configuration only
• PCI Express Base Specification Revision 2.0 (at Gen1 rate of 2.5 Gbps only)
• 2.5 Gbps compliant
• Embedded receive (2 KB), transmit (1 KB), and retry (1 KB) buffer dual-port RAM implementation
• Up to 2 kbytes maximum payload size
• 64-bit AXI or 32-bit/64-bit AHBL Master and Slave interface to the application layer
• 32-bit APB interface to access configuration and status registers of PCIe system
• Up to 3 × 64 bit base address registers
• One virtual channel (VC)

3.2.3 XAUI/XGXS Extension

The XAUI/XGXS extension uses four SerDes channels, operating at 3.125 Gbps to allow the user to
implement a 10 Gbps (XGMII) Ethernet PHY interface by connecting the XGMII fabric interface through
an appropriate soft IP block in the fabric.

3.3 High-Speed Memory Interfaces: DDR2/3 Memory

Controllers
RTG4 devices can have up to two fabric DDR (FDDR) subsystems in them. Each subsystem consists of
a DDR controller, PHY, and a wrapper. Each FDDR block provides an interface to/from the FPGA fabric.
The following are the main features supported by the FDDR blocks:
• Support for LPDDR, DDR2, and DDR3 memories
• Simplified DDR command interface to standard AMBA AXI/AHB interface
• Up to 667 Mbps (333 MHz double data rate) performance for DDR2 and DDR3
• Up to 533 Mbps (266 MHz double data rate) performance for LPDDR
• Supports different DRAM bus width modes: ×8, ×16, and ×32 (or ×9, ×18, and ×36 with SECDED
enabled)
• Supports DRAM burst length of 4 or 8 in full bus-width mode; supports DRAM burst length of 4, 8, or
16 in half bus-width mode
• Supports memory densities up to 4 GB
• Supports a maximum of 8 memory banks
• SECDED enable/disable feature
• Embedded physical interface (PHY)

PB0051 Product Brief Revision 10.0 8

RTG4 Device Family Overview

• Read and Write buffers in fully associative CAMs, configurable in powers of 2, up to 64 Reads plus
64 Writes
• Support for dynamically changing clock frequency while in self-refresh
• Supports command reordering to optimize memory efficiency
• Supports data reordering, returning critical word first for each command
Each FDDR subsystem has an interface to the DDR memories. This is a multiplexed interface from the
FPGA fabric, which can be configured as either a single AXI 64-bit bus or two 32-bit AHB-Lite buses.
There is also a 16-bit APB configuration bus, which is used to initialize the majority of the internal
registers within the FDDR subsystem after reset. This APB configuration bus can be mastered by a
master in the FPGA fabric.

3.4 Clock Sources: On-Chip Oscillators, PLLs, and CCCs

RTG4 devices have an on-chip 50 MHz RC oscillator, which is available to the user for generating clocks
to the on-chip resources and the logic built on the FPGA fabric array. The oscillator can be used in
conjunction with the integrated user phase-locked loops (PLLs) and CCCs to generate clocks of varying
frequency and phase. In addition to being available to the user, this oscillator is also used by the system
controller and power-on-reset (POR) circuitry.
RTG4 devices have up to eight fabric CCC blocks and a dedicated PLL associated with each CCC to
provide flexible clocking to the FPGA fabric portion of the device. Each of the PLL and oscillator clock
sources are radiation hardened to provide glitch free clocks in the system. The user can use any of the
eight PLLs and CCCs to generate fabric clocks from the base fabric clock (CLK_BASE).

3.5 Radiation and Reliability

RTG4 FPGAs are manufactured on a low-power 65 nm process with substantial reliability heritage.
RTG4 FPGAs are now qualified to MIL-STD-883 Class B, and Microsemi will seek QML Class Q and
Class V qualification.
RTG4 FPGAs are immune to radiation-induced (SEU-induced) changes in configuration, due to the
robustness of the flash cells used to connect and configure logic resources and routing tracks.
No background scrubbing or reconfiguration of the FPGA is required to mitigate changes in configuration
due to radiation effects. Data errors, due to radiation, are mitigated by hardwired SEU-resistant flip-flops
in the logic cells and in the mathblocks. SECDED protection is optional for the embedded SRAM
(LSRAM and uSRAM) and the DDR memory controllers. This means that if a one-bit error is detected, it
is corrected automatically. Errors of more than one-bit are detected only but not corrected. SECDED
error signals are brought to the FPGA fabric to allow the user to monitor the status of these protected
internal memories.

3.6 RTG4 Development Tools

3.6.1 Design Software
Microsemi's Libero® SoC is a comprehensive software toolset to design applications using the RTG4
device. Libero SoC manages the entire design flow from design entry, synthesis and simulation,
place-and-route, timing, and power analysis, with enhanced integration of the embedded design flow.
System designers can leverage the easy-to-use Libero SoC that includes the following features:
• Synthesis, DSP, and debug support from Synopsys
• Simulation from Mentor Graphics
• Push-button design flow with power analysis and timing analysis
• SmartDebug for access to non-invasive probes within RTG4 devices
For more information about design software, see Libero SoC.

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RTG4 Device Family Overview

3.6.2 Design Hardware

Microsemi’s RTG4 development kit provides designers with an evaluation and development platform for
applications such as data transmission, serial connectivity, bus interface, and high-speed designs using
RTG4 devices. The development board features an RT4G150 device offering 151,824 logic elements in
a ceramic package with 1,657 pins.
The RTG4 development board includes 2 × 1 GB DDR3 and 2 GB of SPI flash memories. The board also
has several standard and advanced peripherals such as PCIe×4 edge connector, two FMC connectors
for using several off-the-shelf daughter cards, USB, Philips inter-integrated circuit (I2C), gigabit Ethernet
port, serial peripheral interface (SPI), and UART. A high precision operational amplifier circuitry on the
board helps to measure the core power consumption by the device. There is a FlashPro programmer
embedded on the board, allowing programming of the RTG4 FPGA through the JTAG interface.
For more information about kits and boards, see Dev Kits and Boards.

3.6.3 IP Cores
Microsemi offers many soft peripherals that can be placed in the FPGA fabric of the device. These
include Core1553, CoreJESD204BRX/TX, CoreFIR, CoreFFT, and many other DirectCores.
For more information about IP cores, see IP Cores.

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