VMDS 10242

VSC8658 Datasheet
Octal 10/100/1000BASE-T PHY and 100BASE-

FX/1000BASE-X SerDes
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performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
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respective owners.
VMDS-10242. 4.1 11/18

Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Register and Bit Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.1 SerDes MAC-to-Cat5 Mode MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.2 SGMII MAC-to-Cat5 Mode MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.3 All Modes Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 SGMII MAC-to-100BASE-FX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 Automatic Media-Sense (AMS) Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 Cat5 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.6 Manual MDI/MDI-X Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.7 Automatic Crossover and Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.8 Link Speed Downshift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.9 Transformerless Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.10 Ethernet Inline Powered Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.11 IEEE 802.3af PoE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.12 ActiPHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.12.1 Low Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.12.2 Link Partner Wake-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.12.3 Normal Operating State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.13 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.13.1 SMI Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.13.2 SMI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.14 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.1 LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.2 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.3 Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.15 GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.16 Testing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.16.1 Ethernet Packet Generator (EPG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.16.2 CRC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.16.3 Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.16.4 Near-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.16.5 Connector Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.16.6 VeriPHY Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.16.7 IEEE 1149.1 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.16.8 JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.16.9 Boundary Scan Register Cell Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VMDS-10242 VSC8658 Datasheet Revision 4.1 iii

4.17 IEEE 1149.6 AC-JTAG Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.1 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.2 Reserved Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 IEEE Standard and Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.1 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.2 Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.3 Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.4 Auto-Negotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.5 Link Partner Auto-Negotiation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.6 Auto-Negotiation Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.7 Transmit Auto-Negotiation Next Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.8 Auto-Negotiation Link Partner Next Page Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.9 1000BASE-T Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.10 1000BASE-T Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2.11 Main Registers Reserved Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2.12 1000BASE-T Status Extension 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.13 100BASE-TX Status Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.14 1000BASE-T Status Extension 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.15 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.16 Reserved Main Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.17 Extended Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.18 Extended PHY Control Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2.19 Extended PHY Control Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.20 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.21 Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2.22 MAC Interface Auto-Negotiation Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.23 Device Auxiliary Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2.24 LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.25 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3 Extended Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.1 Extended Page Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.2 SerDes Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.3 SerDes MAC/Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.4 CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.5 SIGDET Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.6 ActiPHY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.7 EEPROM Interface Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.8 EEPROM Data Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.9 PoE and Miscellaneous Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.10 VeriPHY Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.11 VeriPHY Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.12 VeriPHY Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.13 Reserved Extended Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.14 Ethernet Packet Generator Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.15 Ethernet Packet Generator Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4 General-Purpose I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4.1 Reserved GPIO Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.4.2 SIGDET vs GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.4.3 GPIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.4.4 GPIO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.4.5 GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.4.6 100BASE-FX Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.5 CMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.5.1 CMODE Pins and Related Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.5.2 Functions and Related CMODE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
VMDS-10242 VSC8658 Datasheet Revision 4.1 iv

5.5.3 CMODE Resistor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.6 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.6.1 EEPROM Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.6.2 Read/Write Access to the EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.1 VDDIO at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.2 VDDIO at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.3 VDDIO at 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1.4 VDD at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1.5 MAC and SerDes Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.1.6 MAC and SerDes Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.1.7 LED Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.8 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.1 Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.2 Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.3 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.4 SMI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.5 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.6 Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5 Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.1 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.2 Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.2.1 SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.2.2 SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.2.3 GPIO and SIGDET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.2.4 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.2.5 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.2.6 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.2.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.2.8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.1 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.2 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.3 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.1 PHY Address ID (Register 23E, Bits 15 to 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.2 JTAG Input High Voltage at 2.1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.3 First SMI Write Fails After Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.4 LED3 Port 7 Coupling Issue into XTAL Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.5 100BASE-FX Clock Data Recovery Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
VMDS-10242 VSC8658 Datasheet Revision 4.1 v

Figures
Figure 1 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2 High-level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3 SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4 SGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5 Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6 Automatic Media Sense Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7 Inline Powered Ethernet Switch Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8 ActiPHY State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 SMI Read Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 SMI Write Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11 MDINT_n Configured as an Open-Drain (Active-Low) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12 MDINT_n Configured as an Open-Source (Active-High) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13 Far-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14 Near-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15 Connector Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16 Test Access Port and Boundary Scan Architecture Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17 Register Space Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18 EEPROM Read and Write Register Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 19 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 20 SMI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 22 Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23 Pin Diagram, Left Side, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24 Pin Diagram, Right Side, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 25 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
VMDS-10242 VSC8658 Datasheet Revision 4.1 vi

Tables
Table 1 Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2 Operating Mode vs. Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3 AMS Media Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4 Supported MDI Pair Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5 LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6 LED Serial Stream Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7 JTAG Device Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8 JTAG Interface Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9 IEEE 802.3 Standard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10 Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11 Mode Control, Address 0 (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12 Mode Status, Address 1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13 Identifier 1, Address 2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14 Identifier 2, Address 3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15 Device Auto-Negotiation Advertisement, Address 4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16 Auto-Negotiation Link Partner Ability, Address 5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17 Auto-Negotiation Expansion, Address 6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18 Auto-Negotiation Next Page Transmit, Address 7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19 Auto-Negotiation LP Next Page Receive, Address 8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20 1000BASE-T Control, Address 9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 21 1000BASE-T Status, Address 10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22 1000BASE-T Status Extension 1, Address 15 (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23 100BASE-TX Status Extension, Address 16 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 24 1000BASE-T Status Extension 2, Address 17 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 25 Bypass Control, Address 18 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 26 Extended Control and Status, Address 22 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 27 Extended PHY Control 1, Address 23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 28 Extended PHY Control 2, Address 24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 29 Interrupt Mask, Address 25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 30 Interrupt Status, Address 26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 31 MAC Auto-Negotiation Control and Status, Address 27 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 32 Auxiliary Control and Status, Address 28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 33 LED Mode Select, Address 29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 34 Available LED Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 35 LED Behavior, Address 30 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 36 Extended Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 37 Extended Page Access, Address 31 (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 38 SerDes Media Auto-Negotiation Control/Status, Address 16E (0x10) . . . . . . . . . . . . . . . . . . . . . . 46
Table 39 SerDes MAC Control, Address 17E (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 40 CRC Good Counter, Address 18E (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 41 SIGDET Polarity Control, Address 19E (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 42 Extended PHY Control 3, Address 20E (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 43 EEPROM Interface Status and Control, Address 21E (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 44 EEPROM Read or Write, Address 22E (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 45 Extended PHY Control 4, Address 23E (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 46 VeriPHY Control Register 1, Address 24E (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 47 VeriPHY Control Register 2, Address 25E (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 48 VeriPHY Control Register 3, Address 26E (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 49 VeriPHY Control Register 3 Fault Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 50 EPG Control Register 1, Address 29E (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 51 EPG Control Register 2, Address 30E (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 52 General-Purpose Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 53 SIGDET vs GPIO Control, Address 13G (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 54 GPIO Input, Address 15G (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VMDS-10242 VSC8658 Datasheet Revision 4.1 vii

Table 55 GPIO Output, Address 16G (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 56 GPIO Input/Output Configuration, Address 17G (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 57 100BASE-FX Control, Address 18G (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 58 CMODE Configuration Pins and Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 59 Device Functions and Associated CMODE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 60 CMODE Resistor Values and Resultant Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 61 EEPROM Configuration Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 62 DC Characteristics for Pins Referenced to VDDIO at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 65 DC Characteristics for Pins Referenced to VDD33 at 3.30 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 66 DC Characteristics for MAC_RDP/N_n and SER_DOP/N_n Pins . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 67 DC Characteristics for MAC_TDP/N_n and SER_DIP/N_n Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 68 DC Characteristics for LED[3:0]_n Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 69 DC Characteristics for JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 70 Typical Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 71 Current Consumption in SerDes/SGMII to 1000BASE-X Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 72 Consumption in SerDes/SGMII to 100BASE-FX or SerDes Pass-Through Mode . . . . . . . . . . . . . 65
Table 73 AC Characteristics for REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 74 AC Characteristics for REFCLK Input with 25 MHz Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 75 AC Characteristics for the CLKOUT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 76 AC Characteristics for the JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 77 AC Characteristics for the SMI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 78 AC Characteristics for Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 79 AC Characteristics for Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 80 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 81 Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 82 SerDes MAC Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 83 SerDes Media Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 84 GPIO and SIGDET Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 85 Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 86 SMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 87 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 88 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 89 Power Supply and Associated Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 90 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 91 Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 92 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
VMDS-10242 VSC8658 Datasheet Revision 4.1 viii

Revision History
1 Revision History
This section describes the changes that were implemented in this document. The changes are listed by
revision, starting with the most current publication.
1.1 Revision 4.1

Revision 4.1 of this datasheet was published in June 2007. In revision 4.1, design consideration issues
were added. For more information, see LED3 Port 7 Coupling Issue into XTAL Clock Pin, page 85 and
100BASE-FX Clock Data Recovery Improvement, page 85.
1.2 Revision 4.0

Revision 4.0 of this datasheet was published in March 2007. The following is a summary of the changes
implemented in the datasheet:
• In register 0, the definitions for bits 13 and 6 (forced speed selection) were combined, because they
are correlated.
• Throughout the electrical specifications, all references to VDD33A were corrected to VDD33 and all
references to VDDIG were corrected to VDD12.
• In the DC characteristics for VDDIO at 1.8 V, the condition for the output low voltage parameter
(VOL) was corrected from a negative value (IOL = –0.5 mA) to a positive value (IOL = 0.5 mA).
• In the DC characteristics for VDD33 at 3.30 V, the output leakage (IOLEAK) was changed to match
the same values as the input leakage (IILEAK) with the same condition (internal resistor included).
Specifically, the values were changed from –10 µA minimum and 10 µA maximum to –42 µA
minimum and 42 µA maximum.
• In the DC characteristics for MAC_RDP/N_n and SER_DOP/N_n pins, the total jitter parameter (TJ)
was updated from 160 ps typical to 185 ps typical and from 180 ps maximum to 260 ps maximum.
• In the DC characteristics for MAC_TDP/N_n and SER_DIP/N_n pins, the input differential voltage
parameter (VIDIFF) was updated from 1400 mV maximum to 2400 mV maximum.
• For better organization, the total receive jitter tolerance parameter (JRXTotal) was moved from the
MAC_RDP/N_n and SER_DOP/N_n pin characteristics to the MAC_TDP/N_n and SER_DIP/N_n
pin characteristics. The values were also updated to account for differences between 1000BASE-X
and 100BASE-FX modes.
• In the DC characteristics for LED pins, a qualifier in the introductory paragraph was removed stating
that these specifications are valid only when a voltage range of 1.3 V to 2.3 V is applied to the LED
pins. For the low voltage parameter (VOL), the condition was corrected from a negative value (IOL =
–4.0 mA) to a positive value (IOL = 4.0 mA). The output low current drive strength parameter (IOL)
was updated from 4.0 mA maximum to 8.0 mA maximum. The maximum value for the output high
current drive strength parameter (IOH) was removed.
• The current consumption specifications previously named 1000BASE-X/100BASE-FX mode are
now named 1000BASE-X mode. The current consumption specifications previously named
1000BASE-X mode are now named 100BASE-FX or SerDes pass-through mode.
• The current consumption specifications were updated for 100BASE-FX or SerDes pass-through
mode (previously named 1000BASE-X mode). All of the parameters were updated, except for the
IVDDIO parameters, which remain the same.
• In the stress ratings, for the DC input voltage on both the VDD12 and VDD12A supply pins, the
maximum was updated from 1.5 V to 1.4 V. The electrostatic discharge voltage values were added.
For charged device model, it was specified ±250 V. For human body model, it was specified as
meeting a Class 2 rating.
• For the serial management interface (SMI) pins, it was clarified that EECLK and EEDAT are
referenced to VDD33, not VDDIO.
• The moisture sensitivity was specified as level 3 for the VSC8658HJ package. For the lead(Pb)-free
package, VSC8658XHJ, it was specified as level 4.
• Design consideration issues were added.
VMDS-10242 VSC8658 Datasheet Revision 4.1 1

Revision History
1.3 Revision 2.0

Revision 2.0 of this datasheet was published in November 2006. This was the first publication of the
document.

Introduction
2 Introduction
This document consists of descriptions and specifications for both functional and physical aspects of the
Octal 10/100/1000BASE-T PHY and 100BASE-FX/1000BASE-X SerDes.
In addition to datasheets, the Microsemi website offers an extensive library of documentation, support
files, and application materials specific to each device. The address of the Microsemi website is
www.microsemi.com.
2.1 Register and Bit Conventions

This document refers to registers by their address and bit number in decimal notation. A range of bits is
indicated with a colon. For example, a reference to address 26, bits 15 through 14 is shown as 26.15:14.
Bit numbering follows the IEEE standard with bit 15 being the most significant bit and bit 0 being the least
significant bit.

Product Overview
3 Product Overview
The VSC8658 device is a low-power, octal Gigabit Ethernet transceiver with dual, fully integrated
1.25 Gbps SerDes interfaces. It is designed for use in applications, such as multiport switches and
routers, where its compact ball grid array (BGA) packaging, low electromagnetic interference (EMI) line
driver, and integrated line side termination resistors conserve both power and PC board space. Using the
VSC8658 device in your design makes it possible to lower the component count of your PC board, sub-
assembly, or device without sacrificing chip-centric capabilities or utility. This feature can make it less
expensive to produce and more cost-effective to deploy.
Microsemi’s mixed signal and digital signal processing (DSP) architecture—a key operational feature of
the VSC8658 device—assures robust performance even under less-than-favorable environmental
conditions. It supports both half-duplex and full-duplex 10BASE-T, 100BASE-TX, and 1000BASE-T
communication speeds over Category 5 (Cat5) unshielded twisted pair (UTP) cable at distances greater
than 140 m, displaying excellent tolerance to NEXT, FEXT, echo, and other types of ambient
environment and system electronic noise. This device also supports 100BASE-FX and 1000BASE-X to
connect to fiber modules, such as GBICs and SFPs.
The following illustration shows a high-level, generic view of a VSC8658 application.
Figure 1 • Typical Application
SGMII, SerDes
1.2 V 3.3 V
SerDes
Optics / SFP
10/100/1000 Mbps Ethernet MAC RJ-45 and Magnetics

VSC8658 SerDes
Octal Optics / SFP
10/100/1000 Mbps Ethernet MAC
10/100/1000BASE-T
RJ-45 and Magnetics
100BASE-FX/1000BASE-X
Gigabit Ethernet
Transceiver PHY
SerDes
Optics / SFP
10/100/1000 Mbps Ethernet MAC
RJ-45 and Magnetics
3.1 Features and Benefits

This section lists key aspects of the VSC8658 device functionality and design that distinguish it from
similar products.
Table 1 • Features and Benefits
Feature Benefit
650 mW per port power consumption (when configured Lowers system cost by eliminating the need for extra
for 1000BASE-T operation) heat-dissipating and power-processing components;
simplifies system design
27 mm x 27 mm, 444-pin BGA packaging Facilitates single row, high port density switch designs
Patented, low EMI line driver with integrated line side Eliminates the need for as many as 384 passive
termination resistors components in 48-port switch applications
Auto-Media Sense™ capability configurable per-port Detects and automatically configures a port for operation
with copper or fiber media; auto-enables
10/100/1000BASE-T fixed media ports, 100BASE-FX
SFPs, 1000BASE-X SFPs, 1000BASE-T SFPs, triple-
speed SFPs, or backplanes

Product Overview
Table 1 • Features and Benefits (continued)
Feature Benefit
Dual, high-performance, 1.25 Gbps SerDes Maximizes receive jitter tolerance and minimizes transmit
jitter (in comparison to single SerDes architectures)
Compliance with IEEE standard 802.3 (10BASE-T, Ensures seamless deployment in devices throughout
100BASE-TX, 1000BASE-T, 1000BASE-X, 100BASE-FX) existing copper networks while maintaining excellent
tolerance to ambient electronic noise and any
substandard cabling
Support for frame sizes greater than 16 kilobytes at all Provides for maximum Jumbo frame sizes on custom
device throughput settings and programmable SANs and LANs
synchronization FIFO buffers
Four integrated and programmable LED direct drivers per Eliminates the need for external components, lowers EMI
port, on-chip filtering and support for bi-color LEDs generation, and lowers design cost
Multiple built-in testing facilities, including near-end, far- Lowers system or device development, lowers
end, and connector loopback; Ethernet packet generator deployment costs, and decreases time-to-market
with CRC error counter
Serial LED interface option Enables design flexibility
Support for the CISCO specification for serial gigabit Saves manufacturing and quality assurance costs
media-independent interface version 1.7 (SGMII (v1.7),
for 1000BASE-X MACs, for IEEE standard 1149.1-1999
JTAG boundary scan, and for IEEE standard 1149.6
AC-JTAG scan.
VeriPHY™ cable diagnostics Enables system managers to simplify deployment and
improve Gigabit Ethernet network performance
3.2 Block Diagram

The following illustration shows the primary functional blocks of the VSC8658 device.

Product Overview
Figure 2 • High-level Block Diagram
T X V P_ A _ n
TX VN _A_ n
1 0 /1 0 0 / 1 0 /1 0 0 / M DI T X V P_ B _ n
TX VN _B_n
1000 BA SE -T 1 0 0 0 B A S E -T T w is te d P a ir T X V P_ C _ n
PCS PM A In te r f a ce TX VN _C _n
Auto-Negotiation (SGMII, FIFOs)

T X V P_ D _ n
TX VN _D_n
M A C_ T D P _ n Serial MAC Interface (SerDes)

1 0 0 0B A S E -X 1 0 0 0B A S E -X
M A C_ T D N _ n
PC S PMA
M A C_ R D P _ n SE R _ D O P _ n
SE R _ D O N _ n
M A C_ R D N _ n
M DI SE R _ D IP _ n
SerD es SE R _ D IN _ n
1 0 0B A S E -F X 1 0 0 B A S E -F X In te r f a ce
SIG D E T _ n /
PC S PMA G P IO[7 :0 ]
1 0 /1 0 0 /1 0 0 0 B A S E -T S F P D a ta P a th
C M O D E [7 :0 ] X T A L1 / R E FC L K
NRESET X T A L2
MDC M anagem ent
R E F_ FIL T _ A
M D IO and JT A G P LL R E F_ R E X T _ A
M D IN T _ n C o n tr o l In te r f a ce R E F_ FIL T _ B
EEDAT R E F_ R E X T _ B
EEC LK (M IIM )
CLKOU T
G P IO [1 5 :8 ]
LE D In te r f a ce L E D [3 :0 ] _ n
TDO
TDI
TCK
TMS
TRST

Functional Descriptions
4 Functional Descriptions
This section provides detailed information about how the VSC8658 device works, what configurations
and operational features are available, and how to test its function. It includes descriptions of the various
device interfaces and how to set them up.
With the information in this section, you can better determine which device setup parameters you must
access to configure the VSC8658 device to work in your application. There are three ways to configure
the VSC8658 device. You can access and set its internal memory registers, use a combination of the
device CMODE pins and its registers, or configure and connect an external EEPROM to execute a
configuration sequence upon system startup.
For information about VSC8658 device registers, see Configuration, page 26.
For information about the device CMODE pins, see CMODE, page 55.
For information about using an EEPROM with the VSC8658 device, see EEPROM, page 58.
4.1 Operating Modes

With respect to its function in your design, the VSC8658 device can act as the interface between a media
access controller (MAC) and either Category 5 (Cat5) media, 100BASE-FX fiber media, or 1000BASE-X
fiber media. Or, the VSC8658 device can act as a MAC-to-MAC pass-through device to take advantage
of the auto-negotiation feature.
Depending upon the speed of data throughput required in your application, the MAC may be either a
SerDes or an SGMII device, and can also be configured to support twisted pair Cat5 cabling, 100BASE-
FX/1000BASE-X fiber optic cabling, or copper small form factor pluggable (SFP) devices.
As shown in the following table, the operating mode you choose when setting up the VSC8658 device is
a function of which type of MAC is to be connected, which data throughput speeds are required in the
application, and the type of Cat5 media support required.
Table 2 • Operating Mode vs. Speed
10/100/
1000BASE-X 1000BASE-T
10/100/1000BAS Fiber Optic 100BASE-FX Copper SFP
VSC8658 Mode E-T Support Support Support Support
SerDes MAC-to-Cat5 Link Partner 1000BASE-T
only
SGMII MAC-to-Cat5 Link Partner Yes
SerDes MAC-to-SerDes with Auto-Negotiation Yes 1000BASE-T
only
SGMII MAC-to-SerDes with Auto-Negotiation Yes 1000BASE-T
only
SerDes MAC-to-SerDes with Pass-Through Yes(1) 1000BASE-T
only(1)
SGMII MAC-to-SGMII with Pass-Through Yes(1) Yes(1)
SGMII MAC-to-100BASE-FX Yes
SerDes MAC with Automatic Media Sensing 1000BASE-T Yes
(AMS) and Auto Negotiation Only
SGMII MAC with AMS Yes Yes Yes

Table 2 • Operating Mode vs. Speed (continued)
10/100/
1000BASE-X 1000BASE-T
10/100/1000BAS Fiber Optic 100BASE-FX Copper SFP
VSC8658 Mode E-T Support Support Support Support
SerDes MAC with AMS and Pass-Through 1000BASE-T Yes(1) 1000BASE-T
Only only(1)
SGMII MAC with AMS and Pass-Through Yes Yes(1) Yes(1)
1. The MAC used must be capable of supporting this media.
4.1.1 SerDes MAC-to-Cat5 Mode MAC Interface

When connected to a SerDes MAC, the VSC8658 device provides data throughput at a rate of
1000 Mbps only; 10 Mbps and 100 Mbps rates are not supported. To configure the device for operation in
this mode, select the 1000BASE-T-only setting in the registers, using the CMODE pin, or in the external
EEPROM startup sequence.
For information about using the device registers to configure the VSC8658 device for operation in
SerDes MAC-to-Cat5 mode, see Mode Control, page 28.
The following illustration shows a typical connection of the VSC8658 device to a SerDes MAC.
Figure 3 • SerDes MAC Interface
TDP MAC_TDP
100 Ω
or
150 Ω
TDN MAC_TDN
SerDes MAC VSC8658

PHY Port_n
0.1 µF
RDP MAC_RDP
100 Ω 100 Ω
or or
150 Ω 0.1 µF 150 Ω
RDN MAC_RDN
4.1.2 SGMII MAC-to-Cat5 Mode MAC Interface

When configured to detect and switch between 10BASE-T, 100BASE-T, and 1000BASE-T data rates, the
VSC8658 device can be connected to an SGMII-compatible MAC.
For information about using the device registers to configure the VSC8658 device for operation in
SerDes MAC-to-Cat5 Mode, see Mode Control, page 28.
The following illustration shows a typical connection of the VSC8658 device to an SGMII-compatible
MAC.

Figure 4 • SGMII MAC Interface
TDP MAC_TDP
100 Ω
or
150 Ω
TDN MAC_TDN
TCP
SGMII MAC VSC8658
PHY Port_n
TCN
0.1 µF
RDP MAC_RDP
100 Ω 100 Ω
or or
150 Ω 150 Ω
0.1 µF
RDN MAC_RDN
4.1.3 All Modes Cat5 Media Interface

The VSC8658 device twisted pair interface is compliant with the IEEE standard 802.3-2000. Unlike many
other gigabit PHYs, the VSC8658 device uses fully integrated, passive components (required to connect
the PHY’s Cat5 interface to an external 1:1 transformer). The following illustration shows the
connections.
Figure 5 • Cat5 Media Interface
TXVP_A_n 1 A+
0.1 µF
2 A–
TXVN_A_n
3 B+
TXVP_B_n
0.1 µF Transformer 6 B–
TXVN_B_n
VSC8658
PHY Port_n RJ-45
4 C+
TXVP_C_n
0.1 µF
5 C–
TXVN_C_n
7 D+
TXVP_D_n
0.1 µF
8 D–
TXVN_D_n
75 Ω
75 Ω
1000 pF, 2 kV
75 Ω
75 Ω

4.2 SerDes Media Interface

The VSC8658 device SerDes Media Interface performs data serialization and deserialization functions
using an integrated SerDes block. The interface operates at 1.25 Gbps speed, providing full-duplex and
half-duplex 1000 Mbps bandwidth that can connect directly to 100BASE-FX/1000BASE-X-compliant
optical devices as well as to 10/100/1000BASE-T copper SFP devices. The interface can be operated in
two SerDes modes:
• SerDes with Media Interface PCS Auto-Negotiation mode
• SerDes with Pass-Through mode
The SerDes with Media Interface PCS Auto-Negotiation mode supports IEEE standard 802.3, clauses 36
and 37, which describe fiber auto-negotiation. In this mode, control and status of the SerDes media is
displayed in the VSC8658 device registers 0 through 15 in a manner similar to what is described in the
IEEE standard 802.3, clause 28. In this mode, connected copper SFPs can only operate at 1000BASE-T
speed. A link in this mode is established using auto-negotiation (enabled or disabled) between the PHY
and the link partner.
For information about how the VSC8658 LEDs operate in this mode, see LED Behavior, page 19.
SerDes with Pass-Through mode is a feature that links a fiber module or copper SFP directly to the
SerDes interface of the MAC through the VSC8658 device. For example, to support 10/100/1000 copper
SFPs, the MAC must be able to operate in SGMII mode. Because the MAC controls the establishment of
the link, PHY registers 0 through 15 and the PHY LEDs do not indicate link information when in SerDes
Pass-Through Mode. In this case, the only supported LED operation is the force on and force off modes.
A pass-through link is established when the SIGDET pin is asserted.
4.3 SGMII MAC-to-100BASE-FX Mode

The VSC8658 can support the 100BASE-FX communication speed to connect to fiber modules, such as
GBICs and SFPs.
This capability is facilitated by using the connections on the SerDes pins when connected to a MAC
through SGMII. Ethernet Package Generator (EPG), cyclical redundancy checking (CRC) counters, and
loopback modes are supported in the 100BASE-FX over SerDes mode. For information about how the
VSC8658 LEDs operate in this mode, see LED Behavior, page 19.
For information about how to configure the VSC8658 in 100BASE-FX mode using the twisted pair
interface, see 100BASE-FX Control, page 54.
4.4 Automatic Media-Sense (AMS) Interface Mode

This mode can automatically set the media interface to Cat5 or to SerDes interface modes automatically.
The active media mode chosen is based on the automatic media-sense (AMS) preferences set in the
device register 23, bit 11.
The following illustration shows a block diagram of the AMS functionality in the VSC8658 device.

Figure 6 • Automatic Media Sense Block Diagram
VSC8658 port_n
Cat5
MAC
SGMII /
Serial MAC
TD Auto Sense
RD Logic
SerDes
Fiber Optic
SIGDET Module
When both SerDes and Cat5 media interfaces attempt to establish a link, the preferred media interface
overrides a link-up of the non-preferred media interface. For example, if the preference is set for SerDes
mode and Cat5 media establishes a link, then Cat5 becomes the active media interface. However, after
the SerDes media interface establishes a link, the Cat5 interface drops its link because the preference
was set for SerDes mode. In this scenario, the SerDes preference determines the active media source
until the SerDes link is lost. Also, Cat5 media cannot link up unless there is no SerDes media link
established.
The following table lists the available AMS preferences.
Table 3 • AMS Media Preferences
Cat5 Linked, SerDes Linked, Both Cat5 and

Preference Cat5 Linked, SerDes Linked, SerDes Attempts Cat5 Attempts to SerDes Attempt
Setting Fiber Not Linked Cat5 Not Linked to Link Link to Link
SerDes Cat5 SerDes SerDes SerDes SerDes
Cat5 Cat5 SerDes Cat5 Cat5 Cat5
The status of the media mode selected by the AMS can be read from device register 20E, bits 7:6. It
indicates whether copper media, SerDes media, or no media is selected.
Each PHY has two auto-media sense modes. The difference between the modes is based on the SerDes
media modes:
• SerDes with Auto-Negotiation
• SerDes with Pass-Through
For more information about SerDes media mode functionality with AMS enabled, see SerDes Media
Interface, page 10.
For AMS with SerDes auto-negotiation, the status and control of both the Cat5 and the SerDes media
can be made using registers 0 through 15. For AMS with SerDes pass-through, only the Cat5 interface
can have its interface control and status monitored. The SerDes media must then be controlled and
monitored within the MAC.
4.5 Cat5 Auto-Negotiation

The VSC8658 device supports twisted pair auto-negotiation as defined by clause 28 of the IEEE
standard 802.3-2000.
The auto-negotiation process consists of the evaluation of the advertised capabilities of the PHY and its
link partner to determine the best possible operating mode, throughput speed, duplex configuration, and
master or slave operating modes in the case of 1000BASE-T setups. Auto-negotiation also allows a

connected MAC to communicate with its link partner MAC through the VSC8658 device using optional
“next pages,” which set attributes that may not otherwise be defined by the IEEE standard.
In installations where the Cat5 link partner does not support auto-negotiation, the VSC8658 automatically
switches to use parallel detection to select the appropriate link speed.
Clearing VSC8658 device register 0, bit 12 disables clause 28 twisted-pair auto-negotiation. If auto-
negotiation is disabled, the state of register bits 0.6, 0.13, and 0.8 determine the device operating speed
and duplex mode. For more information about configuring auto-negotiation, see IEEE Standard and Main
Registers, page 27.
4.6 Manual MDI/MDI-X Setting

As an alternative to Auto MDI/MDI-X detection, you can force the PHY to be MDI or MDI-X using the
following scripts.
Format:
Phywrite ( register(dec), data(hex) )
Phywritemask ( register(dec), data(hex), mask(hex) )
To force MDI:
Phywrite ( 31, 0x2A30 )
Phywritemask ( 5, 0x0010, 0x0018 )
Phywrite ( 31, 0x0000 )
To force MDI-X:
Phywrite ( 31, 0x0000 )
To resume MDI/MDI-X setting based on register 18, bits 7 and 5:
Phywrite ( 31, 0x0000 )
4.7 Automatic Crossover and Polarity Detection

For trouble-free configuration and management of Ethernet links, the VSC8658 device includes a robust,
automatic, media-dependent and crossed media-dependent detection feature, Auto MDI/MDI-X, in all of
its three available speeds (10BASE-T, 100BASE-T, and 1000BASE-T). The function is fully compliant
with clause 40 of the IEEE standard 802.3-2002.
Additionally, the device detects and corrects polarity errors on all MDI pairs—a useful capability that
exceeds the requirements of the standard.
Both auto MDI/MDI-X detection and polarity correction are enabled in the device by default. You can
change the default settings using device register bits 18.5:4. Status bits for each of these functions are
located in register 28.
The VSC8658 device’s automatic MDI/MDI-X algorithm successfully detects, corrects, and operates with
any of the MDI wiring pair combinations listed in the following table.
Table 4 • Supported MDI Pair Combinations
RJ-45 Pin Pairings

1, 2 3, 6 4, 5 7, 8 Mode
A B C D Normal MDI
B A D C Normal MDI-X
A B D C Normal MDI with pair swap on C and D pair
B A C D Normal MDI-X with pair swap on C and D pair

Note: The VSC8658 device can be configured to perform Auto MDI/MDI-X even when its Auto-negotiation
feature is disabled (setting register 0.12 to 0) and the link is forced into 10/100 speeds. To enable this
feature, set register 18.7 to 0.
4.8 Link Speed Downshift

For operation in cabling environments that are incompatible with 1000BASE-T, the VSC8658 device
provides an automatic link speed “downshift” option. When enabled, the device automatically changes its
1000BASE-T auto-negotiation advertisement to the next slower speed after a set number of failed
attempts at 1000BASE-T.
This is useful in setting up in networks using older cable installations that may include only pairs A and B
and not pairs C and D.
You can configure and monitor link speed downshifting using register bits 20E.4:1. For more information,
see Extended PHY Control Set 1, page 37.
4.9 Transformerless Ethernet

The Cat5 media interface supports 10/100/1000BT Ethernet for backplane applications such as those
specified by the PICMG™ 2.16 and ATCA™ 3.0 specifications for eight-pin channels. With proper AC
coupling, the typical Cat5 transformer can be removed and replaced with capacitors.
4.10 Ethernet Inline Powered Devices

The VSC8658 device can detect legacy inline powered devices in Ethernet network applications. Its
inline powered detection capability can be part of a system that allows for IP-phone and other devices
such as wireless access points to receive power directly from their Ethernet cable, similar to office digital
phones receiving power from a Private Branch Exchange (PBX) office switch over the telephone cabling.
This can eliminate the need for an IP-phone to have an external power supply. It also enables the inline
powered device to remain active during a power outage (assuming the Ethernet switch is connected to
an uninterrupted power supply, battery, back-up power generator, or some other uninterruptable power
source).
For more information about legacy inline powered device detection, visit the Cisco Web site at
www.cisco.com.
The following illustration shows an example of this type of application.

Figure 7 • Inline Powered Ethernet Switch Diagram
Gigabit Switch Processor
Control
SGMII SMI
Interface
Inline,
VSC8658_0 VSC8658_1 VSC8658_n Power-Over-Ethernet
(PoE)
Power Supply
Transformer Transformer Transformer
RJ-45 RJ-45 RJ-45

I/F I/F I/F
Cat5
Link Link Link

Partner Partner Partner
The following procedure describes the process that an Ethernet switch must perform in order to process
inline power requests made by a link partner (LP) that is, in turn, capable of receiving inline power.
1. Enable the inline powered device detection mode on each VSC8658 PHY using its serial
management interface. Set register bit 23E.10 to 1.
2. Ensure that the VSC8658 device Auto-Negotiation Enable bit (register 0.12) is also set to 1. In the
application, the device sends a special Fast Link Pulse (FLP) signal to the LP. Reading register bit
23E.9:8 returns 00 during the search for devices that require Power-over-Ethernet (PoE).
3. The VSC8658 PHY monitors its inputs for the FLP signal looped back by the LP. An LP capable of
receiving PoE loops back the FLP pulses when the LP is in a powered-down state. This is reported
when VSC8658 device register bit 23E.9:8 reads back 01. It can also be verified as an inline power
detection interrupt by reading VSC8658 device register bit 26.9, which should be a 1, and which is
subsequently cleared and the interrupt de-asserted after the read. If an LP device does not loop
back the FLP after a specific time, VSC8658 device register bit 23E.9:8 automatically resets to 10.
4. If the VSC8658 PHY reports that the LP needs PoE, the Ethernet switch must enable inline power
on this port, externally of the PHY.
5. The PHY automatically disables inline powered device detection if the VSC8658 device register bit
23E.9:8 automatically resets to 10, and then automatically changes to its normal auto-negotiation
process. A link is then auto-negotiated and established when the link status bit is set (register bit 1.2
is set to 1).
6. In the event of a link failure (indicated when VSC8658 device register bit 1.2 reads 0), the inline
power should be disabled to the inline powered device external to the PHY. The VSC8658 PHY
disables its normal auto-negotiation process and re-enables its inline powered device detection
mode.

4.11 IEEE 802.3af PoE Support

The VSC8658 device is also compatible with switch designs that are intended for use in systems that
supply power to Data Terminal Equipment (DTE) by means of the MDI or twisted pair cable, as described
in clause 33 of the IEEE standard 802.3af.
4.12 ActiPHY Power Management

In addition to the IEEE-specified power-down control bit (device register bit 0.11), the device also
includes an ActiPHY™ power management mode for each PHY. This mode enables support for power-
sensitive applications such as laptop computers with Wake-on-LAN™ capability. It utilizes a signal-detect
function that monitors the media interface for the presence of a link to determine when to automatically
power-down the PHY. The PHY “wakes up” at a programmable interval and attempts to “wake-up” the
link partner PHY by sending a burst of FLP over copper media.
The ActiPHY™ power management mode in the VSC8658 device is enabled on a per-port basis during
normal operation at any time by setting register bit 28.6 to 1.
There are three operating states possible when ActiPHY™ mode is enabled:
• Low power state
• LP wake-up state
• Normal operating state (link up state)
The VSC8658 device switches between the low power state and LP wake-up state at a programmable
rate (the default is two seconds) until signal energy has been detected on the media interface pins. When
signal energy is detected, the PHY enters the normal operating state. If the PHY is in its normal operating
state and the link fails, the PHY returns to the low power state after the expiration of the link status time-
out timer. After reset, the PHY enters the low power state.
When auto-negotiation is enabled in the PHY, the ActiPHY state machine operates as described. If auto-
negotiation is disabled and the link is forced to use 10BT or 100BTX modes while the PHY is in its low
power state, the PHY continues to transition between the low power and LP wake-up states until signal
energy is detected on the media pins. At that time, the PHY transitions to the normal operating state and
stays in that state even when the link is dropped. If auto-negotiation is disabled while the PHY is in the
normal operation state, the PHY stays in that state when the link is dropped and does not transition back
to the low power state.
The following illustration shows the relationship between ActiPHY states and timers.
Figure 8 • ActiPHY State Diagram
Low Power State
Signal Energy
Sleep Timer Detected on the
Expires Connected Media
FLP Burst or
Timeout Timer Expires;
Clause 37 Restart
Auto-negotiation Enabled
Signal Sent
Link Partner Normal

Wake-up State Operation
4.12.1 Low Power State

In the low power state, all major digital blocks are powered down. However, the following functionality is
provided:
• SMI interface (MDC, MDIO, MDINT_n)

• CLKOUT
In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low
power state and transitions to the normal operating state when signal energy is detected on the media.
This happens when the PHY is connected to one of the following:
• Auto-negotiation capable link partner
• Another PHY in enhanced ActiPHY LP wake-up state
In the absence of signal energy on the media pins, the PHY transitions from the low power state to the
LP wake-up state periodically based on the programmable sleep timer (register bits 20E.14:13). The
actual sleep time duration is randomized from –80 milliseconds (ms) to +60 ms to avoid two linked PHYs
in ActiPHY mode entering a lock-up state during operation.
4.12.2 Link Partner Wake-up State

In this state, the PHY attempts to wake up the link partner. Up to three complete FLP bursts are sent on
alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer, which is set using
register bits 20E.12:11.
In this state, the following functionality is provided:
• SMI interface (MDC, MDIO, MDINT_n)
• CLKOUT
After sending signal energy on the relevant media, the PHY returns to the low power state.
4.12.3 Normal Operating State

In this state, the PHY establishes a link with a link partner. When the media is unplugged or the link
partner is powered down, the PHY waits for the duration of the programmable link status time-out timer,
which is set using register bit 28.7 and bit 28.2. It then enters the low power state.
4.13 Serial Management Interface

The VSC8658 device includes an IEEE 802.3-compliant serial management interface (SMI) that is
affected by use of its MDC and MDIO pins. The SMI provides access to device control and status
registers. The register set that controls the SMI consists of 32 16-bit registers, including all required
IEEE-specified registers. Also, there are additional pages of registers accessible using device register
31.
For more information, see Extended Page Registers, page 45.
The SMI is a synchronous serial interface with bidirectional data on the MDIO pin that is clocked on the
rising edge of the MDC pin. The interface can be clocked at a rate from 0 MHz to 12.5 MHz, depending
on the total load on MDIO. An external, 2 kΩ pull-up resistor is required on the MDIO pin.
4.13.1 SMI Frames

Data is transferred over the SMI using 32-bit frames with an optional and arbitrary length preamble. The
following illustrations show the SMI frame format for the read operation and write operation.
Figure 9 • SMI Read Frame
Station Manager Drives MDIO PHY Drives MDIO
MDC
MDIO
Z Z 1 0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 Z 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Z Z
Idle Preamble SFD Read PHY Address Register Address TA Register Data from PHY Idle
(optional) to PHY

Figure 10 • SMI Write Frame

Station Manager Drives MDIO (PHY tristates MDIO during entire sequence )
MDC
MDIO
Z Z 1 0 1 0 1 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Z Z
Idle Preamble SFD Write PHY Address Register Address TA Register Data from PHY Idle
(optional ) to PHY
The following provides additional information about the terms used in Figure 9 and Figure 10.
Idle During idle, the MDIO node goes to a high-impedance state. This allows an external pull-up resistor
to pull the MDIO node up to a logical 1 state. Because the idle mode should not contain any transitions
on MDIO, the number of bits is undefined during idle.
Preamble By default, preambles are not expected or required. The preamble is a string of ones. If it
exists, the preamble must be at least one bit; otherwise, it may be of an arbitrary length.
Start of Frame (SFD) A pattern of 01 indicates the start of frame. If the pattern is not 01, all following
bits are ignored until the next preamble pattern is detected.
Read or Write Opcode A pattern of 10 indicates a read. A 01 pattern indicates a write. If the bits are
not either 01 or 10, all following bits are ignored until the next preamble pattern is detected.
PHY Address The particular VSC8658 responds to a message frame only when the received PHY
address matches its physical address. The physical address is five bits long (4:0). Bits 4:3 are set by the
CMODE pins. Bits 2:0 represent the PHY of the device being addressed.
Register Address The next five bits are the register address.
Turnaround The two bits used to avoid signal contention when a read operation is performed on the
MDIO are called the turnaround (TA) bits. During read operations, the VSC8658 device drives the
second TA bit, a logical 0.
Data The 16-bits read from or written to the device are considered the data or data stream. When data
is read from a PHY, it is valid at the output from one rising edge of MDC to the next rising edge of MDC.
When data is written to the PHY, it must be valid around the rising edge of MDC.
Idle The sequence is repeated.
4.13.2 SMI Interrupts

The SMI also includes an output interrupt signal, MDINT_n, for signaling the station manager when
certain events occur in the PHY. A separate MDINT_n pin is included for each VSC8658 device PHY.
Each MDINT_n pin can be configured for open-drain (active-low) by tying the pin to a pull-up resistor and
to VDDIO. The following illustration shows this configuration.
Figure 11 • MDINT_n Configured as an Open-Drain (Active-Low) Pin
VDDIO External Pull-up
Resistor at the
Station Manager for
PHY_n Open-drain
(Active-low Mode)
Interrupt Pin Enable
MDINT_n MDINT_n
(Register 25.15) (to the Station
Manager)
Interrupt Pin Status

(Register 26.15)

Alternatively, each MDINT_n pin can be configured for open-source (active-high) by tying the pin to a
pull-down resistor and to VSS. The following illustration shows this configuration.
Figure 12 • MDINT_n Configured as an Open-Source (Active-High) Pin
VDDIO
Interrupt Pin Enable

(Register 25.15)
MDINT_n
(to the Station
MDINT_n Manager)
Interrupt Pin Status
(Register 26.15) External Pull-down at
the Station Manager
PHY_n
For Open-source
(Active-high Mode)
If only one interrupt pin is required, each MDINT_n pin can be tied together to a single pull-up or pull-
down resistor in a wired-OR configuration.
When a PHY generates an interrupt, the MDINT_n pin is asserted (driven high or low, depending on
resistor connection) if the interrupt pin enable bit (MII register 25.15) is set.
4.14 LED Interface

The VSC8658 device drives up to four LEDs directly for each PHY port. All LED outputs are active-low
and are driven using 3.3 V from the VDD33 power supply. The pins, mainly used to sink the current of the
cathode side of an LED when active, can also supply power to the anode portion of LEDs when not in the
active state. This allows for two LED pins to be used to drive a multi-status, bi-colored LED.
4.14.1 LED Modes

Each LED pin can be configured to display different status information. Set the LED mode either by using
register 29 or the CMODE pin setting. For additional operating flexibility, LED output functions can be set
on a per-port basis.
The modes in the following table are equivalent to the setting used in register 29 to configure each LED
pin. For all LED states, 1 = pin held high (de-asserted), 0 = pin held low (asserted), and the blink/pulse-
stretch is dependent on the LED behavior setting in register 30.
Table 5 • LED Mode and Function Summary
Mode Function Name LED State and Description

0 Link/Activity(1) 1 = No link in any speed on any media interface.
0 = Valid link at any speed on any media interface.
Blink or pulse-stretch = Valid link at any speed on any media interface with
activity present.
1 Link1000/Activity 1 = No link in 1000BASE-T.
0 = Valid 1000BASE-T link.
Blink or pulse-stretch = Valid 1000BASE-T link with activity present.
2 Link100/Activity 1 = No link in 100BASE-TX.
0 = Valid 100BASE-TX link.
Blink or pulse-stretch = Valid 100BASE-TX link with activity present.
3 Link10/Activity 1 = No link in 10BASE-T.
0 = Valid 10BASE-T link.
Blink or pulse-stretch = Valid 10BASE-T link with activity present.

Table 5 • LED Mode and Function Summary (continued)
Mode Function Name LED State and Description

4 Link100/1000/Activity 1 = No link in 100BASE-TX or 1000BASE-T.
0 = Valid 100BASE-TX or 1000BASE-T link.
Blink or pulse-stretch = Valid 100BASE-TX or 1000BASE-T link with activity
present.
5 Link10/1000/Activity 1 = No link in 10BASE-T or 1000BASE-T.
0 = Valid 10BASE-T or 1000BASET-T link.
Blink or pulse-stretch = Valid 10BASE-T or 1000BASE-T link with activity
present.
6 Link10/100/Activity 1 = No link in 10BASE-T or 100BASE-TX.
0 = Valid 10BASE-T or 100BASE-TX link.
Blink or pulse-stretch = Valid 10BASE-T or 100BASE-TX link with activity
present.
7 Link100BASE-FX/ 1 = No link in 100BASE-FX or 1000BASE-X.
1000BASE-X/Activity 0 = Valid 100BASE-FX or 1000BASE-X link.
Blink or pulse-stretch = Valid 100BASE-FX or 1000BASE-X link with activity
present.
8 Duplex/Collision 1 = Link established in half-duplex mode, or no link established.
0 = Link established in full-duplex mode.
Blink or pulse-stretch = Link established in half-duplex mode but collisions are
present.
9 Collision 1 = No collision detected.
Blink or pulse-stretch = Collision detected.
10 Activity 1 = No activity present.
Blink or pulse-stretch = Activity present (becomes TX activity present if register
bit 30.14 is set to 1).
11 100BASE-FX/ 1 = No 100BASE-FX or 1000BASE-X activity present.
1000BASE-X Fiber Blink or pulse-stretch = 100BASE-FX or 1000BASE-X activity present (becomes
Activity RX activity present if register bit 30.14 is set to 1).
12 Auto-Negotiation Fault 1 = No auto-negotiation fault present.
0 = Auto-negotiation fault occurred.
13 Serial Mode Serial stream = See Serial LED Mode, page 20. Only relevant on PHY port 0 and
reserved in others.
14 Force LED Off 1 = De-asserts the LED.
15 Force LED On 0 = Asserts the LED.
1. Link/Activity can be configured to only display copper link and disable fiber link status by setting register bits 30.15 to 1.
4.14.2 LED Behavior

Several LED behaviors can be programmed into the VSC8658 device. Use the settings in register 30 to
program LED behavior, which includes the following:
LED Combine Enables an LED to display the status for a combination of primary and secondary
modes. This can be enabled or disabled for each LED pin. For example, a copper link running in
1000BASE-T mode and activity present can be displayed with one LED by configuring an LED pin to
Link1000/Activity mode. The LED asserts when linked to a 1000BASE-T partner and also blinks or
performs pulse-stretch when activity is either transmitted by the PHY or received by the Link Partner.
When disabled, the combine feature only provides status of the selected primary function. In this
example, only Link1000 asserts the LED, and the secondary mode, activity, does not display if the
combine feature is disabled.

LED Blink or Pulse-Stretch This behavior is used for activity and collision indication. This can be
uniquely configured for each LED pin. Activity and collision events can occur randomly and intermittently
throughout the link-up period. Blink is a 50% duty cycle oscillation of asserting and de-asserting an LED
pin. Pulse-stretch guarantees that an LED is asserted and de-asserted for a specific period of time when
activity is either present or not present. These rates can also be configured using a register setting.
Rate of LED Blink or Pulse-Stretch This behavior controls the LED blink rate or pulse-stretch length
when blink/pulse-stretch is enabled on an LED pin. The blink rate, which alternates between a high and
low voltage level at a 50% duty cycle, can be set to 2.5 Hz, 5 Hz, 10 Hz, or 20 Hz. For pulse-stretch, the
rate can be set to 50 ms, 100 ms, 200 ms, or 400 ms.
LED Pulsing Enable To provide additional power savings, the LEDs (when asserted) can be pulsed at
5 kHz, 20% duty cycle.
Fiber LED Disable This bit controls whether the LEDs indicate the Fiber and Copper status (default) or
the Copper status only.
4.14.3 Serial LED Mode

Optionally, the VSC8658 device can be configured so that access to all its LED signals is available
through two pins. This option is enabled by setting LED0 on PHY0 to Serial LED mode. When the mode
is enabled on PHY0, the device LED[0] pin becomes the serial data pin and the LED[1] pin becomes the
serial clock pin. All other LED pins can still be configured normally. The Serial LED mode clocks the 96
LED status bits on the rising edge of the serial clock.
The LED behavior settings (in device register 30) can also be used in Serial LED Mode. The controls are
used on a per-PHY basis, where the LED combine and LED blink or pulse-stretch setting of LED0_n for
each PHY is used to control the behavior of each bit of the serial LED stream for each corresponding
PHY.
The serial bitstream outputs, 1 through 96, of each LED signal are shown in the following table beginning
with PHY port 0 and ending with PHY port 7. The individual signals can be clocked in the order shown.
Table 6 • LED Serial Stream Order
PHY0 PHY1 PHY2 PHY3 PHY4 PHY5 PHY6 PHY7

Bit 1. Bit 13. Bit 25. Bit 37. Bit 49. Bit 61. Bit 73. Bit 85.
Link/Activity Link/Activity Link/Activity Link/Activity Link/Activity Link/Activity Link/Activity Link/Activity
Link1000/ Link1000/ Link1000/ Link1000/ Link1000/ Link1000/ Link1000/ Link1000/
Activity Activity Activity Activity Activity Activity Activity Activity
Link100/ Link100/ Link100/ Link100/ Link100/ Link100/ Link100/ Link100/
Bit 4. Link10/ Bit 16. Bit 28. Bit 40. Bit 52. Bit 64. Bit 76. Bit 88.
Activity Link10/ Link10/ Link10/ Link10/ Link10/ Link10/ Link10/
Activity Activity Activity Activity Activity Activity Activity
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit 6. Duplex/ Bit 18. Bit 30. Bit 42. Bit 54. Bit 66. Bit 78. Bit 90.
Collision Duplex/ Duplex/ Duplex/ Duplex/ Duplex/ Duplex/ Duplex/
Collision Collision Collision Collision Collision Collision Collision
Collision Collision Collision Collision Collision Collision Collision Collision
Bit 8. Activity Bit 20. Bit 32. Bit 44. Bit 56. Bit 68. Bit 80. Bit 92.
Activity Activity Activity Activity Activity Activity Activity

Table 6 • LED Serial Stream Order (continued)
PHY0 PHY1 PHY2 PHY3 PHY4 PHY5 PHY6 PHY7

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit 10. TX Bit 22. TX Bit 34. TX Bit 46. TX Bit 58. TX Bit 70. TX Bit 82. TX Bit 94. TX
Bit 11. RX Bit 23. RX Bit 35. RX Bit 47. RX Bit 59. RX Bit 71. RX Bit 83. RX Bit 95. RX
Bit 12. Auto- Bit 24. Auto- Bit 36. Auto- Bit 48. Auto- Bit 60. Auto- Bit 72. Auto- Bit 84. Auto- Bit 96. Auto-
Negotiation Negotiation Negotiation Negotiation Negotiation Negotiation Negotiation Negotiation
Fault Fault Fault Fault Fault Fault Fault Fault
4.15 GPIO Pins

The VSC8658 provides up to 8 dedicated general-purpose input/output (GPIO) pins. In addition, the
eight device SIGDET pins can also be configured as eight GPIO pins, resulting in a total of 16 GPIO pins.
All device GPIO pins and their behavior are controlled using registers. For more information, see
General-Purpose I/O Registers, page 52.
4.16 Testing Features

The VSC8658 device includes several testing features designed to make it easier to perform system-
level debugging and in-system production testing. This section describes the available features.
4.16.1 Ethernet Packet Generator (EPG)

The device EPG can be used at each of the 10/100/1000BASE-T speed settings for Copper Cat5 media
to isolate problems between the MAC and the VSC8658 device, or between a locally connected PHY
and its remote link partner. Enabling the EPG feature effectively disables all MAC interface transmit pins
and selects the EPG as the source for all data transmitted onto the twisted pair interface.
Important The EPG is intended for use with laboratory or in-system testing equipment only. Do not use
the EPG testing feature when the VSC8658 device is connected to a live network.
To enable the VSC8658 device EPG feature, set the device register bit 29E.15 to 1.
When the EPG is enabled, packet loss occurs during transmission of packets from the MAC to the PHY.
However, the PHY receive output pins to the MAC are still active when the EPG is enabled. If it is
necessary to disable the MAC receive pins as well, set the register bit 0.10 to 1.
When the device register bit 29E.14 is set to 1, the PHY begins transmitting Ethernet packets based on
the settings in registers 29E and 30E. These registers set:
• Source and destination addresses for each packet
• Packet size
• Inter-packet gap
• FCS state
• Transmit duration
• Payload pattern
If register bit 29E.13 is set to 0, register bit 29E.14 is cleared automatically after 30,000,000 packets are
transmitted.
4.16.2 CRC Counters

Two separate cyclical redundancy checking (CRC) counters are available on all PHYs in the VSC8658
device. There is a 14-bit good CRC counter available in register bits 18E.13:0 and a separate 8-bit
counter available in register bits 23E.7:0.
The device CRC counters operate in the 100BASE-FX/1000BASE-X over SerDes mode as well as in the
10/100/1000BASE-T mode testing as follows:

• After receiving a packet on the media interface, register bit 18E.15 is set and cleared after being
read. The packet then is counted by either the good CRC counter or the bad CRC counter. Both
CRC counters are also automatically cleared when read.
• The good CRC counter’s highest value is 10,000 packets. After it reaches this value, the counter
clears and continues to count additional packets beyond that value. The bad CRC counter stops
counting when it reaches its maximum counter limit of 255 packets.
4.16.3 Far-End Loopback

The far-end loopback testing feature is enabled by setting register bit 23.3 to 1. When enabled, it forces
incoming data from a link partner on the current media interface to be retransmitted back to the link
partner on the media interface as shown in the following illustration. In addition, the incoming data also
appears on the receive data pins of the MAC interface. Data present on the transmit data pins of the
MAC interface is ignored when using this testing feature.
Figure 13 • Far-End Loopback Diagram
Link Partner PHY_Port_n MAC

RX RXD
TX TXD
Cat5
4.16.4 Near-End Loopback

When the near-end loopback testing feature is enabled (by setting the device register bit 0.14 to 1), data
on the transmit data pins (TXD) is looped back onto the device receive data pins (RXD), as shown in the
following figure. When using this testing feature, no data is transmitted over the network.
Figure 14 • Near-End Loopback Diagram
Link Partner RX PHY Port_n MAC

RXD
TX TXD
Cat5
4.16.5 Connector Loopback

The connector loopback testing feature allows the twisted pair interface to be looped back externally.
When using this feature, the PHY must be connected to a loopback connector or a loopback cable. Pair
A should be connected to pair B, and pair C to pair D, as shown in the following figure. The connector
loopback feature functions at all available interface speeds.
Figure 15 • Connector Loopback Diagram
A RXD
B
Cat5 PHY Port_n MAC
C
TXD
D

When using the connector loopback testing feature, the device auto-negotiation, speed, and duplex
configuration is set using device registers 0, 4, and 9. For 1000BASE-T connector loopback, only the
following additional writes are required. Execute the additional writes in the following order:
1. Enable the 1000BASE-T connector loopback. Set register bit 24.0 to 1.
2. Disable pair swap correction. Set register bit 18.5 to 1.
4.16.6 VeriPHY Cable Diagnostics

The VSC8658 device includes a comprehensive suite of cable diagnostic functions that are available
using SMI reads and writes. These functions enable a variety of cable operating conditions and status to
be accessed and checked. The VeriPHY® suite has the ability to identify the cable length and operating
conditions and to isolate a variety of common faults that can occur on the Cat5 twisted pair cabling.
Note: If a link is established on the twisted pair interface in the 1000BASE-T mode, VeriPHY can run without
disrupting the link or disrupting any data transfer. However, if a link is established in 100BASE-TX or
10BASE-T, VeriPHY causes the link to drop while the diagnostics are running. After the diagnostics are
finished, the link is re-established.
The following diagnostic functions are part of the VeriPHY suite:
• Detecting coupling between cable pairs
• Detecting cable pair termination
• Determining cable length
Coupling Between Cable Pairs Shorted wires, improper termination, or high crosstalk resulting from
an incorrect wire map can cause error conditions, such as anomalous coupling between cable pairs. All
these conditions can prevent the device from establishing a link in any speed.
Cable Pair Termination Proper termination of Cat5 cable requires a 100 Ω differential impedance
between the positive and negative cable terminals. The IEEE standard 802.3 allows for a termination of
as high as 115 Ω or as low as 85 Ω. If the termination falls outside of this range, it is reported by the
VeriPHY diagnostics as an anomalous termination. The diagnostics can also determine the presence of
an open or shorted cable pair.
Cable Length When the Cat5 cable in an installation is properly terminated, VeriPHY reports the
approximate cable length in meters.
4.16.7 IEEE 1149.1 JTAG Boundary Scan

The VSC8658 device supports the Test Access Port (TAP) and Boundary Scan Architecture described in
the IEEE standard 1149.1. The device includes an IEEE 1149.1-compliant test interface, often referred to
as a “JTAG TAP Interface.”
The JTAG boundary scan logic on the VSC8658 device, accessed using its TAP interface, consists of a
boundary scan register and other logic control blocks. The TAP controller includes all IEEE-required
signals (TMS, TCK, TDI, and TDO), in addition to the optional asynchronous reset signal NTRST.
The following illustration shows the TAP and Boundary Scan Architecture.

Figure 16 • Test Access Port and Boundary Scan Architecture Diagram
Boundary-Scan Register
Device Identification
Register
Bypass Register
Control Mux, TDO

Instruction Register, DFF
Instruction Decode,
Control
TDI
Control
TMS
Test Access Port Select
NTRST Controller TDO Enable
TCK
After a TAP reset, the device identification register is serially connected between TDI and TDO by
default. The TAP instruction register is loaded either from a shift register (when a new instruction is
shifted in) or, if there is no new instruction in the shift register, a default value of 0110 (IDCODE) is
loaded. Using this method, there is always a valid code in the instruction register, and the problem of
toggling instruction bits during a shift is avoided. Unused codes are mapped to the BYPASS instruction.
4.16.8 JTAG Instruction Codes

The VSC8658 device supports the following instruction codes:
EXTEST Allows tests of the off-chip circuitry and board-level interconnections by sampling input pins
and loading data onto output pins. Outputs are driven by the contents of the boundary-scan cells, which
have to be updated with valid values (with the PRELOAD instruction) prior to the EXTEST instruction.
SAMPLE/PRELOAD Allows a snapshot of inputs and outputs during normal system operation to be
taken and examined. It also allows data values to be loaded into the boundary-scan cells prior to the
selection of other boundary-scan test instructions.
IDCODE Provides the version number (bits 31:28), part number (bits 27:12), and the manufacturer
identity (bits 11:1) to be serially read from the device.
The following table provides information about the meaning of IDCODE binary values stored in the
device JTAG registers.
Table 7 • JTAG Device Identification Register Description
Device Version Manufacturing

Description Number Model Number Identity LSB
Bit field 31 through 28 27 through 12 11 through 1 0
Binary value 0000 1000 0110 0101 1000 001 1001 1000 1

CLAMP Allows the state of the signals driven from the component pins to be determined from the
boundary scan register while the bypass register is selected as the serial path between TDI and TDO.
While the CLAMP instruction is selected, the signals driven from the component pins do not change.
HIGHZ Places the component in a state in which all of its system logic outputs are placed in a high-
impedance state. In this state, an in-circuit test system may drive signals onto the connections normally
driven by a component output without incurring a risk of damage to the component. This makes it
possible to use a board where not all of the components are compatible with the IEEE 1149.1 standard.
BYPASS The bypass register contains a single shift-register stage and is used to provide a minimum-
length serial path (one TCK clock period) between TDI and TDO to bypass the device when no test
operation is required.
The following table provides more information about the location and IEEE compliance of the JTAG
instruction codes used in the VSC8658. For more information about these IEEE specifications, visit the
IEEE Web site at www.IEEE.org.
Table 8 • JTAG Interface Instruction Codes
Register IEEE 1149.1 IEEE 1149.6

Instruction Code Selected Register Width Specification Specification
EXTEST 0000 Boundary-Scan 244 Mandatory
SAMPLE/PRELOA 0001 Boundary-Scan 244 Mandatory
D
IDCODE 0110 Device Identification 32 Optional
CLAMP 0010 Bypass Register 1 Optional
HIGHZ 0011 Bypass Register 1 Optional
BYPASS 1111 Bypass Register 1 Mandatory
EXTEST_PULSE 0100 Boundary-Scan Register 244 Mandatory
EXTEST_TRAIN 0101 Boundary-Scan Register 244 Mandatory
RESERVED 0111,
1000 through
1110
4.16.9 Boundary Scan Register Cell Order

All inputs and outputs are observed in the boundary scan register cells. All outputs are additionally driven
by the contents of boundary scan register cells. Bidirectional pins have all three related boundary scan
register cells: input, output, and control.
The complete boundary scan cell order is available as a BSDL file format on the Microsemi Web site at
www.microsemi.com.
4.17 IEEE 1149.6 AC-JTAG Boundary Scan Interface

The IEEE 1149.6 AC-JTAG solution integrated on all SerDes ports of the VSC8658 device extends the
capability of IEEE 1149.1 boundary scan for robust board-level testing. This interface is backward-
compatible to the IEEE 1149.1 standard.

Configuration
5 Configuration
The VSC8658 device can be configured using three different methods:

• Setting internal memory registers using the management interface
• Setting a combination of CMODE pins and registers
• Loading a configuration into an external EEPROM and connecting that device so that it writes
configuration information at system startup
5.1 Registers
This section provides information about how to configure the VSC8658 device using its internal memory
registers and the management interface. For information about configuring the device using the CMODE
pins, see CMODE, page 55. For information about setting up an external EEPROM to perform startup
configuration, see EEPROM, page 58.
The VSC8658 device uses three types of registers:
• IEEE standard and main device registers with addresses from 0 to 31
• Extended registers with addresses from 16E through 30E
• General-purpose input and output (GPIO) registers with addresses from 0G to 30G
The following illustration shows the relationship between the device registers and their address spaces.
Figure 17 • Register Space Diagram
0
1
2 0G
3 1G
. 2G
. 3G
IEEE 802.3 .
.
Standard Registers .
.
. .
. .
. .
. .
15 .
.
15G
16 16E 16G
17 17E GPIO Registers .
18 18E .
19 19E .
. . .
. . .
. Main Registers Extended Registers . .
. . .
. . .
. . .
. . .
. . .
30 30E 30G
31 0x0000 0x0001 0x0010
5.1.1 Reserved Registers

For main registers 16 through 31, extended registers 16E through 30E, and GPIO registers 0G through
30G, any bits marked as “Reserved” should be processed as read only and their states as undefined.

Configuration
5.1.2 Reserved Bits

In writing to registers with reserved bits, use a “read-modify-then-write” technique, where the entire
register is read but only the intended bits to be changed are modified. Reserved bits cannot be changed
and their read state cannot be considered static or unchanging.
5.2 IEEE Standard and Main Registers

In the VSC8658 device, the page space of the standard registers consists of the IEEE standard registers
and the Microsemi standard registers. The following table lists the names of the registers associated with
the addresses as dictated by the IEEE standard.
Table 9 • IEEE 802.3 Standard Registers
Register Address Register Name

0 Mode control
1 Mode status
2 PHY identifier 1
3 PHY identifier 2
4 Auto-negotiation advertisement
5 Auto-negotiation link partner ability
6 Auto-negotiation expansion
7 Auto-negotiation next-page transmit
8 Auto-negotiation link partner next-page receive
9 1000BASE-T control
10 1000BASE-T status
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 1000BASE-T status extension 1
The following table lists the names of the registers in the main page space of the device. These registers
are accessible only when register address 31 is set to 0x0000.
Table 10 • Main Registers

16 100BASE-TX status extension
17 1000BASE-T status extension 2
18 Bypass control
19 Reserved
20 Reserved
21 Reserved
22 Extended control and status
23 Extended PHY control 1
24 Extended PHY control 2

Configuration
Table 10 • Main Registers (continued)

25 Interrupt mask
26 Interrupt status
27 MAC interface auto-negotiation control and status
28 Auxiliary control and status
29 LED mode select
30 LED behavior
31 Extended register page access
5.2.1 Mode Control

The device register at memory address 0 controls several aspects of VSC8658 functionality. The
following table shows the available bit settings in this register and what they control.
Table 11 • Mode Control, Address 0 (0x00)
Bit Name Access Description Default

15 Software reset R/W This is a self-clearing bit that restores all 0
serial management interface (SMI) registers
to their default state, except for sticky and
super sticky bits.
1 = Reset asserted.
0 = Reset de-asserted.
You must wait 4 µs after setting this bit to
initiate another SMI register access.
14 Loopback R/W 1 = Loopback enabled. 0
0 = Loopback disabled.
When loop back is enabled, the device
functions at the current speed setting and
with the current duplex mode setting (bit 8 of
this register).
13 LSB for speed R/W See bit 6 below. 0
selection
12 Auto-negotiation R/W 1 = Auto-negotiation enabled. 1
enable 0 = Auto-negotiation disabled.
11 Power-down R/W 1 = Power-down enabled. 0
10 Isolate R/W 1 = Disable MAC interface outputs and ignore 0
MAC interface inputs.
9 Restart auto- R/W This is a self-clearing bit. 0
negotiation 1 = Restart auto-negotiation on media
interface.
8 Duplex R/W 1 = Full-duplex. 0
0 = Half-duplex.
7 Collision test enable R/W 1 = Collision test enabled. 0
6, 13 Forced speed R/W MSB = bit 6, LSB = bit 13. 10
selection 00 = 10 Mbps.
01 = 100 Mbps.
10 = 1000 Mbps.
11 = Reserved.

Configuration
Table 11 • Mode Control, Address 0 (0x00) (continued)

5:0 Reserved 000000
5.2.2 Mode Status

The register at address 1 in the device main registers space allows you to read the currently enabled
mode setting. The following table shows possible readouts of this register.
Table 12 • Mode Status, Address 1 (0x01)

15 100BASE-T4 RO 1 = 100BASE-T4 capable. 0
capability
14 100BASE-TX FDX RO 1 = 100BASE-TX FDX capable. 1
capability
13 100BASE-TX HDX RO 1 = 100BASE-TX HDX capable. 1
capability
12 10BASE-T FDX RO 1 = 10BASE-T FDX capable. 1
capability
11 10BASE-T HDX RO 1 = 10BASE-T HDX capable. 1
capability
10 100BASE-T2 FDX RO 1 = 100BASE-T2 FDX capable. 0
capability
9 100BASE-T2 HDX RO 1 = 100BASE-T2 HDX capable. 0
capability
8 Extended status RO 1 = Extended status information present in 1
enable register 15.
7 Reserved RO 0
6 Preamble RO 1 = MF preamble may be suppressed. 1
suppression 0 = MF always required.
capability
5 Auto-negotiation RO 1 = Auto-negotiation complete. 0
complete
4 Remote fault RO This bit latches high. 0
1 = Far-end fault detected.
3 Auto-negotiation RO 1 = Auto-negotiation capable. 1
capability
2 Link status RO This bit latches low. 0
1 = Link is up.
1 Jabber detect RO This bit latches high. 0
1 = Jabber condition detected.
0 Extended capability RO 1 = Extended register capable. 1

Configuration
5.2.3 Device Identification

All 16 bits in both register 2 and register 3 in the VSC8658 device are used to provide information
associated with aspects of the device identification. The following tables list the readouts you can expect.
Table 13 • Identifier 1, Address 2 (0x02)

15:0 Organizationally unique RO OUI most significant bits (3:18) 0x0007
identifier (OUI)
Table 14 • Identifier 2, Address 3 (0x03)

15:10 OUI RO OUI least significant bits (19:24) 0x0001
9:4 Microsemi model RO VSC8658 110101
number
3:0 Device revision number RO 0000
5.2.4 Auto-Negotiation Advertisement

The bits in address 4 in the main registers space control the VSC8658 device ability to notify other
devices of the status of its auto-negotiation feature. The following table shows the available settings and
readouts.
Table 15 • Device Auto-Negotiation Advertisement, Address 4 (0x04)

15 Next page transmission R/W 1 = Request enabled 0
request
14 Reserved RO 0
13 Transmit remote fault R/W 1 = Enabled 0
12 Reserved technologies R/W 0
11 Advertise asymmetric R/W 1 = Advertises asymmetric pause CMODE
pause
10 Advertise symmetric R/W 1 = Advertises symmetric pause CMODE
pause
9 Advertise R/W 1 = Advertises 100BASE-T4 0
100BASE-T4
8 Advertise R/W 1 = Advertise 100BASE-TX FDX CMODE
100BASE-TX FDX
7 Advertise R/W 1 = Advertises 100BASE-TX HDX CMODE
100BASE-TX HDX
6 Advertise R/W 1 = Advertises 10BASE-T FDX CMODE
10BASE-T FDX
5 Advertise R/W 1 = Advertises 10BASE-T HDX CMODE
10BASE-T HDX
4:0 Advertise selector R/W 00001

Configuration
5.2.5 Link Partner Auto-Negotiation Capability

The bits in main register 5 enable you to determine if the Cat5 link partner (LP) used with the VSC8658
device is compatible with the auto-negotiation functionality.
Table 16 • Auto-Negotiation Link Partner Ability, Address 5 (0x05)

15 LP next page RO 1 = Requested 0
transmission request
14 LP acknowledge RO 1 = Acknowledge 0
13 LP remote fault RO 1 = Remote fault 0
12 Reserved RO 0
11 LP advertise RO 1 = Capable of asymmetric pause 0
asymmetric pause
10 LP advertise RO 1 = Capable of symmetric pause 0
symmetric pause
9 LP advertise RO 1 = Capable of 100BASE-T4 0
100BASE-T4
8 LP advertise RO 1 = Capable of 100BASE-TX FDX 0
100BASE-TX FDX
7 LP advertise RO 1 = Capable of 100BASE-TX HDX 0
100BASE-TX HDX
6 LP advertise RO 1 = Capable of 10BASE-T FDX 0
10BASE-T FDX
5 LP advertise RO 1 = Capable of 10BASE-T HDX 0
10BASE-T HDX
4:0 LP advertise selector RO 00000
5.2.6 Auto-Negotiation Expansion

The bits in main register 6 work together with those in register 5 to indicate the status of the LP auto-
negotiation functioning. The following table shows the available settings and readouts.
Table 17 • Auto-Negotiation Expansion, Address 6 (0x06)

15:5 Reserved RO 00000000000
4 Parallel detection RO This bit latches high. 0
fault 1 = Parallel detection fault.
3 LP next page capable RO 1 = LP is next page capable. 0
2 Local PHY next page RO 1 = Local PHY is next page capable. 1
capable
1 Page received RO This bit latches low. 0
1 = New page is received.
0 LP is auto-negotiation RO 1 = LP is capable of auto-negotiation. 0
capable

Configuration
5.2.7 Transmit Auto-Negotiation Next Page

The settings in register 7 in the main registers space provide information about the number of pages in
an auto-negotiation sequence. The following table shows the settings available.
Table 18 • Auto-Negotiation Next Page Transmit, Address 7 (0x07)

15 Next page R/W 1 = More pages follow 0
14 Reserved RO 0
13 Message page R/W 1 = Message page 1
0 = Unformatted page
12 Acknowledge 2 R/W 1 = Complies with request 0
0 = Cannot comply with request
11 Toggle RO 1 = Previous transmitted LCW = 0 0
0 = Previous transmitted LCW = 1
10:0 Message R/W 00000000
/unformatted code 001
5.2.8 Auto-Negotiation Link Partner Next Page Receive

The bits in register 8 of the main register space work together with register 7 to determine certain aspects
of the LP auto-negotiation. The following table shows the possible readouts.
Table 19 • Auto-Negotiation LP Next Page Receive, Address 8 (0x08)

15 LP next page RO 1 = More pages follow 0
14 Acknowledge RO 1 = LP acknowledge 0
13 LP message page RO 1 = Message page 0
0 = Unformatted page
12 LP Acknowledge 2 RO 1 = LP complies with request 0
11 LP toggle RO 1 = Previous transmitted LCW = 0 0
0 = Previous transmitted LCW = 1
10:0 LP message RO 00000000000
/unformatted code
5.2.9 1000BASE-T Control

The VSC8658 device’s 1000BASE-T functionality is controlled by the bits in register 9 of the main
register space. The following table shows the settings and readouts available.
Table 20 • 1000BASE-T Control, Address 9 (0x09)

15:13 Transmitter test R/W 000 = Normal. 000
mode 001 = Mode 1: Transmit waveform test.
010 = Mode 2: Transmit jitter test as master.
011 = Mode 3: Transmit jitter test as slave.
100 = Mode 4: Transmitter distortion test.
101 to 111 = Reserved: Operation not defined.

Configuration
Table 20 • 1000BASE-T Control, Address 9 (0x09) (continued)

12 Master/slave R/W 1 = Master/slave manual configuration enabled. 0
manual
configuration
11 Master/slave R/W This register is only valid when bit 9.12 is set to 1. 0
value 1 = Configure PHY as master during negotiation.
0 = Configure PHY as slave during negotiation.
10 Port type R/W 1 = Multi-port device. 1
0 = Single-port device.
9 1000BASE-T R/W 1 = PHY is 1000BASE-T FDX capable. CMODE
FDX capability
8 1000BASE-T R/W 1 = PHY is 1000BASE-T HDX capable. CMODE
HDX capability
7:0 Reserved R/W 0x00
Note Transmitter Test mode (bits 15:13) operates in the manner described in IEEE standard 802.3,
section 40.6.1.1.2. When using any of the Transmitter Test modes, the Auto-Media Sense functionality
must be disabled. For more information, see Extended PHY Control Set 1, page 37.
5.2.10 1000BASE-T Status

The bits in register 10 of the main register space allow you to read the status of the 1000BASE-T
communications enabled in the device. The following table shows the readouts.
Table 21 • 1000BASE-T Status, Address 10 (0x0A)

15 Master/slave RO This bit latches high. 0
configuration fault 1 = Master/slave configuration fault detected.
0 = No master/slave configuration fault
detected.
14 Master/slave RO 1 = Local PHY configuration resolved to 1
configuration master.
resolution 0 = Local PHY configuration resolved to slave.
13 Local receiver status RO 1 = Local receiver is operating normally. 0
12 Remote receiver RO 1 = Remote receiver OK. 0
status
11 LP 1000BASE-T FDX RO 1 = LP 1000BASE-T FDX capable. 0
capability
10 LP 1000BASE-T HDX RO 1 = LP 1000BASE-T HDX capable. 0
capability
9:8 Reserved RO 00
7:0 Idle error count RO This is a self-clearing bit. 0x00
5.2.11 Main Registers Reserved Addresses

In the VSC8658 device main registers page space, registers 11 through 15 (0x0B through 0x0E) are
reserved.

Configuration
5.2.12 1000BASE-T Status Extension 1

Register 15 provides additional information about the operation of the device 1000BASE-T
communications. The following table shows the readouts available.
Table 22 • 1000BASE-T Status Extension 1, Address 15 (0x0F)

15 1000BASE-X FDX RO 1 = PHY is 1000BASE-X FDX capable 0
capability
14 1000BASE-X HDX RO 1 = PHY is 1000BASE-X HDX capable 0
capability
13 1000BASE-T FDX RO 1 = PHY is 1000BASE-T FDX capable 1
capability
12 1000BASE-T HDX RO 1 = PHY is 1000BASE-T HDX capable 1
capability
11:0 Reserved RO 0x000
5.2.13 100BASE-TX Status Extension

Register 16 in the main registers page space of the VSC8658 device provides additional information
about the status of the device’s 100BASE-TX operation.
Table 23 • 100BASE-TX Status Extension, Address 16 (0x10)

15 100BASE-TX RO 1 = Descrambler locked. 0
Descrambler
14 100BASE-TX lock RO This is a self-clearing bit. 0
error 1 = Lock error detected.
13 100BASE-TX RO This is a self-clearing bit. 0
disconnect state 1 = PHY 100BASE-TX link disconnect
detected.
12 100BASE-TX current RO 1 = PHY 100BASE-TX link active. 0
link status
11 100BASE-TX receive RO This is a self-clearing bit. 0
error 1 = Receive error detected.
10 100BASE-TX RO This is a self-clearing bit. 0
transmit error 1 = Transmit error detected.
9 100BASE-TX SSD RO This is a self-clearing bit. 0
error 1 = Start-of-stream delimiter error detected.
8 100BASE-TX ESD RO This is a self-clearing bit. 0
error 1 = End-of-stream delimiter error detected.
7:0 Reserved RO

Configuration
5.2.14 1000BASE-T Status Extension 2

The second status extension register is at address 17 in the device main registers space. It provides
information about another set of parameters associated with 1000BASE-T communications. For
information about the first status extension register, see Table 23, page 34.
Table 24 • 1000BASE-T Status Extension 2, Address 17 (0x11)

15 1000BASE-T RO 1 = Descrambler locked. 0
descrambler
14 1000BASE-T lock RO This is a self-clearing bit. 0
error 1 = Lock error detected.
13 1000BASE-T RO This is a self-clearing bit. 0
disconnect state 1 = PHY 1000BASE-T link disconnect
detected.
12 1000BASE-T current RO 1 = PHY 1000BASE-T link active. 0
link status
11 1000BASE-T receive RO This is a self-clearing bit. 0
error 1 = Receive error detected.
10 1000BASE-T transmit RO This is a self-clearing bit. 0
error 1 = Transmit error detected.
9 1000BASE-T SSD RO This is a self-clearing bit. 0
error 1 = Start-of-stream delimiter error detected.
8 1000BASE-T ESD RO This is a self-clearing bit. 0
error 1 = End-of-stream delimiter error detected.
7 1000BASE-T carrier RO This is a self-clearing bit. 0
extension error 1 = Carrier extension error detected.
6:0 Reserved RO
5.2.15 Bypass Control

The bits in the Bypass Control register in the VSC8658 device control aspects of functionality in effect
when the device is disabled so that traffic can bypass it in your design. The following table shows the
settings available.
Table 25 • Bypass Control, Address 18 (0x12)

15 Transmit disable R/W 1 = PHY transmitter disabled. 0
14:9 Reserved RO
8 1000BASE-T R/W 1 = Enabled. 0
transmitter test clock
7 Auto MDI-X at forced R/W This is a sticky bit. 1
10/100 1 = Disable Auto MDI-X at forced 10/100
speeds.
6 Reserved RO
5 Disable pair swap R/W This is a sticky bit. 0
correction 1 = Disable the automatic pair swap correction.

Configuration
Table 25 • Bypass Control, Address 18 (0x12) (continued)

4 Disable polarity R/W This is a sticky bit. 0
correction 1 = Disable polarity inversion correction on
each subchannel.
3 Parallel detect control R/W This is a sticky bit. 1
1 = Do not ignore advertised ability.
0 = Ignore advertised ability.
2 Reserved RO
1 Disable automatic R/W This is a sticky bit. 0
1000BASE-T next 1 = Disable automatic 1000BASE-T next page
page exchange exchanges.
0 CLKOUT output R/W This is a sticky bit. CMODE
enable 1 = Enable clock output pin.
Note If bit 18.1 is set to 1 in this register, automatic exchange of next pages is disabled, and control is
returned to the user through the SMI after the base page is exchanged. The user then must send the
correct sequence of next pages to the link partner, determine the common capabilities, and force the
device into the correct configuration following the successful exchange of pages.
5.2.16 Reserved Main Address Space

The bits in register 19, register 20, and register 21 (0x13, 0x14, and 0x15, respectively) are reserved.
5.2.17 Extended Control and Status

The bits in register 22 provide additional device control and readouts. The following table shows the
settings available.
Table 26 • Extended Control and Status, Address 22 (0x16)

15 Force 10BASE-T R/W This is a sticky bit. 0
link high 1 = Bypass link integrity test.
0 = Enable link integrity test.
14 Jabber detect R/W This is a sticky bit. 0
disable 1 = Disable jabber detect.
13 Disable 10BASE-T R/W This is a sticky bit. 1
echo 1 = Disable 10BASE-T echo.
12 Reserved RO
11:10 10BASE-T squelch R/W This is a sticky bit. 00
control 00 = Normal squelch.
01 = Low squelch.
10 = High squelch.
11 = Reserved.
9 Sticky reset enable R/W This is a super-sticky bit. 1
1 = Enabled.
8 EOF Error RO This bit is self-clearing. 0
1 = EOF error detected.
7 10BASE-T RO This bit is self-clearing. 0
disconnect state 1 = 10BASE-T link disconnect detected.

Configuration
Table 26 • Extended Control and Status, Address 22 (0x16) (continued)

6 10BASE-T link RO 1 = 10BASE-T link active. 0
status
5:1 Reserved RO
0 SMI broadcast R/W This is a sticky bit. 0
write 1 = Enabled.
The following information applies to the extended control and status bits:
• When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link
pass status.
• When bits 22.11:0 are set to 00, the squelch threshold levels are based on the IEEE standard for
10BASE-T. When set to 01, the squelch level is decreased, which may improve the bit error rate
performance on long loops. When set to 10, the squelch level is increased and may improve the bit
error rate in high-noise environments.
• When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this
bit causes all sticky register bits to change to their default values upon software reset. Super-sticky
bits retain their values upon software reset regardless of the setting of bit 22.9.
• When bit 22.0 is set, if a write to any PHY register (registers 0 through 31, including extended
registers), the same write is broadcast to all PHYs. For example, if bit 22.0 is set to 1 and a write to
PHY_0 is executed (register 0 is set to 0x1040), all PHYs’ register 0s are set to 0x1040. Disabling
this bit restores normal PHY write operation. Reads are still possible when this bit is set, but the
value that is read corresponds only to the particular PHY being addressed.
5.2.18 Extended PHY Control Set 1

The bits in the extended control set control the MAC auto-negotiation function, the 100BASE-FX SerDes
function, and report SGMII alignment errors and EEPROM status. The following table shows the settings
available.
Table 27 • Extended PHY Control 1, Address 23 (0x17)

15:14 Reserved RO
13 MAC interface R/W This is a super-sticky bit. CMODE
auto-negotiation 1 = Enabled.
12 MAC interface mode R/W This is a super-sticky bit. 0
1 = 1000BASE-X.
0 = SGMII.
11 AMS preference R/W This is a super-sticky bit. 0
1 = Cat5 copper preferred.
0 = SerDes fiber/SFP preferred.

Configuration
Table 27 • Extended PHY Control 1, Address 23 (0x17) (continued)

10:8 Media operating R/W This is a super-sticky bit. CMODE
mode 000 = Cat5 copper only.
001 = SerDes fiber/SFP pass-through mode
only. No auto-negotiation performed in the
PHY.
010 = 1000BASE-X fiber/SFP media only with
auto-negotiation performed by the PHY.
011 = 100BASE-X fiber/SFP on the fiber
media pins only
101 = Auto-Media Sense with Cat5 media or
SerDes fiber/SFP pass-through mode.
1000BASE-X fiber/SFP media with auto-
negotiation performed by PHY.
100BASE-FX fiber/SFP media.
100 = Reserved.
7:6 Force AMS override R/W 00 = Normal auto-media selection (AMS). 00
01 = Force AMS to select SerDes media only.
10 = Force AMS to select copper media only.
11 = Reserved.
5:4 Reserved RO
3 Far-end loopback R/W 1 = Enabled. 0
mode
2 Reserved RO
1 SGMII alignment RO This is a self-clearing bit. 0
error status 1 = Alignment error detected since last read.
0 EEPROM status RO 1 = EEPROM present on EECLK and EEDAT 0
pins.
Note After configuring bits 13:8 of the extended PHY control register set 1, a software reset (register 0,
bit 15) must be written to change the device operating mode.
5.2.19 Extended PHY Control Set 2

The second set of extended controls is located in register 24 in the main register space for the device.
The following table shows the settings and readouts available.
Table 28 • Extended PHY Control 2, Address 24 (0x18)

15:13 100BASE-TX edge R/W This is a sticky bit. 110
rate control 011 = +5 Edge rate (slowest).
010 = +4 Edge rate.
001 = +3 Edge rate.
000 = +2 Edge rate.
111 = +1 Edge rate.
110 = Default edge rate.
101 = –1 Edge rate.
100 = –2 Edge rate (fastest).
12 PICMG 2.16 reduced R/W This is a sticky bit. 0
power mode 1 = Enabled.

Configuration
Table 28 • Extended PHY Control 2, Address 24 (0x18) (continued)

11:9 Reserved RO
8:7 SGMII input preamble R/W This is a sticky bit. 00
00 = No SGMII preamble required.
01 = One-byte SGMII preamble required.
10 = Two-byte SGMII preamble required.
11 = Reserved.
6 SGMII output R/W This is a sticky bit. 1
preamble 0 = No SGMII preamble.
1 = Two-byte SGMII preamble.
5:4 Jumbo packet mode R/W This is a sticky bit. 00
00 = Normal IEEE 1.5 kB packet length.
01 = 9 kB jumbo packet length (12 kB with
60 ppm or better reference clock).
10 = 12 kB jumbo packet length (16 kB with
70 ppm or better reference clock).
11 = Reserved.
3:1 100BASE-TX R/W 011 = +3 Amplitude setting (largest). 000
transmitter amplitude 010 = +2 Amplitude setting.
control 001 = +1 Amplitude setting.
000 = Default amplitude.
111 = –1 Amplitude setting.
100 = –4 Amplitude setting (smallest).
0 1000BASE-T R/W 1 = Enabled. 0
connector loopback
Note When bits 5:4 are set to Jumbo Packet mode, the default maximum packet values are based on
100 ppm driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY
as specified in the bit description results in a higher Jumbo packet length.
5.2.20 Interrupt Mask

The bits in register 25 control the device interrupt mask. The following table shows the settings available.
Table 29 • Interrupt Mask, Address 25 (0x19)

15 MDINT interrupt status enable R/W This is a sticky bit. 0
1 = Enabled.
14 Speed state change mask R/W This is a sticky bit. 0
1 = Enabled.
13 Link state change mask R/W This is a sticky bit. 0
1 = Enabled.
12 FDX state change mask R/W This is a sticky bit. 0
1 = Enabled.
11 Auto-negotiation error mask R/W 1 = Enabled. 0
10 Auto-negotiation complete mask R/W This is a sticky bit. 0
1 = Enabled.

Configuration
Table 29 • Interrupt Mask, Address 25 (0x19) (continued)

9 Inline powered device (PoE) detect mask R/W This is a sticky bit. 0
1 = Enabled.
8:5 Reserved RO
4 AMS media changed mask R/W This is a sticky bit. 0
1 = Enabled.
3 Reserved RO
2 Link speed downshift detect mask R/W This is a sticky bit. 0
1 = Enabled.
1 Master/Slave resolution error mask R/W This is a sticky bit. 0
1 = Enabled.
0 Reserved RO
Note When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the
state of bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted.
5.2.21 Interrupt Status

The status of interrupts already written to the device are available for reading from register 26 in the main
registers space. The following table shows the readouts you can expect.
Table 30 • Interrupt Status, Address 26 (0x1A)

15 Interrupt status RO This is a self-clearing bit. 0
1 = Interrupt pending.
14 Speed state change status RO This is a self-clearing bit. 0
13 Link state change status RO This is a self-clearing bit. 0
12 FDX state change status RO This is a self-clearing bit. 0
11 Auto-negotiation error status RO This is a self-clearing bit.
10 Auto-negotiation complete status RO This is a self-clearing bit. 0
9 Inline powered device detect status RO This is a self-clearing bit. 0
8:5 Reserved RO
4 AMS media changed status RO This is a self-clearing bit. 0
3 Reserved RO
2 Link speed downshift detect status RO This is a self-clearing bit. 0
1 Master/Slave resolution error status RO This is a self-clearing bit. 0
0 Reserved RO

Configuration
The following information applies to the interrupt status bits:

• All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is set, the cause of
the interrupt can be read by reading bits 26.14:0.
• For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert.
• For bit 26.2, bits 4.8:5 must be set for this interrupt to assert.
5.2.22 MAC Interface Auto-Negotiation Control and Status

Device auto-negotiation for the MAC interface is controlled in register 27. The same register is used to
check the status of those parameters. The following table shows the settings available.
Table 31 • MAC Auto-Negotiation Control and Status, Address 27 (0x1B)

15 MAC or media R/W This is a sticky bit. 0
interlock 1 = MAC interface disabled when media link
down.
0 = MAC interface not suppressed by media
link status.
14 MAC or media R/W This is a sticky bit. 0
restart 1 = MAC interface restarts its auto-negotiation
auto-negotiation if the media link changes.
interlock 0 = MAC interface does not automatically
change if media link changes.
13 MAC interface R/W This is a sticky bit. 0
auto-negotiation 1 = If MAC auto-negotiation is enabled, this
auto-sense allows the MAC interface to be able to link to
MACs with auto-negotiation enabled and
disabled.
0 = Normal MAC auto-negotiation behavior.
12 MAC interface R/W This is a self-clearing bit. 0
auto-negotiation 1 = Restart auto-negotiation.
restart
11:10 Reserved RO
9:8 Remote fault RO Corresponds to the remote fault bits sent by 00
detected from MAC the MAC during auto-negotiation.
7 Asymmetric pause RO Corresponds to the asymmetric pause bit sent 0
advertised by the by the MAC during auto-negotiation.
MAC
6 Symmetric pause RO Corresponds to the symmetric pause bit sent 0
advertised by the by the MAC during auto-negotiation.
MAC
5 Full-duplex RO Corresponds to the full-duplex bit sent by the 0
advertised by the MAC during auto-negotiation.
MAC
4 Half-duplex RO Corresponds to the half-duplex bit sent by the 0
advertised by the MAC during auto-negotiation.
MAC
3 MAC RO 1 = MAC is auto-negotiation capable. 0
auto-negotiation
capable
2 MAC interface link RO 1 = The MAC interface is actively linked. 0
status

Configuration
Table 31 • MAC Auto-Negotiation Control and Status, Address 27 (0x1B) (continued)

1 MAC interface RO 1 = The MAC interface auto-negotiation is 0
auto-negotiation complete.
complete
0 Reserved RO
5.2.23 Device Auxiliary Control and Status

Register 28 provides control and status information for several device functions not controlled or
monitored by other device registers. The following table shows the settings available and the readouts
you can expect.
Table 32 • Auxiliary Control and Status, Address 28 (0x1C)

15 Auto-negotiation RO Duplicate of bit 1.5. 0
complete
14 Auto-negotiation RO Inverted duplicate of bit 0.12. 0
disabled
13 MDI/MDI-X crossover RO 1 = MDI/MDI-X crossover performed 0
indication internally.
12 CD pair swap RO 1 = CD pairs are swapped. 0
11 A polarity inversion RO 1 = Polarity swap on pair A. 0
10 B polarity inversion RO 1 = Polarity swap on pair B. 0
9 C polarity inversion RO 1 = Polarity swap on pair C. 0
8 D polarity inversion RO 1 = Polarity swap on pair D. 0
7 ActiPHY link status R/W This is a sticky bit. CMODE
time-out control [1] Bits 7 and 2 are part of the ActiPHY Link
Status time-out control.
Bit 7 is the MSB.
00 = 1 second.
01 = 2 seconds.
10 = 3 seconds.
11 = 4 seconds.
6 ActiPHY mode enable R/W This is a sticky bit. 0
1 = Enabled.
5 FDX status RO 1 = Full-duplex. 00
0 = Half-duplex.
4:3 Speed status RO 00 = Speed is 10BASE-T. 0
01 = Speed is 100BASE-TX or 100BASE-FX.
10 = Speed is 1000BASE-T or 1000BASE-X.
11 = Reserved.
2 ActiPHY link status R/W This is a sticky bit. 0
time-out control [0] Bits 7 and 2 are part of the ActiPHY Link
Status time-out control.
Bit 7 is the MSB.
00 = 1 second.
01 = 2 seconds.
10 = 3 seconds.
11 = 4 seconds.

Configuration
Table 32 • Auxiliary Control and Status, Address 28 (0x1C) (continued)

1:0 Reserved RO
5.2.24 LED Mode Select

The device LED outputs are controlled using the bits in register 29 of the main register space. The
following table shows the information you need to access the functionality of each of the outputs. For
information about the LED modes referenced in the table, see Table 34, page 43.
Table 33 • LED Mode Select, Address 29 (0x1D)

15:12 LED3 mode select R/W This is a sticky bit. CMODE
Select from LED modes 0 through 15.
The following table shows the LED functional modes that can be programmed into any of the device’s
LED outputs. For more information about accessing or reading the status of the outputs, see Table 33,
page 43.
Table 34 • Available LED Mode Settings
Bit Setting LED Indicates

0000 Link/activity, Mode 0
0001 Link1000/activity, Mode 1
0100 Link100/1000/activity, Mode 4
0111 Link100BASE-FX/1000BASE-X/activity, Mode 7
1000 Duplex/collision, Mode 8
1001 Collision, Mode 9
1010 Activity, Mode 10
1011 100BASE-FX/1000BASE-X/fiber activity, Mode 11
1100 Auto-negotiation fault, Mode 12
1101 Serial mode (on LED0 and LED1 on PHY0 only), Mode 13
1110 Force LED off, Mode 14
1111 Force LED on, Mode 15

Configuration
5.2.25 LED Behavior

The bits in register 30 control and enable you to read the status of the pulse or blink rate of the device
LEDs. The following table shows the settings you can write to the register or read from the register.
Table 35 • LED Behavior, Address 30 (0x1E)

15 Copper and fiber LED R/W This is a sticky bit. 0
combine disable 0 = Combine enabled
(Copper/Fiber on
Link/LinkXXXX/Activity LED).
1 = Disable combination
(Link/LinkXXXX/Activity LED
indicates copper only).
14 Activity output select R/W This is a sticky bit. 0
1 = Activity LED becomes
TX_Activity and fiber activity LED
becomes RX_Activity.
0 = TX and RX activity both
displayed on activity LEDs.
13 Reserved RO
12 LED pulsing enable R/W This is a sticky bit. 0
0 = Normal operation.
1 = LEDs pulse with a 5-kHz, 20%
duty cycle when active.
11:10 LED blink/ R/W This is a sticky bit. CMODE
pulse-stretch rate 00 = 2.5-Hz blink rate / 400 ms
pulse-stretch.
01 = 5-Hz blink rate / 200 ms pulse-
stretch.
10 = 10-Hz blink rate / 100 ms
pulse-stretch.
11 = 20-Hz blink rate / 50 ms pulse-
stretch.
9 Reserved RO
8 LED3 pulse-stretch/ R/W This is a sticky bit. CMODE
blink select 1 = Pulse-stretch.
0 = Blink.
0 = Blink.
0 = Blink.
0 = Blink.
4 Reserved RO

Configuration
Table 35 • LED Behavior, Address 30 (0x1E) (continued)

3 LED3 combine R/W This is a sticky bit. CMODE
feature disable 0 = Combine enabled (link/activity,
duplex/collision).
1 = Disable combination (link only,
duplex only).
duplex/collision).
duplex only).
duplex/collision).
duplex only).
duplex/collision).
duplex only).
Note: Bits 29.11:10 are controlled only by port 0 and affect the behavior of all ports.
5.3 Extended Page Registers

To provide functionality beyond the IEEE802.3-specified 32 registers and main device registers, the
VSC8658 device includes an extended set of registers that provide an additional 15 register spaces.
To access the extended page registers (16E through 30E), enable extended register access by writing
0x0001 to register 31. For more information, see Table 37, page 46.
When extended page register access is enabled, reads and writes to registers 16 through 30 affect the
extended registers 16E through 30E instead of those same registers in the IEEE-specified register
space. Registers 0 through 15 are not affected by the state of the extended page register access.
Writing 0x0000 to register 31 restores the main register access.
The following table lists the addresses and register names in the extended register page space. These
registers are accessible only when the device register 31 is set to 0x0001.
Table 36 • Extended Registers Page Space

16E SerDes Media control
17E SerDes MAC/Media control
18E CRC good counter
19E SIGDET polarity control
20E Extended PHY control 3 (ActiPHY)
21E EEPROM interface status and control
22E EEPROM data read or write
23E Extended PHY control 4 (PoE and CRC error counter)
24E VeriPHY 1

Configuration
Table 36 • Extended Registers Page Space (continued)

25E VeriPHY 2
26E VeriPHY 3
27E Reserved
28E Reserved
29E Ethernet packet generator (EPG) 1
30E EPG 2
5.3.1 Extended Page Access

The register at address 31 controls the access to both the extended and GPIO registers for the VSC8658
device. Accessing the GPIO page register space is similar to accessing the extended page registers. The
following table shows the settings available.
Table 37 • Extended Page Access, Address 31 (0x1F)

15:0 Extended/GPIO page R/W 0x0000 = Register 16 through 30 accesses 0x0000
register access main register space
0x0001 = Register 16 through 30 accesses
extended register space
0x0010 = Register 0 through 30 accesses
GPIO register space
5.3.2 SerDes Media Control

Register 16E, which is accessible only when extended register access is enabled, controls the SerDes
media interface. The following table shows the settings available.
Table 38 • SerDes Media Auto-Negotiation Control/Status, Address 16E (0x10)

15:14 Transmit remote fault R/W Remote fault indication sent to link partner 00
(LP).
13:12 Link partner (LP) RO Remote fault bits sent by LP during auto- 00
remote fault negotiation.
11 Parallel detect R/W 1 = Enables parallel detect of auto- 0
negotiation enabled and disabled devices.
10 SerDes media signal RO Signal detect indication on media interface. 0
detect
9:0 Reserved RO

Configuration
5.3.3 SerDes MAC/Media Control

Register 17E, which is accessible only when extended register access is enabled, controls the
transmitter and receiver of the VSC8658 device SerDes MAC/Media. The following table shows the
settings available.
Table 39 • SerDes MAC Control, Address 17E (0x11)

15:8 Reserved RO
7:5 SerDes media output R/W This is a sticky bit. 100
swing control 000 = 400 mV (peak-to-peak).
001 = 600 mV (peak-to-peak).
110 and 111 = Reserved.
4:2 SerDes MAC output R/W This is a sticky bit. 100
swing control 000 = 400 mV (peak-to-peak).
110 and 111 = Reserved.
1:0 Reserved RO
5.3.4 CRC Good Counter

Register 18E makes it possible to read the contents of the CRC good counter; the number of CRC
routines that have executed successfully. The following table shows the readouts you can expect.
Table 40 • CRC Good Counter, Address 18E (0x12)

15 Packet since last read RO This is a self-clearing bit. 0
1 = Packet received since last read.
14 Reserved RO
13:0 CRC good counter RO This is a self-clearing bit. 0x000
contents Counter containing the number of packets
with valid CRCs; this counter does not
saturate and will roll over.
5.3.5 SIGDET Polarity Control

Register 19E controls the SIGDET pin polarity. The following table shows the settings available.
Table 41 • SIGDET Polarity Control, Address 19E (0x13)

15:1 Reserved RO
0 SIGDET pin polarity R/W 1 = Active low. CMODE
0 = Active high.

Configuration
5.3.6 ActiPHY Control

Register 20E controls the device ActiPHY sleep timer, its wake-up timer, the frequency of the CLKOUT
signal, and its link speed downshifting feature. The following table shows the settings available.
Table 42 • Extended PHY Control 3, Address 20E (0x14)

15 Disable carrier R/W 1 = Disable. 0
extension
14:13 ActiPHY sleep timer R/W This is a sticky bit. 01
00 = 1 second.
01 = 2 seconds.
10 = 3 seconds.
11 = 4 seconds.
12:11 ActiPHY wake-up timer R/W This is a sticky bit. 11
00 = 160 ms.
01 = 400 ms.
10 = 800 ms.
11 = 2 seconds.
10:9 Reserved RO
(1)
8 CLKOUT frequency R/W This is a sticky bit. CMODE
1 = 156.25 MHz.
0 = 125 MHz.
7:6 Media mode status RO 00 = No media selected. 00
01 = Copper media selected.
10 = SerDes media selected.
11 = Reserved.
5 Reserved RO
4 Enable link speed auto- R/W This is a sticky bit. CMODE
downshift feature 1 = Enable auto link speed downshift from
1000BASE-T.
3:2 Link speed R/W This is a sticky bit. 01
auto-downshift control 00 = Downshift after 2 failed 1000BASE-T
auto-negotiation attempts.
01 = Downshift after 3 failed 1000BASE-T
1 Link speed RO 0 = No downshift. 0
auto-downshift status 1 = Downshift is required or has occurred.
0 Reserved RO
1. Bit 8 is valid only on PHY_0.

Configuration
5.3.7 EEPROM Interface Status and Control

Register 21E is used to affect control over device function when you have incorporated a startup
EEPROM into your design.
Table 43 • EEPROM Interface Status and Control, Address 21E (0x15)

15 Reserved RO
14 Re-read EEPROM R/W This is a super-sticky bit. 0
after software reset 1 = Contents of EEPROM to be re-read
after software reset.
13 Enable EEPROM R/W This is a self-clearing bit. 0
access 1 = Execute read or write EEPROM
based on the settings of register bit
21E.12.
12 EEPROM read or R/W 1 = Read from EEPROM. 1
write 0 = Write to EEPROM.
11 EEPROM ready RO 1 = EEPROM is ready for read or write. 1
10:0 EEPROM address R/W Sets the address of the EEPROM to 00000000000
which the read or write is to be directed.
5.3.8 EEPROM Data Read/Write

Register 22E in the extended register space enables access to the contents of the external EEPROM in
your design. The following table shows the writes needed to obtain the data from the external device.
Table 44 • EEPROM Read or Write, Address 22E (0x16)

15:8 EEPROM read data RO Eight-bit data read from EEPROM; 0x00
requires setting register 21E, bit 13.
7:0 EEPROM write data R/W Eight-bit data to be written to EEPROM. 0x00
5.3.9 PoE and Miscellaneous Functionality

The register at address 23E controls various aspects of inline powering and the CRC error counter in the
VSC8658.
Table 45 • Extended PHY Control 4, Address 23E (0x17)

15:11 PHY address RO PHY address; latched on reset. CMODE
10 Inline powered device R/W This is a sticky bit. 0
detection 1 = Enabled.
9:8 Inline powered device RO 00 = Searching for devices. 00
detection status 01 = Device found; requires inline power.
10 = Device found; does not require inline
power.
11 = Reserved.

Configuration
Table 45 • Extended PHY Control 4, Address 23E (0x17) (continued)

7:0 CRC error counter RO This is a self-clearing bit. 0x00
CRC error counter for the Ethernet packet
generator. The value saturates at 0xFF and
subsequently clears when read and restarts
count.
Note: Bits 9:8 are only valid if bit 10 is set.
5.3.10 VeriPHY Control 1

Register 24E in the extended register space provides control over the device VeriPHY diagnostics
features. There are three separate VeriPHY control registers. The following table shows the settings
available and describes the readouts you can expect.
Table 46 • VeriPHY Control Register 1, Address 24E (0x18)

15 VeriPHY trigger R/W This is a self-clearing bit. 0
1 = Triggers the VeriPHY algorithm and clears
when VeriPHY has completed. Settings in
registers 24E through 26E become valid after
this bit clears.
14 VeriPHY valid RO 1 = VeriPHY results in registers 24E through 0
26E are valid.
13:8 Pair A (1-2) distance RO Loop length or distance to anomaly for pair A 0x00
(1-2).
7:6 Reserved RO
5:0 Pair B (3-6) distance RO Loop length or distance to anomaly for pair B 0x00
(3-6).
Note: The resolution of the 6-bit length field is 3 meters.

The register at address 25E consists of the second of the three device registers that provide control over
VeriPHY diagnostics features. The following table shows the readouts you can expect.
Table 47 • VeriPHY Control Register 2, Address 25E (0x19)

15:14 Reserved RO
13:8 Pair C (4-5) distance RO Loop length or distance to anomaly for 0x00
pair C (4 and 5)
7:6 Reserved RO
5:0 Pair D (7-8) distance RO Loop length or distance to anomaly for 0x00
pair D (7 and 8)
Note: The resolution of the 6-bit length field is 3 meters.

Configuration

The register at address 26E consists of the third of the three device registers that provide control over
VeriPHY diagnostics features. Specifically, this register provides information about the termination status
(fault condition) for all four link partner pairs. The following table shows the readouts you can expect.
Table 48 • VeriPHY Control Register 3, Address 26E (0x1A)

15:12 Pair A (1 and 2) RO Termination fault for pair A (1 and 2) 0x00
termination status
11:8 Pair B (3 and 6) RO Termination fault for pair B (3 and 4) 0x00
termination status
7:4 Pair C (4 and 5) RO Termination fault for pair C (4 and 5) 0x00
termination status
3:0 Pair D (7 and 8) RO Termination fault for pair D (7 and 8) 0x00
termination status
The following table shows the meanings for the various fault codes.
Table 49 • VeriPHY Control Register 3 Fault Codes
Code Denotes
0000 Correctly terminated pair
0001 Open pair
0010 Shorted pair
0100 Abnormal termination
1000 Cross-pair short to pair A
1001 Cross-pair short to pair B
1010 Cross-pair short to pair C
1011 Cross-pair short to pair D
1100 Abnormal cross-pair coupling with pair A
1101 Abnormal cross-pair coupling with pair B
1110 Abnormal cross-pair coupling with pair C
1111 Abnormal cross-pair coupling with pair D
5.3.13 Reserved Extended Address Space

The bits in the extended register page space at address 27E (0x1B) and 28E (0x1C) are reserved.
5.3.14 Ethernet Packet Generator Control 1

The EPG control register provides access to and control of various aspects of the EPG testing feature.
There are two, separate EPG control registers. The following table shows the setting available in the first
register.
Table 50 • EPG Control Register 1, Address 29E (0x1D)

15 EPG enable R/W 1 = Enable EPG 0
14 EPG run or stop R/W 1 = Run EPG 0

Configuration
Table 50 • EPG Control Register 1, Address 29E (0x1D) (continued)

13 Transmission R/W 1 = Continuous (sends in 10,000-packet 0
duration increments)
0 = Send 30,000,000 packets and stop
12:11 Packet length R/W 00 = 125 bytes 0
01 = 64 bytes
10 = 1518 bytes
11 = 10,000 bytes (Jumbo packet)
10 Inter-packet gap R/W 1 = 8,192 ns 0
0 = 96 ns
9:6 Destination address R/W Lowest nibble of the 6-byte destination 0001
address
5:2 Source address R/W Lowest nibble of the 6-byte destination 0000
address
1 Payload type R/W 1 = Randomly generated payload pattern 0
0 = Fixed based on payload pattern
0 Bad frame check R/W 1 = Generate packets with bad FCS 0
sequence (FCS) 0 = Generate packets with good FCS
generation
The following information applies to the EPG control number 1:

• Do not run the EPG when the VSC8658 device is connected to a live network.
• Bit 29E.13 (Continuous EPG mode control): When enabled, this mode causes the device to send
continuous packets. When disabled, the device continues to send packets only until it reaches the
next 10,000-packet increment mark. It then ceases to send packets.
• The six-byte destination address in bits 9:6 is assigned one of 16 addresses in the range of 0xFF FF
FF FF FF F0 through 0xFF FF FF FF FF FF.
• The six-byte source address in bits 5:2 is assigned one of 16 addresses in the range of 0xFF FF FF
FF FF F0 through 0xFF FF FF FF FF FF.
• If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14 must be cleared
and then set back to 1 for the change to take effect and to restart the EPG.
5.3.15 Ethernet Packet Generator Control 2

The register at address 30E consists of the second of bits that provide access to and control over various
aspects of the EPG testing feature. For information about the first set of EPG control bits, see Table 50,
page 51. The following table shows the settings available.
Table 51 • EPG Control Register 2, Address 30E (0x1E)

15:0 EPG packet payload R/W Data pattern repeated in the payload of 0x00
packets generated by the EPG
Note: If any of bits 15:0 in this register are changed while the EPG is running (bit 14 of register 29E is set to 1),
that bit (29E.14) must first be cleared and then set back to 1 for the change to take effect and to restart
the EPG.
5.4 General-Purpose I/O Registers

Accessing the GPIO page register space is similar to accessing the extended page registers. Set register
31 to 0x0010. This sets all 32 registers to the GPIO page register space.
To restore main register page access, write 0x0000 to register 31.

Configuration
The following table lists the addresses and register names in the GPIO register page space. These
registers are accessible only when the device register 31 is set to 0x0010.
Table 52 • General-Purpose Registers Page Space

0G through 12G Reserved
13G SIGDET vs GPIO control
14G Reserved
15G GPIO input
16G GPIO output
17G GPIO output enable
18G 100BASE-FX control
19G through 30G Reserved
5.4.1 Reserved GPIO Address Space

The bits in registers 0G to 12G, and 14G of the GPIO register page space are reserved.
5.4.2 SIGDET vs GPIO Control

The SIGDET control register configures GPIO pins 7:0 to be either SIGDET pins for each port or to be
GPIO pins. The following table shows the values that can be written.
Table 53 • SIGDET vs GPIO Control, Address 13G (0x0D)

15:14 SIGDET7 control R/W 00 = Normal SIGDET operation 0x00
01, 10 = Reserved
11 = Controlled by MII registers 15G to 17G
01, 10 = Reserved
01, 10 = Reserved
01, 10 = Reserved
01, 10 = Reserved
01, 10 = Reserved
01, 10 = Reserved
01, 10 = Reserved

Configuration
5.4.3 GPIO Input

The input register contains information about the input to the device GPIO pins. Read from this register to
access the data on the device GPIO pins. The following table shows the readout you can expect.
Table 54 • GPIO Input, Address 15G (0x0F)

15:0 GPIO [15:0] input RO Data read from the GPIO pins 0x00
5.4.4 GPIO Output

The output register allows you to access and control the output from the device GPIO pins. The following
table shows the values you can write.
Table 55 • GPIO Output, Address 16G (0x10)

15:0 GPIO [15:0] output R/W Data written to the GPIO pins 0x00
5.4.5 GPIO Pin Configuration

Register 17G in the GPIO register space controls whether a particular GPIO pin functions as an input or
an output. The following table shows the settings available.
Table 56 • GPIO Input/Output Configuration, Address 17G (0x11)

15:0 GPIO [15:0] input or R/W 1 = Pin is configured as an output. 0x00
output enable 0 = Pin is configured as an input.
5.4.6 100BASE-FX Control

The 100BASE-FX control register can configure each PHY within the device to be in 100BASE-FX mode.
The following table shows the values that can be written.
Table 57 • 100BASE-FX Control, Address 18G (0x12)

15 Activate 100BASE-FX R/W 0 = No action 0
1 = Activate 100BASE-FX based on bits
11:0
14:12 Reserved RO 000
11 100BASE-FX on all R/W 0 = No 100BASE-FX on all PHYs 0
PHYs 1 = Configure 100BASE-FX on all PHYs
10:8 Individual 100BASE-FX R/W PHY number to be configured for 000
setting 100BASE-FX mode
7:0 100BASE-FX mode R/W 0x00 = No 100BASE-FX 0x00
0x01 = 100BASE-FX mode
0x02 to 0xFF = Reserved
Example 1 To configure all PHYs to 100BASE-FX mode, first ensure bit 15 = 0, then set bit 11 = 1 and
bits 7:0 = 0x01, and then reset bit 15 = 1.

Configuration
Example 2 To configure an individual PHY to 100BASE-FX mode, first ensure that bit 15 = 0, then set
bits 10:8 to the correct PHY number to be configured for 100BASE-FX, then set bits 7:0 = 0x01, and
finally reset bit 15 = 1. Repeat these steps for each individual PHY.
5.5 CMODE
The information in this section provides a detailed description of the methods you can use to configure
the VSC8658 device using its CMODE pins. It includes descriptions of the registers that work together
with the CMODE pins to control the device function.
There are eight configuration mode (CMODE) pins on the VSC8658 device. For more information about
the physical location of the CMODE pins, see Pin Descriptions, page 72. Each of the CMODE pins maps
to four configuration bits, which means that each pin controls 16 possible settings for the device.
5.5.1 CMODE Pins and Related Functions

The following table lists the pin numbers and device functionality that are controlled by each
configuration bit.
Table 58 • CMODE Configuration Pins and Device Functions
CMODE Pin Bit 3 (MSB) Control Bit 2 Controls Bit 1 Controls Bit 0 (LSB) Controls
7 Reserved Link speed downshift Speed and duplex [1] Speed and duplex [0]
Always set to logic 0
6 MAC auto-negotiation ActiPHY Advertise asymmetric Advertise symmetric
pause pause
5 Media interface [2] SIGDET polarity Clock speed 125 MHz CLKOUT enable
or 156 MHz selection
4 Media interface [1] LED fiber/copper LED blink or pulse LED blink or pulse
combine stretch [1] stretch [0]
3 Media interface [0] LED3 combine or LED3 [1] LED3 [0]
separate
2 PHY address reversal LED2 combine or LED2 [1] LED2 [0]
separate
1 PHY address [4] LED1 combine or LED1 [1] LED1 [0]
separate
0 PHY address [3] LED0 combine or LED0 [1] LED0 [0]
separate
5.5.2 Functions and Related CMODE Pins

The following table lists the pin and bit settings according to the device function and CMODE pin used to
configure them.
Table 59 • Device Functions and Associated CMODE Pins
Sets MII CMODE

Function Register Pin Bit Description
Link speed Register 20E, 7 2 0 = Link only according to the auto-negotiation resolution.
downshift bit 4 1 = Enable link speed downshift feature.
Speed and duplex Register 4, 7 1 and 0 00 = 10/100/1000BASE-T FDX/HDX. 1000BASE-X
bits 8:5 and FDX/HDX.
register 9, 01 = 10/100/1000BASE-T FDX; 10/100BASE-T HDX.
bits 9:8 1000BASE-X FDX.
10 = 1000BASE-T FDX only.
11 = 10/100BASE-T FDX/HDX.

Configuration
Table 59 • Device Functions and Associated CMODE Pins (continued)
Sets MII CMODE

MAC Register 23, 6 3 0 = Disabled.
auto-negotiation bit 13 1 = Enabled.
ActiPHY Register 28, 6 2 0 = Disabled.
bit 6 1 = Enabled.
Advertise Register 4, 6 1 0 = Not advertised.
asymmetric pause bit 11 1 = Advertised.
Advertise symmetric Register 4, 6 0 0 = Not advertised.
pause bit 10 1 = Advertised.
Media interface [2:0] Register 23, 5, 4, 3 3 000 = Cat5 copper only.
bits 10:8 001 = SerDes Fiber/SFP Pass-Through mode only. No
auto-negotiation performed in the PHY.
010 = 1000BASE-X Fiber/SFP mode only with auto-
negotiation performed by the PHY.
011 = 100BASE-X Fiber/SFP mode on the fiber media pins
only.
101 = Auto-media sense with Cat5 media or SerDes
Fiber/SFP Pass-Through mode.
110 = Auto-media sense with Cat5 media or 1000BASE-X
Fiber/SFP mode with auto-negotiation performed by PHY.
111 = Auto-media sense with Cat5 media or 100BASE-FX
Fiber/SFP mode.
100 = Reserved.
SIGDET polarity Register 19E, 5 2 0 = Active high.
bit 0 1 = Active low.
Clock speed Register 20E, 5 1 0 = 125 MHz.
bit 8 1 = 156.2 MHz.
CLKOUT enable Register 18, 5 0 0 = Disabled.
bit 0 1 = Enabled.
LED fiber/copper Register 30, 4 2 0 = Combine enabled (Copper/Fiber on
combine bit 15 Link/LinkXXXX/Activity LED).
1 = Disable combination (Link/LinkXXXX/Activity LED
indicates copper only).
LED blink/pulse Register 30, 4 1 and 0 00 = 2.5 Hz blink rate, 400 ms pulse stretch.
stretch rate bits 11:10 01 = 5.0 Hz blink rate, 200 ms pulse stretch.
10 = 10.0 Hz blink rate, 100 ms pulse stretch.
11 = 20.0 Hz blink rate, 50 ms pulse stretch.
LED_3, LED_2, Register 30, 3, 2, 1, 2 0 = Link, Link10, Link100, Link1000, Link10/100,
LED_1, and LED_0 bits 3:0 and 0 Link10/1000, Link100/1000.
combine or separate LEDs blink or flash when activity is present.
Also, a duplex LED blinks or flashes when collision is
present.
1 = Link, Link10, Link100, Link1000, Link10/100,
Link10/1000, Link100/1000.
LEDs indicate status only.
Also, a duplex LED indicates a duplex status only.
LED_3 indication Register 29, 3 1 and 0 00 = Duplex or collision.
function bits 15:12 01 = Link100 or activity.
10 = Activity.
11 = Fiber_Link/Fiber_Activity.

Configuration
Table 59 • Device Functions and Associated CMODE Pins (continued)
Sets MII CMODE

Address reversal 2 3 0 = Normal functioning.
PHY address 0:7 = Port 0:7.
1 = Reversed functioning.
PHY address 7:0 = Port 0:7.
LED_2 indication Register 29, 2 1 and 0 00 = Link or activity.
function bits 11:8 01 = Duplex or collision.
10 = Fiber_Activity.
11 = Link10 or activity.
PHY address [4:3] 1 and 0 3 Sets the two MSBs of the PHY address.
LED_1 indication Register 29, 1 1 and 0 00 = Link100 or activity.
function bits 7:4 01 = Link100/1000 or activity.
10 = Link 10/100 or activity.
11 = Fiber_Link/Fiber_Activity.
LED_0 indication Register 29, 0 1 and 0 00 = Link1000 or activity.
function bits 3:0 01 = Link100/1000 or activity.
10 = Activity.
11 = Link or activity.
Note: The MAC auto-negotiation, LED_0, LED_1, LED_2, and LED_3 settings available using the CMODE
pins and configuration bits is limited. For full functionality, use the registers. For more information about
using the registers for these and other functions, see Registers, page 26.
5.5.3 CMODE Resistor Values

To affect an aspect of the VSC8658 device configuration, find the parameter in Table 58, page 55 or in
Table 59, page 55, and connect the associated pin to the resistor specified in the following table. This
sets the bits as shown.
Table 60 • CMODE Resistor Values and Resultant Bit Settings
With CMODE With 1% Set Set Set Set

Pin Tied To Resistor Value Bit 3 (MSB) to: Bit 2 to: Bit 1 to: Bit 0 (LSB) to:
VSS 0 0 0 0 0
VSS 2.26 kΩ 0 0 0 1
VSS 4.02 kΩ 0 0 1 0
VSS 5.90 kΩ 0 0 1 1
VSS 8.25 kΩ 0 1 0 0
VSS 12.1 kΩ 0 1 0 1
VSS 16.9 kΩ 0 1 1 0
VSS 22.6 kΩ 0 1 1 1
VDD33 0 1 0 0 0
VDD33 2.26 kΩ 1 0 0 1
VDD33 4.02 kΩ 1 0 1 0
VDD33 5.90 kΩ 1 0 1 1
VDD33 8.25 kΩ 1 1 0 0
VDD33 12.1 kΩ 1 1 0 1

Configuration
Table 60 • CMODE Resistor Values and Resultant Bit Settings (continued)
With CMODE With 1% Set Set Set Set

Pin Tied To Resistor Value Bit 3 (MSB) to: Bit 2 to: Bit 1 to: Bit 0 (LSB) to:
VDD33 16.9 kΩ 1 1 1 0
VDD33 22.6 kΩ 1 1 1 1
Using resistors with the CMODE pins can be optional in designs that access the device’s MDC/MDIO
pins. In designs that do this, all configurations otherwise affected on the device by using the CMODE
pins can be changed using the regular device register settings, and all the CMODE pins can be pulled to
VSS (ground). However, in this case, the PHYADDR [4:3] and the PHYADD_REVERSAL settings still
require CMODE configuration. This configuration can be set by connecting these pins to either the
VDD33 or VSS pins.
5.6 EEPROM
The VSC8658 device EEPROM interface makes it possible for you to set up the device to self-configure
its internal registers based on the information programmed into and stored in an external device. To
accomplish this, the EEPROM is read on power-up or de-assertion of the NRESET bit. For field
configurability, the EEPROM can also be accessed using VSC8658 device registers 21E and 22E.
The EEPROM you use to interface to the VSC8658 device must have a two-wire interface. A device such
as the Atmel part AT24CXXX is suggested.
As defined by the interface, data is clocked from the VSC8658 device on the falling edge of EECLK. The
device determines that an external EEPROM is present if EEDAT is connected to a 4.7-kΩ external pull-
up resistor. The EEDAT pin can be left floating or grounded to indicate that no EEPROM is present.
5.6.1 EEPROM Contents Description

When an EEPROM is present, the VSC8658 device looks for the command header, 0xBDBD at address
0 and 1 of the EEPROM. The address is incremented by 256 until the header is found. If the header is
not found or no EEPROM is connected, the VSC8658 device bypasses the EEPROM read step.
When an EEPROM is present, the VSC8658 device waits for an acknowledgement for approximately
three seconds (in accordance with the ATMEL EEPROM protocol). If there is no acknowledgement for
three seconds, the VSC8658 device aborts its attempt to connect to the EEPROM and reverts to its
otherwise normal operating mode.
After the header value is found, the two-byte address value shown in the following table indicates the
EEPROM word address where the configuration contents for the device are located. At the base address
location, the next set of bytes indicates where the configuration data contents to be programmed into the
VSC8658 device are located. The first address points to the data common to all PHYs. Each subsequent
address location points to each individual PHY’s configuration contents. At each programming location,
the two bytes represent the total number of bytes (11 bits, with MSB first) where the
Total_Number_Bytes[10:0] is equal to the number of SMI writes multiplied by 3 (one byte for SMI port
and register address and two bytes for data). Data is read from the EEPROM sequentially until all SMI
write commands are completed.
Table 61 • EEPROM Configuration Contents
10-bit Address Content (Bits 7:0)

0 0xBD
1 0xBD
2 PHY_ADDR[4:2], 00, Base_Address_Location[10:8]
3 Base_Address_Location[7:0] (K)
Address length not specified
K 00000, Common_Config_Base_Address[10:8]

Configuration
Table 61 • EEPROM Configuration Contents (continued)
10-bit Address Content (Bits 7:0)

K+1 Common_Config_Base_Address[7:0] (X)
K+2 00000, PHY0_Specific_Config_Base_Address[10:8]
K+3 PHY0_Specific_Config_Base_Address[7:0] (Y)
K+5 PHY1_Specific_Config_Base_Address[7:0]
X 00000, Total_Number_Bytes[10:8]
X+1 Total_Number_Bytes [7:0] (M)
X+2 Register address a
X+3 Data[15:8] to be written to register address a
X+4 Data[7:0] to be written to register address a
X+5 Register address b
X+6 Data[15:8] to be written to register Address b
X+7 Data[7:0] to be written to register address b
X+(M-2) Register address x
X+(M-1) Data[15:8] to be written to register address x
X+M Data[7:0] to be written to register address x
Y 00000, Total_Number_Bytes[10:8]
Y+1 Total_Number_Bytes [7:0] (N)
Y+2 Register address a
Y+3 Data[15:8] to be written to register address a
Y+4 Data[7:0] to be written to register address a
Y+(N-2) Register address x
Y+(N-1) Data[15:8] to be written to register address x
Y+N Data[7:0] to be written to register address x
Max Address
5.6.2 Read/Write Access to the EEPROM

The VSC8658 device also has the ability to read from and write to an EEPROM such as an ATMEL
AT24CXXX that is directly connected to its EECLK and EEDAT pins. If it is required to be able to write to

Configuration
the EEPROM, refer to the EEPROM’s specific datasheet to ensure that write protection on the EEPROM
is not set.
The following illustration shows the interaction of the VSC8658 device and the EEPROM.
Figure 18 • EEPROM Read and Write Register Flow
Start
21E.11 = 0
Wait for Ready
Read Data = 22E.15:8

21E.11 = 1
Write EEPROM 21E.11 = 1
Data
Read or Write
21E.13 = 1
Wait for Ready
Read EEPROM
Data
21E.11 = 0
21E.10:0 = Write Address
21E.12 = 0
21E.10:0 = Address to Read
22E.7:0 = Data to Write 21E.13 = 1
21E.12 = 1
To read a value from a specific address of the EEPROM:

1. Read the VSC8658 device register bit 21E.11, and ensure that it is set.
2. Write the EEPROM address to be read to register bits 21E.10:0.
3. Set both register bits 21E.12 and 21E.13 to 1.
4. When register bit 21E.11 changes to 1, read the 8-bit data value found at register bits 22E.15:8. This
is the contents of the address just read by the PHY.
To write a value to a specific address of the EEPROM:
1. Read the VSC8658 device register bit 21E.11 and ensure that it is set.
2. Write the address to be written to register bits 21E.10:0.
3. Set register bit 21E.12 to 0.
4. Set register bits 22E.7:0 with the 8-bit value to be written to the EEPROM.
5. Set register bit 21E.13 to 1.
To avoid collisions during read and write transactions, always wait until register bit 21E.11 changes to 1
before performing another EEPROM read or write operation.

Electrical Specifications
6 Electrical Specifications
This section provides the DC characteristics, AC characteristics, recommended operating conditions,

and stress ratings for the VSC8658 device. It includes information on the various timing functions of the
device.
6.1 DC Characteristics
In addition to any parameter-specific conditions, the specifications listed in the following tables may be
considered valid only in the environment characterized by the specifications listed as recommended
operating conditions for the VSC8658 device. For more information about the recommended operating
conditions, see Operating Conditions, page 70.
6.1.1 VDDIO at 3.3 V

In addition to any parameter-specific conditions, the specifications listed in the following table may be
considered valid only when:
• VDDIO is 3.3 V
• VDD33 is 3.3 V
• VDD12 is 1.2 V
• VDD12A is 1.2 V
Table 62 • DC Characteristics for Pins Referenced to VDDIO at 3.3 V
Parameter Symbol Minimum Maximum Unit Condition

Output high voltage VOH 2.4 3.6 V IOH = –4 mA
Output low voltage VOL 0 0.5 V IOL = 4 mA
Input high voltage VIH 2.1 3.6 V
Input low voltage VIL –0.3 0.9 V
Input leakage current IILEAK –42 42 µA Internal resistor included
Output leakage IOLEAK –42 42 µA Internal resistor included
current
Output low current IOL 8 mA
drive strength
Output high current IOH –8 mA
drive strength

• VDDIO is 2.5 V
• VDD33 is 3.3 V
• VDD12 is 1.2 V
• VDD12A is 1.2 V

Output high voltage VOH 2.0 2.8 V IOH = –1.0 mA
Output low voltage VOL –0.3 0.4 V IOL = 1.0 mA

Table 63 • DC Characteristics for Pins Referenced to VDDIO at 2.5 V (continued)

Output leakage current IOLEAK –32 32 µA Internal resistor included
drive strength
drive strength

• VDDIO is 1.8 V
• VDD33 is 3.3 V
• VDD12 is 1.2 V
• VDD12A is 1.2 V

Output low voltage VOL 0.3 V IOL = 0.5 mA
Input low voltage VIL 0.6 V
Output leakage IOLEAK –23 23 µA Internal resistor included
current
Output low current IOL 4.0 mA
drive strength
Output high current IOH –4.0 mA
drive strength
6.1.4 VDD at 3.3 V

• VDDIO is 3.3 V
• VDD33 is 3.3 V
• VDD12 is 1.2 V
• VDD12A is 1.2 V
Table 65 • DC Characteristics for Pins Referenced to VDD33 at 3.30 V

Output high voltage VOH 2.4 3.6 V IOH = –4 mA
Output low voltage VOL 0 0.5 V IOL = 4 mA

Table 65 • DC Characteristics for Pins Referenced to VDD33 at 3.30 V (continued)

drive strength
drive strength
6.1.5 MAC and SerDes Outputs

For more information about the number and physical location of the MAC and SerDes output pins on the
VSC8658 device, see Pin Descriptions, page 72.
Table 66 • DC Characteristics for MAC_RDP/N_n and SER_DOP/N_n Pins
Parameter Symbol Minimum Typical Maximum Unit Condition

Frequency lock time TLOCK 500 µs
Output differential VODIFF 700 1000 1200 mV Measured peak-to-
voltage peak. Based on
100 Ω differential
load.
Output common- VOCM 480 540 610 mV VDD12A = 1.20 V.
mode voltage
Output rise time and tr , tf 300 ps
fall time (20% to
80%)
Total jitter TJ 185 260 ps Measured peak-to-
peak. Uses K28.5
test pattern. Bit error
rate (BER) = 10–12.
drive strength
drive strength
Output driver ZO 50 Ω
impedance per pin
6.1.6 MAC and SerDes Inputs

For more information about the number and physical location of the MAC and SerDes input pins on the
VSC8658 device, see Pin Descriptions, page 72.
Table 67 • DC Characteristics for MAC_TDP/N_n and SER_DIP/N_n Pins

Input differential voltage VIDIFF 120 2400 mV Measured peak-to-peak.
Based on 100 Ω
differential load.

Table 67 • DC Characteristics for MAC_TDP/N_n and SER_DIP/N_n Pins (continued)

Input common mode VICM 0.4 1.3 V VDD12A = 1.20 V.
voltage
Total receive jitter JRXTotal 450 550 ps Measured peak-to-peak.
tolerance 1000BASE-X mode.
JRXTotal 5870 6500 ps Measured peak-to-peak.
100BASE-FX mode.
6.1.7 LED Pins

• VDDIO is 3.30 V
• VDD33 is 3.30 V
• VDD12 is 1.20 V
• VDD12A is 1.20 V
Table 68 • DC Characteristics for LED[3:0]_n Pins

Output low voltage VOL 0 0.5 V IOL = 4.0 mA
Output leakage current IOLEAK –10 10 µA
Output low current drive strength IOL 8.0 mA
Output high current drive strength IOH –8.0 mA
6.1.8 JTAG Pins

• VDDIO is 3.30 V
• VDD33 is 3.30 V
• VDD12 is 1.20 V
• VDD12A is 1.20 V
Table 69 • DC Characteristics for JTAG Pins

Output low voltage VOL 0 0.5 V IOL = 1.5 mA
Output low current drive IOL 8 mA
strength
drive strength

6.2 Current Consumption

There are three sets of current consumption values:
• Typical current consumption
• Current consumption in SerDes/SGMII to 1000BASE-X mode
• Current consumption in SerDes/SGMII to 100BASE-FX mode or SerDes pass-through mode
The typical current consumption values are based on nominal voltages with all ports operating at
1000BASE-T speeds with full-duplex enabled and a 64-bit random data pattern at 100% utilization.
Table 70 • Typical Current Consumption
Parameter Symbol Typical Maximum Unit

Worst-case power consumption PD 5.91 W
Current with VDDIO at 1.8 V IVDDIO 1 mA
Current with VDD33 at 3.3 V IVDD33 852 mA
Current with VDD12 at 1.2 V IVDD12 1488 mA
Current with VDD12A at 1.2 V IVDD12A 490 mA
If all eight ports are running in SerDes/SGMII to 1000BASE-X mode, the current consumption values are
shown in the following table.
Table 71 • Current Consumption in SerDes/SGMII to 1000BASE-X Mode

Current with VDD33 at 3.3 V IVDD33 68.6 mA
Current with VDD12 at 1.2 V IVDD12 134.2 mA
Current with VDD12A at 1.2V IVDD12A 448.6 mA
If all eight ports are running in SerDes/SGMII to 100BASE-FX mode or SerDes pass-through mode, the
current consumption values are as shown in the following table.
Table 72 • Consumption in SerDes/SGMII to 100BASE-FX or SerDes Pass-Through Mode

Current with VDD33 IVDD33 64 mA
Current with VDD12 IVDD12 146 mA
Current with VDD12A IVDD12A 444 mA

6.3 AC Characteristics
The AC specifications are grouped according to specific device pins and associated timing
characteristics.
6.3.1 Reference Clock Input

The following table shows the specifications for the reference clock input frequency including various
frequencies, duty cycle, and accuracy.
Table 73 • AC Characteristics for REFCLK Input
Parameter Symbol Minimum Typical Maximum Unit

Frequency with 25 MHz input fCLK25 25 MHz
Frequency with 125 MHz input fCLK125 125 MHz
Frequency accuracy fTOL 100 ppm
Duty cycle %DUTY 40 60 %
Rise time with 25 MHz input (20% to 80%) tR25 4 ns
Rise time with 125 MHz input (20% to 80%) tR125 1 ns
Fall time with 25 MHz input (20% to 80%) tR25 4 ns
Fall time with 125 MHz input (20% to 80%) tF125 1 ns
If using the 25 MHz crystal clock input option, the additional specifications in the following table are
required.
Table 74 • AC Characteristics for REFCLK Input with 25 MHz Clock Input
Parameter Minimum Typical Maximum Unit

Crystal parallel load capacitance 18 20 pF
Crystal equivalent series resistance 10 30 Ω
Crystal accuracy 50 ppm
6.3.2 Clock Output

The specifications in the following table show the AC characteristics for the clock output of the VSC8658
device when used in your design.
Table 75 • AC Characteristics for the CLKOUT Pin

CLKOUT frequency fCLK125 125.00 MHz 125 MHz output clock
156.25 156.25 MHz output clock
CLKOUT cycle time tCYC 8.0 ns 125 MHz output clock
6.4 156.25 MHz output clock
Frequency stability fSTABILITY 100 ppm
Duty cycle %DUTY 40 50 60 %
Clock rise and fall times tR and tF 1 ns
(20% to 80%)
Total jitter JCLK 217 491 ps Measured peak-to-peak

6.3.3 JTAG Interface

The following table lists the characteristics for the JTAG testing feature. The illustration provides a
diagram of the timing.
Table 76 • AC Characteristics for the JTAG Interface
Parameter Symbol Minimum Maximum Unit

TCK frequency fCLK 10 MHz
TCK cycle time tCYC 100 ns
TCK time high tWH 45 ns
TCK time low tWL 45 ns
Setup time to TCK rising tSU 10 ns
Hold time from TCK rising tH 10 ns
TCK to TDO valid tCO 15 ns
Figure 19 • JTAG Interface Timing

tCYC
TCK
tWH tWL
tSU tH
TDI
TMS
TDO
tCO
6.3.4 SMI Interface

Use the information in the following table when incorporating the VSC8658 device SMI interface into your
own design. The illustration provides information about SMI interface timing.
Table 77 • AC Characteristics for the SMI Interface

(1)
MDC frequency fCLK 2.5 12.5 MHz
MDC cycle time tCYC 80 400 ns
MDC time high tWH 20 50 ns
MDC time low tWL 20 50 ns
Setup to MDC rising tSU 10 ns
Hold from MDC tH 10 ns
rising
MDC rise time tR 100 ns For MDC = 0 – 1 MHz
tCYC × 10%(1) For MDC = 1 MHz – fCLK(MAX)

Table 77 • AC Characteristics for the SMI Interface (continued)

MDC fall time tF 100
tCYC × 10%(1)
MDC to MDIO valid tCO 10 300 ns Time-dependant on the value of
the external pull-up resistor on
the MDIO pin
1. For fCLK above 1 MHz, the minimum rise time and fall time is in relation to the frequency of the MDC clock period. For example,
if fCLK is 2 MHz, the minimum clock rise time and fall time is 50 ns.
Figure 20 • SMI Interface Timing

tWL tWH
MDC
tCYC
tSU tH
MDIO Data
(write)
tCO
MDIO
Data
(read)
6.3.5 Device Reset

The following specifications apply to the device reset functionality. The illustration shows the reset timing.
Table 78 • AC Characteristics for Device Reset

NRESET assertion time tRESET 100 ns
Wait time between tWAIT 20 ms Register 21E.14 = 0
NRESET de-assert and 220 ms Register 21E.14 = 1
access of the SMI
interface
Soft reset (pin) assertion tSRESET_ASSERT 4 ms
Soft reset (pin) de- tSRESET_DEASSERT 4 ms
assertion
Wait time between soft tSWAIT 4 µs Registers 22.9 = 1, 21E.14 = 0
reset pin de-assert and 300 µs Registers 22.9 = 0, 21E.14 = 0
access of the SMI 200 ms Registers 22.9 = 0, 21E.14 = 1
interface 200 ms Registers 22.9 = 1, 21E.14 = 1
Soft reset MII register 0.15 tSREG_RESET 100 ns
assertion

Table 78 • AC Characteristics for Device Reset (continued)

Wait time between Soft tSREG_WAIT 4 µs Registers 22.9 = 1, 21E.14 = 0
Reset (MII Register 0.15) 300 µs Registers 22.9 = 0, 21E.14 = 0
de-assert and access to 200 ms Registers 22.9 = 0, 21E.14 = 1
the SMI interface 200 ms Registers 22.9 = 1, 21E.14 = 1
Figure 21 • Reset Timing
REFCLK
tWAIT
tRESET
NRESET
tSWAIT
tSRESET_ASSERT tSRESET_DEASSERT
NSRESET
tSREG_WAIT
tSREG_RESET
Soft Reset
(MII Register 0.15)
Undefined State
MDC
MDIO
6.3.6 Serial LEDs

The following table provides specifications for the device serial LEDs. The illustration shows the LED
timing.
Table 79 • AC Characteristics for Serial LEDs

LED_CLK cycle time tCYC 1 µs
Pause between LED bit sequences tPAUSE 25 ms
LED_CLK to LED_DATA tCO 1 ns

Figure 22 • Serial LED Timing
tCYC tPAUSE
LED_CLK
tCO
LED_DATA Bit 1 Bit 2 Bit 96 Bit 1
6.4 Operating Conditions

The following table shows the recommended operating conditions for the VSC8658 device.
Table 80 • Recommended Operating Conditions
Parameter Symbol Minimum Typical Maximum Unit

Power supply voltage for VDDIO at 1.8 V VDDIO 1.70 1.80 1.90 V
Power supply voltage for VDD33 VDD33 3.13 3.30 3.47 V
Power supply voltage for VDD12 VDD12 1.14 1.20 1.26 V
Power supply voltage for VDD12A VDD12A 1.14 1.20 1.26 V
Operating temperature(1) T 0 90 °C
1. Lower limit of specification is ambient temperature, and upper limit is case temperature.
6.5 Stress Ratings

This section contains the stress ratings for the VSC8658 device.
Warning Stresses listed in the following table may be applied to devices one at a time without causing
permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these
values for extended periods may affect device reliability.
Table 81 • Stress Ratings

DC input voltage on VDDIO supply pin VDDIO –0.5 4.0 V
DC input voltage on VDD33 supply pin VDD33 –0.5 4.0 V
DC input voltage on VDD12 supply pin VDD12 –0.5 1.4 V
DC input voltage on VDD12A supply pin VDD12A –0.5 1.4 V
DC input voltage on JTAG 5 V-tolerant pins VDD(5 V) –0.5 5.5 V
DC input voltage on any non-supply pin VDD(PIN) –0.5 VDD + 0.5 V
Storage temperature TS –65 150 oC
Electrostatic discharge voltage, charged device VESD_CDM –250 250 V

model
Electrostatic discharge voltage, human body model VESD_HBM See note(1) V

1. This device has completed all required testing as specified in the JEDEC standard JESD22-A114,
Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), and complies with a Class 2
rating. The definition of Class 2 is any part that passes an ESD pulse of 2000 V, but fails an ESD pulse of
4000 V.
Warning This device can be damaged by electrostatic discharge (ESD) voltage. Microsemi
recommends that all integrated circuits be handled with appropriate precautions. Failure to observe
proper handling and installation procedures may adversely affect reliability of the device.

Pin Descriptions
7 Pin Descriptions
The VSC8658 device has 444 pins, which are described in this section.
7.1 Pin Diagram

The following illustrations show the pin diagram for the VSC8658 device. For clarity, the device is shown
in two halves in Figure 23, page 72 and Figure 24, page 73.
Figure 23 • Pin Diagram, Left Side, Top View
1 2 3 4 5 6 7 8 9 10 11 12 13
A VSS TXVPB_6 TXVPC_6 TXVPD_6 TXVPA_5 TXVPB_5 TXVPC_5 TXVPD_5 TXVPA_4 TXVPB_4 TXVPC_4 TXVPD_4
B VSS VSS TXVNB_6 TXVNC_6 TXVND_6 TXVNA_5 TXVNB_5 TXVNC_5 TXVND_5 TXVNA_4 TXVNB_4 TXVNC_4 TXVND_4
C TXVPA_6 TXVNA_6 VDD33 VDD33 VSS NC VDD12A VSS VSS VDD33 VDD33 VDD33 VDD12A
D TXVPD_7 TXVND_7 VDD33 VDD33 VSS VDD12A VDD12A VSS VSS VDD33 VDD33 VDD33 VDD12A
E TXVPC_7 TXVNC_7 VDD12A VDD12A
F TXVPB_7 TXVNB_7 VSS REF_REXT_B
G TXVPA_7 TXVNA_7 NC REF_FILT_B
H VSS VSS VSS VSS
J XTAL1/REFCLK XTAL2 LED3_7 LED2_7
K VSS VSS LED1_7 LED0_7 VDD12 VSS VSS VSS VSS VSS
L LED3_6 LED2_6 LED3_5 LED2_5 VDD12 VSS VSS VSS VSS VSS
M LED1_6 LED0_6 LED1_5 LED0_5 VDD12 VSS VSS VSS VSS VSS
N VDD33 VDD33 VDD33 VDD33 VDD12 VSS VSS VSS VSS VSS
P EECLK EEDAT LED3_4 LED2_4 VDD12 VSS VSS VSS VSS VSS
R PLLM ODE OSCEN LED1_4 LED0_4 VDD12 VSS VSS VSS VSS VSS
T TM S TCK NTRST TDO VDD12 VSS VSS VSS VSS VSS
U TDI VDDIO M DC VDD33 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12
V CLKOUT VDDIO M DIO VSS
W M DINT_0 M DINT_1 M DINT_2 M DINT_3
Y M DINT_4 M DINT_5 M DINT_6 M DINT_7
AA SER_DON_7 SER_DOP_7 NRESET VSS
AB SER_DIN_7 SER_DIP_7 VSS VDDIO
AC MAC_RDN_7 MAC_RDP_7 VSS VDD12A VDD12A VSS VDD12A VDD12A VSS VSS VDD12A VDD12A VDD12A
AD MAC_TDN_7 MAC_TDP_7 VDD33 VSS VDD33 VSS VDD33 VDD12A VSS VSS VDD33 VDD33 VSS
AE VSS SER_DoP_6 SER_DIP_6 MAC_RDP_6 MAC_TDP_6 SER_DoP_5 SER_DiP_5 MAC_RDP_5 MAC_TDP_5 SER_DoP_4 SER_DiP_4 MAC_RDP_4 MAC_TDP_4
AF SER_DoN_6 SER_DIN_6 MAC_RDN_6 MAC_TDN_6 SER_DoN_5 SER_DiN_5 MAC_RDN_5 MAC_TDN_5 SER_ DoN_4 SER_DiN_4 MAC_RDN_4 MAC_TDN_4
1 2 3 4 5 6 7 8 9 10 11 12 13

Pin Descriptions
Figure 24 • Pin Diagram, Right Side, Top View

14 15 16 17 18 19 20 21 22 23 24 25 26
TXVPA_3 TXVPB_3 TXVPC_3 TXVPD_3 TXVPA_2 TXVPB_2 TXVPC_2 TXVPD_2 TXVPA_1 TXVPB_1 TXVPC_1 TXVPD_1 A
TXVNA_3 TXVNB_3 TXVNC_3 TXVND_3 TXVNA_2 TXVNB_2 TXVNC_2 TXVND_2 TXVNA_1 TXVNB_1 TXVNC_1 TXVND_1 VSS B
VSS VSS VDD33 VDD33 VSS VDD12A VDD12A VDD33 NC VDD33 VSS VDD33 VSS C
VSS VSS VDD33 VDD33 VSS VDD12A VDD12A VDD33 VDD33 VDD12A VSS TXVNA_0 TXVPA_0 D
REF_FILT_A VDD12A TXVNB_0 TXVPB_0 E
REF_REXT_A VDD33 TXVNC_0 TXVPC_0 F
VDD33 NC TXVND_0 TXVPD_0 G
VDD33 VDD33 CM ODE7 VSS H
VDD33 CM ODE6 CM ODE5 CM ODE4 J
VSS VSS VSS VSS VSS VDD12 VSS CM ODE3 CM ODE2 CM ODE1 K
VSS VSS VSS VSS VSS VDD12 VSS CM ODE0 LED1_0 LED0_0 L
VSS VSS VSS VSS VSS VDD12 VDD33 VDD33 LED3_0 LED2_0 M
VSS VSS VSS VSS VSS VDD12 LED1_2 LED0_2 LED1_1 LED0_1 N
VSS VSS VSS VSS VSS VDD12 LED3_2 LED2_2 LED3_1 LED2_1 P
VSS VSS VSS VSS VSS VDD12 LED1_3 LED0_3 VDD33 VDD33 R
VSS VSS VSS VSS VSS VDD12 LED3_3 LED2_3 GPIO14 GPIO15 T
VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 GPIO10 GPIO11 GPIO12 GPIO13 U
GPIO6 / SIGDE T_ 6 GPIO7 / SIGDE T_ 7 GPIO8 GPIO9 V
GPIO2 / SIGDE T_ 2 GPIO3 / SIGDE T_ 3 GPIO4 / SIGDE T_ 4 GPIO5 / SIGDE T_ 5 W
GPIO0 / SIGDE T_ 0 GPIO1 / SIGDE T_ 1 VSS VSS Y
VDD33 VSS MAC_TDP _0 MAC_TDN_0 AA
VDD33 VDD12A MAC_RDP_0 MAC_RDN_0 AB
VSS VDD12A VDD12A VSS VDD12A VDD12A VDD12A VSS VSS VSS VDD12A SER_DIP_0 SER_DIN_0 AC
VDD33 VSS VSS VDD33 VSS VDD12A VDD33 VDD33 VSS VSS VSS SER_DOP_0 SER_DON_0 AD
SER_DOP_3 SER_DIP_3 MAC_RDP_3 MAC_TDP_3 SER_DOP_2 SER_DIP_2 MAC_RDP_2 MAC_TDP_2 SER_DOP_1 SER_DIP_1 MAC_RDP_1 MAC_TDP_1 VSS AE
SER_DON_3 SER_DIN_3 MAC_RDN_3 MAC_TDN_3 SER_DON_2 SER_DIN_2 MAC_RDN_2 MAC_TDN_2 SER_DON_1 SER_DIN_1 MAC_RDN_1 MAC_TDN_1 AF
14 15 16 17 18 19 20 21 22 23 24 25 26
7.2 Pin Identifications

This section contains the functional pin descriptions for the VSC8658 device.

Pin Descriptions
7.2.1 SerDes MAC Interface

The following table shows the pins associated with the device SerDes MAC interface.
Table 82 • SerDes MAC Interface Pins
Pin Name Type Description

AD2 MAC_TDP_7 IDIFF SerDes MAC transmitter input pair.
AE5 MAC_TDP_6
AE9 MAC_TDP_5
AE13 MAC_TDP_4
AE17 MAC_TDP_3
AE21 MAC_TDP_2
AE25 MAC_TDP_1
AA25 MAC_TDP_0
AD1 MAC_TDN_7
AF5 MAC_TDN_6
AF9 MAC_TDN_5
AF13 MAC_TDN_4
AF17 MAC_TDN_3
AF21 MAC_TDN_2
AF25 MAC_TDN_1
AA26 MAC_TDN_0
AC2 MAC_RDP_7 ODIFF SerDes MAC receiver output pair.
AE4 MAC_RDP_6
AE8 MAC_RDP_5
AE12 MAC_RDP_4
AE16 MAC_RDP_3
AE20 MAC_RDP_2
AE24 MAC_RDP_1
AB25 MAC_RDP_0
AC1 MAC_RDN_7
AF4 MAC_RDN_6
AF8 MAC_RDN_5
AF12 MAC_RDN_4
AF16 MAC_RDN_3
AF20 MAC_RDN_2
AF24 MAC_RDN_1
AB26 MAC_RDN_0
7.2.2 SerDes Media Interface

The following table shows the pins associated with the device SerDes media interface.
Table 83 • SerDes Media Interface Pins
Pin Signal Name Type Description

Pin Descriptions
Table 83 • SerDes Media Interface Pins (continued)
AA2 SER_DOP_7 ODIFF SerDes media transmitter output pair.

AE2 SER_DOP_6
AE6 SER_DOP_5
AE10 SER_DOP_4
AE14 SER_DOP_3
AE18 SER_DOP_2
AE22 SER_DOP_1
AD25 SER_DOP_0
AA1 SER_DON_7
AF2 SER_DON_6
AF6 SER_DON_5
AF10 SER_DON_4
AF14 SER_DON_3
AF18 SER_DON_2
AF22 SER_DON_1
AD26 SER_DON_0
AB2 SER_DIP_7 IDIFF SerDes media receiver input pair.
AE3 SER_DIP_6
AE7 SER_DIP_5
AE11 SER_DIP_4
AE15 SER_DIP_3
AE19 SER_DIP_2
AE23 SER_DIP_1
AC25 SER_DIP_0
AB1 SER_DIN_7
AF3 SER_DIN_6
AF7 SER_DIN_5
AF11 SER_DIN_4
AF15 SER_DIN_3
AF19 SER_DIN_2
AF23 SER_DIN_1
AC26 SER_DIN_0
7.2.3 GPIO and SIGDET

The following table shows the pins associated with the device GPIO and SIGDET.
Table 84 • GPIO and SIGDET Pins

T26 GPIO15 IPD/O General purpose input/output (GPIO). Eight
T25 GPIO14 dedicated GPIO pins are provided. Additionally, the
U26 GPIO13 eight SIGDET pins can be configured to become
U25 GPIO12 GPIO pins if not used.
U24 GPIO11
U23 GPIO10
V26 GPIO9
V25 GPIO8
V24 GPIO7 / SIGDET_7
V23 GPIO6 / SIGDET_6
W26 GPIO5 / SIGDET_5
Y24 GPIO1 / SIGDET_1
Y23 GPIO0 / SIGDET_0

Pin Descriptions
7.2.4 Twisted Pair Interface

The following table lists the device pins associated with the device two-wire, twisted pair interface.
Table 85 • Twisted Pair Interface Pins

G1 TXVPA_7 ADIFF TX/RX channel A positive signal
C1 TXVPA_6
A6 TXVPA_5
A10 TXVPA_4
A14 TXVPA_3
A18 TXVPA_2
A22 TXVPA_1
D26 TXVPA_0
G2 TXVNA_7 ADIFF TX/RX channel A negative signal
C2 TXVNA_6
B6 TXVNA_5
B10 TXVNA_4
B14 TXVNA_3
B18 TXVNA_2
B22 TXVNA_1
D25 TXVNA_0
F1 TXVPB_7 ADIFF TX/RX channel B positive signal
A3 TXVPB_6
A7 TXVPB_5
A11 TXVPB_4
A15 TXVPB_3
A19 TXVPB_2
A23 TXVPB_1
E26 TXVPB_0
F2 TXVNB_7 ADIFF TX/RX channel B negative signal
B3 TXVNB_6
B7 TXVNB_5
B11 TXVNB_4
B15 TXVNB_3
B19 TXVNB_2
B23 TXVNB_1
E25 TXVNB_0
E1 TXVPC_7 ADIFF TX/RX channel C positive signal
A4 TXVPC_6
A8 TXVPC_5
A12 TXVPC_4
A16 TXVPC_3
A20 TXVPC_2
A24 TXVPC_1
F26 TXVPC_0
E2 TXVNC_7 ADIFF TX/RX channel C negative signal
B4 TXVNC_6
B8 TXVNC_5
B12 TXVNC_4
B16 TXVNC_3
B20 TXVNC_2
B24 TXVNC_1
F25 TXVNC_0

Pin Descriptions
Table 85 • Twisted Pair Interface Pins (continued)

D1 TXVPD_7 ADIFF TX/RX channel D positive signal
A5 TXVPD_6
A9 TXVPD_5
A13 TXVPD_4
A17 TXVPD_3
A21 TXVPD_2
A25 TXVPD_1
G26 TXVPD_0
D2 TXVND_7 ADIFF TX/RX channel D negative signal
B5 TXVND_6
B9 TXVND_5
B13 TXVND_4
B17 TXVND_3
B21 TXVND_2
B25 TXVND_1
G25 TXVND_0
7.2.5 Serial Management Interface

The following table lists the device pins associated with the device serial management interface (SMI).
Note that the pins in this table, except for EECLK and EEDAT, are referenced to VDDIO and can be set to
a 1.8 V, 2.5 V, or 3.3 V power supply. The EECLK and EEDAT pins are instead referenced to VDD33.
Table 86 • SMI Pins

U3 MDC I Management data clock. A 0 MHz to 12.5 MHz reference
input is used to clock serial MDIO data into and out of the
PHY.
V3 MDIO OD Management data input/output pin. Serial data is written
or read from this pin bidirectionally between the PHY and
Station Manager, synchronously on the positive edge of
MDC. One external pull-up resistor is required at the
Station Manager, and its value depends on the MDC clock
frequency and the total sum of the capacitive loads from
the MDIO pins.
Y4 MDINT_7 OS/OD Management interrupt signal. Upon reset the device will
Y3 MDINT_6 configure these pins as active-low (open drain) or active-
Y2 MDINT_5 high (open source) based on the polarity of an external
Y1 MDINT_4 10 kΩ resistor connection. These pins can be tied
W4 MDINT_3 together in a wired-OR configuration with only a single
W3 MDINT_2 pull-up or pull-down resistor.
W2 MDINT_1
W1 MDINT_0

Pin Descriptions
Table 86 • SMI Pins (continued)

P2 EEDAT IPD/O (Optional) EEPROM serial I/O data. Used to configure
PHYs in a system without a Station Manager. Connect to
the SDA pin of the ATMEL “AT24CXXX” serial EEPROM
device family.
The VSC8658 device determines that an external
EEPROM is present by monitoring the EEDAT pin at
power-up or when NRESET is de-asserted. If EEDAT has
a 4.7 kΩ external pull-up resistor, the VSC8658 assumes
an EEPROM is present. The EEDAT pin can be left
floating or grounded to indicate no EEPROM.
P1 EECLK O (Optional) EEPROM serial output clock. Used to configure
PHYs in a system without a station manager. Connect to
the SCL pin of the ATMEL “AT24CXXX” serial EEPROM
device family.
AA3 NRESET IPU Device reset. Active low input that powers down the
device and sets the register bits to their default state.
V1 CLKOUT O Clock output can be enabled or disabled and also output
a reference clock frequency of 125 MHz or 156.25 MHz
using CMODE or register setting. This pin is not active
when NRESET is asserted. When disabled, the pin is held
low.
7.2.6 JTAG
The following table lists the pins associated with the device JTAG testing facility.
Table 87 • JTAG Pins

U1 TDI IPU5V JTAG test serial data input.
T4 TDO O JTAG test serial data output.
T1 TMS IPU5V JTAG test mode select.
T2 TCK IPU5V JTAG test clock input.
T3 NTRST IPU5V JTAG reset. If JTAG is not used, then tie this pin to VSS
(ground) with a pull-down resistor.
7.2.7 Power Supply

The following table lists the device power supply pins.
Table 88 • Power Supply Pins

C3 C4 C10 C11 C12 C16 C17 C21 C23 VDD33 3.3 V General 3.3 V power supply
C25 D3 D4 D10 D11 D12 D16 D17 D21
D22 F24 G23 H23 H24 J23 M23 M24
N1 N2 N3 N4 R25 R26 U4 AA23 AB23
AD3 AD5 AD7 AD11 AD12 AD14 AD17
AD20 AD21

Pin Descriptions
Table 88 • Power Supply Pins (continued)

U2 V2 AB4 VDDIO 3.3 V I/O power supply
2.5 V
1.8 V
K8 K19 L8 L19 M8 M19 N8 N19 P8 VDD12 1.2 V Internal digital core voltage
P19 R8 R19 T8 T19 U8 U9 U10 U11
U12 U13 U14 U15 U16 U17 U18 U19
C7 C13 C19 C20 D6 D7 D13 D19 D20 VDD12A 1.2 V 1.2 V analog power requiring additional PCB power
D23 E3 E4 E24 AB24 AC4 AC5 AC7 supply filtering
AC8 AC11 AC12 AC13 AC15 AC16
AC18 AC19 AC20 AC24 AD8 AD19
A2 B1 B2 B26 C5 C8 C9 C14 C15 C18 VSS 0V General device ground
C24 C26 D5 D8 D9 D14 D15 D18 D24
F3 H1 H2 H3 H4 H26 K1 K2 K9 K10
K11 K12 K13 K14 K15 K16 K17 K18
K23 L9 L10 L11 L12 L13 L14 L15 L16
L17 L18 L23 M9 M10 M11 M12 M13
M14 M15 M16 M17 M18 N9 N10 N11
N12 N13 N14 N15 N16 N17 N18 P9
P10 P11 P12 P13 P14 P15 P16 P17
P18 R9 R10 R11 R12 R13 R14 R15
R16 R17 R18 T9 T10 T11 T12 T13 T14
T15 T16 T17 T18 V4 Y25 Y26 AA4
AA24 AB3 AC3 AC6 AC9 AC10 AC14
AC17 AC21 AC22 AC23 AD4 AD6 AD9
AD10 AD13 AD15 AD16 AD18 AD22
AD23 AD24 AE1 AE26
Although certain function pins may not be used for a specific application, all power supply pins must be
connected to their respective voltage input.
Table 89 • Power Supply and Associated Function Pins
Nominal
Pin Voltage Associated Functional Pins
VDD33 3.3 V LED[3:0]_n, GPIO[15:0], EECLK, EEDAT, JTAG (5), XTAL1,
XTAL2, CMODE, TXVP_n, TXVN_n, REF_FILT, REF_REXT
VDDIO 1.8 V, 2.5 V, MDC, MDIO, MDINT_n, nRESET, CLKOUT
3.3 V
VDD12A 1.2 V MAC_RDP/N_n, MAC_TDP/N_n
VDD12 1.2 V N/A (Internal Core Voltage)

Pin Descriptions
7.2.8 Miscellaneous
The following table lists pins not associated with a particular interface or facility on the device.
Table 90 • Miscellaneous Pins

H25 CMODE7 IA Configuration mode (CMODE) pins. For more
J24 CMODE6 information, see CMODE, page 55.
J25 CMODE5
J26 CMODE4
K24 CMODE3
K25 CMODE2
K26 CMODE1
L24 CMODE0
J1 XTAL1/REFCLK I Crystal oscillator input. If OSCEN=high then a
25 MHz parallel resonant crystal with +/–50 ppm
frequency tolerance should be connected across
XTAL1 and XTAL2. A 33 pF capacitor should also
tie the XTAL1 pin to ground.
Reference clock input. If OSCEN=low, the clock
input frequency can either be 25 MHz
(PLLMODE=0) or 125 MHZ (PLLMODE is high).
J2 XTAL2 OCRYST Crystal oscillator output. The crystal should be
connected across XTAL1 and XTAL2. A 33 pF
capacitor should also tie the XTAL2 pin to ground.
If not using a crystal oscillator, this output pin can
be left floating if driving XTAL1/REFCLK with a
reference clock.
R2 OSCEN IPD Oscillator enable. This pin is sampled on the rising
edge of NRESET. If HIGH, then the on-chip
oscillator circuit is enabled. If low (or left floating),
the oscillator circuit is disabled and the device
must be supplied with a 25 MHz or 125 MHz
reference clock to the REFCLK pin
R1 PLLMODE IPD PLL mode input select. Sampled on power-up or
reset. If PLLMODE is low, then REFCLK must be
25 MHz. If PLLMODE is high, then REFCLK must
be 125 MHz.
J3 J4 K3 K4 LED[3:0]_7 O LED direct-drive outputs. All LEDs pins are active-
L1 L2 M1 M2 LED[3:0]_6 low. A serial LED stream can also be
L3 L4 M3 M4 LED[3:0]_5 implemented. For more information about LED
P3 P4 R3 R4 LED[3:0]_4 operation, see LED Mode Select, page 43.
T23 T24 R23 R24 LED[3:0]_3
P23 P24 N23 N24 LED[3:0]_2
P25 P26 N25 N26 LED[3:0]_1
M25 M26 L25 L26 LED[3:0]_0
F23 REF_REXT_A ABIAS Reference external connects to an external 2 KΩ
(1%) resistor to analog ground.
E23 REF_FILT_A ABIAS Reference filter connects to an external 1 µF
capacitor to analog ground.
F4 REF_REXT_B ABIAS Reference external connects to an external 2 KΩ
(1%) resistor to analog ground.

Pin Descriptions
Table 90 • Miscellaneous Pins (continued)

G4 REF_FILT_B ABIAS Reference filter connects to an external 1 µF
capacitor to analog ground.
G3 C6 C22 G24 NC NC These pins are no connects. Do not connect them
together or to ground. Leave these pins
unconnected (floating).

Package Information
8 Package Information
The VSC8658 device is available in two package types. VSC8658HJ is a 444-pin, thermally enhanced,
plastic ball grid array (BGA) with a 27 mm × 27 mm body size, 1 mm pin pitch, and a 2.36 mm maximum
height. The device is also available in a lead(Pb)-free package, VSC8658XHJ.
Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint
IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC
standard.
This section provides the package drawing, thermal specifications, and moisture sensitivity rating for the
VSC8658 device.
8.1 Package Drawing

The following illustration shows the package drawing for the VSC8658 device. The drawing contains the
top view, bottom view, side view, dimensions, tolerances, and notes.

Package Information
Figure 25 • Package Drawing

Top View Bottom View
0.10 M C
f.
Re
0.25 M C A B
)
(3
Pin #1 corner 0.50~ 0.70 ( 44 )
00
1.
2 4 6 8 10 12 14 16 18 20 22 24 26 26 24 22 20 18 16 14 12 10 8 6 4 2
1 3 5 7 9 11 13 15 17 19 21 23 25 25 23 21 19 17 15 13 11 9 7 5 3 1
A A
B B
C C
D D
E E
1.00
F F
G G
H H
27.00 +/-0.20
J J
K K
24.00 Ref.
L L
25.00
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC
AC
AD
AD AE
AE AF
AF
E
4.00 * 45 (4 ) B 1.00
24.00 Ref. Heat slug 25.00

D 19.0~20.0 A 27.00 +/-0.20
0.06
0.30 S C AS B S 0.20 (4 )
0.50 S C DS E S
0.25 C
0.35 C
1.17 Ref.
0.20 C
30 Typ. Side View

0.56 Ref.
0.40~0.60
C Seating plane
2.23 +/-.13
Note:
All dimensions are in millimeters (mm).
8.2 Thermal Specifications

Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been
modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p
PCB). For more information, see the JEDEC standard.
Table 91 • Thermal Resistances
θJA (°C/W) vs. Airflow (ft/min)

Part Order Number θJC θJB 0 100 200
VSC8658HJ 4.1 7.3 13.4 13.2 13
VSC8658XHJ 4.1 7.3 13.4 13.2 13

Package Information
To achieve results similar to the modeled thermal resistance measurements, the guidelines for board
design described in the JEDEC standard EIA/JESD51 series must be applied. For information about
specific applications, see the following:
EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal
Attachment Mechanisms
EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements
8.3 Moisture Sensitivity

Moisture sensitivity level ratings for Microsemi products comply with the joint IPC and JEDEC standard
IPC/JEDEC J-STD-020.
VSC8658HJ is rated moisture sensitivity level 3 or better.
VSC8658XHJ is rated moisture sensitivity level 4.
For more information, see the IPC and JEDEC standard.

Design Considerations
9 Design Considerations
This section provides information about design issues for the VSC8658 device.
9.1 PHY Address ID (Register 23E, Bits 15 to 11)

Issue: The PHY Address ID in Register 23E does not function as intended. It can only indicate the
physical PHY port numbers 0 through 7 instead of those set through the CMODE pins.
Implications: A user needs to be aware that this address only represents the physical port number as
opposed to the actually PHY address on the MDC/MDIO bus.
Workaround: Software needing this feature must detect which specific device it is communicating to and
add a necessary offset to the address value to process the correct address.
9.2 JTAG Input High Voltage at 2.1 V

Issue: The JTAG pins do not meet the VIH(min) requirements of the CMOS and LVTTL standards. At
certain PVT corners, the minimum is 2.1 V.
Implications: None.
Workaround: None.
9.3 First SMI Write Fails After Software Reset

Issue: After applying software reset (using either register 0, bit 15 or the NSRESET pin), the first
subsequent SMI write operation into register 4 (auto-negotiation advertisement) or register 9
(1000BASE-T control) does not work. This issue only occurs if the first SMI write after software reset is
into register 4 or 9. This issue does not occur if any kind of SMI transaction (either read or write) is
applied to any register between the time of the software reset and the SMI write into register 4 or 9.
Implications: The PHY may operate unexpectedly, because settings for registers 4 and 9 remain at the
reset value. There are no such implications after either hardware reset or power-down events.
Workaround: Writing “0x0000” into register 31 after every software reset avoids this issue, and
subsequent SMI writes into register 4 or 9 succeed.
9.4 LED3 Port 7 Coupling Issue into XTAL Clock Pin

Issue: Whenever LED3 Port 7 blinks, the resulting noise couples into the XTAL clock input pin. This
causes additional noise on the transmit SerDes interface in the form of transmit jitter. In this case,
transmit jitter increases to a value in the range of 360 ps to 380 ps. This behavior is not seen with other
LED pins.
Implications: Using both the LED3 Port 7 and XTAL pins causes a higher level of transmit jitter on the
SerDes interface of the device.
Workaround: For better performance, avoid using the LED3 Port 7 pin as an LED indication.
9.5 100BASE-FX Clock Data Recovery Improvement

Issue: It is possible to improve the overall receive data performance in 100BASE-FX media by changing
the standard settings for the Clock Data Recovery (CDR) block.
Implications: While there is a low chance of seeing an issue in 100BASE-FX, it is recommended to
implement this script.
Workaround: There is a software workaround for this problem that can improve the 100BASE-FX CDR.
Change the CDR settings using the following script at PHY initialization time:
PhyWrite( PortNo, Register (dec), 16_bit_unsigned_data(hex) );
16_bit_unsigned_data = PhyRead( PortNo, Register (dec) );

Design Considerations
PhyWrite( PortNo, 31, 0x52b5 ); // Switch to internal block

PhyWrite( PortNo, 16, 0xae0e ); // Read CDR internal register
Reg18 = PhyRead( PortNo, 18 );
Reg17 = PhyRead( PortNo, 17 );
Reg17 = Reg17 & 0xffef; // Clear bit 4 of this register
PhyWrite( PortNo, 18, Reg18 );
PhyWrite( PortNo, 17, Reg17 );
PhyWrite( PortNo, 16, 0x8e0e ); // Write CDR internal register
PhyWrite( PortNo, 31, 0x0000 ); // Goto Normal Page

Ordering Information
10 Ordering Information
The VSC8658 device is available in two package types. VSC8658HJ is a 444-pin, thermally enhanced,
plastic ball grid array (BGA) with a 27 mm × 27 mm body size, 1 mm pin pitch, and a 2.36 mm maximum
height. The device is also available in a lead(Pb)-free package, VSC8658XHJ.
Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint
IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC
standard.
The following table lists the ordering information for the VSC8658 device.
Table 92 • Ordering Information
Part Order Number Description

VSC8658HJ 444-pin, thermally enhanced, plastic BGA with a 27 mm × 27 mm body size,
1 mm pin pitch, and a 2.36 mm maximum height
VSC8658XHJ Lead(Pb)-free, 444-pin, thermally enhanced, plastic BGA with a 27 mm ×
27 mm body size, 1 mm pin pitch, and a 2.36 mm maximum height

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VSC8658 Datasheet

Octal 10/100/1000BASE-T PHY and 100BASE-

VMDS-10242. 4.1 11/18

VMDS-10242 VSC8658 Datasheet Revision 4.1 iii

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Figure 1 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

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Table 1 Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

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1.1 Revision 4.1

1.2 Revision 4.0

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1.3 Revision 2.0

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2.1 Register and Bit Conventions

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10/100/1000 Mbps Ethernet MAC RJ-45 and Magnetics

3.1 Features and Benefits

Table 1 • Features and Benefits

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Table 1 • Features and Benefits (continued)

3.2 Block Diagram

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Figure 2 • High-level Block Diagram

Auto-Negotiation (SGMII, FIFOs)

M A C_ T D P _ n Serial MAC Interface (SerDes)

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4.1 Operating Modes

Table 2 • Operating Mode vs. Speed

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Table 2 • Operating Mode vs. Speed (continued)

1. The MAC used must be capable of supporting this media.

4.1.1 SerDes MAC-to-Cat5 Mode MAC Interface

SerDes MAC VSC8658

4.1.2 SGMII MAC-to-Cat5 Mode MAC Interface

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Figure 4 • SGMII MAC Interface

4.1.3 All Modes Cat5 Media Interface

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4.2 SerDes Media Interface

4.3 SGMII MAC-to-100BASE-FX Mode

4.4 Automatic Media-Sense (AMS) Interface Mode

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Figure 6 • Automatic Media Sense Block Diagram

Table 3 • AMS Media Preferences

Cat5 Linked, SerDes Linked, Both Cat5 and

4.5 Cat5 Auto-Negotiation

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4.6 Manual MDI/MDI-X Setting

4.7 Automatic Crossover and Polarity Detection

Table 4 • Supported MDI Pair Combinations

RJ-45 Pin Pairings

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4.8 Link Speed Downshift

4.9 Transformerless Ethernet

4.10 Ethernet Inline Powered Devices

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