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Unit-I

Introduction of BJT

Power Bipolar Junction Transistor (BJT) is the first semiconductor device to allow full control over its
Turn on and Turn off operations. It simplified the design of a large number of Power Electronic circuits
that used forced commutated thyristors at that time and also helped realize a number of new circuits.
Subsequently, many other devices that can broadly be classified as “Transistors” have been developed.
Many of them have superior performance compared to the BJT in some respects. They have, by now,
almost completely replaced BJTs. However, it should be emphasized that the BJT was the first
semiconductor device to closely approximate an ideal fully controlled Power switch. Other “transistors”
have characteristics that are qualitatively similar to those of the BJT (although the physics of operation
may differ). Hence, it will be worthwhile studying the characteristics and operation a BJT in some depth.
From the point of view of construction and operation BJT is a bipolar (i.e. minority carrier) current
controlled device. It has been used at signal level power for a long time. However, the construction and
operating characteristics of a Power BJT differs significantly from its signal level counterpart due to the
requirement for a large blocking voltage in the “OFF” state and a high current carrying capacity in the
“ON” state. In this module, the construction, operating principle and characteristics of a Power BJT will
be explored.

Basic Operating Principle of a Bipolar Junction Transistor A junction transistor consists of a

semiconductor crystal in which a p type region is sandwiched between two n type regions. This is called
an n-p-n transistor. Alternatively an n type region may be placed in between two p type regions to give a
p-n-p transistor. Fig shows the circuit symbols and schematic representations of an n-p-n and a p-n-p
transistor. The terminals of a transistor are called Emitter (E), Base (B) & Collector (C) as shown in the
figure.
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Fig. Bipolar junction transistor under different biasing condition. (a) n – p – n transistor ; (b) p – n – p
transistor.

If no external biasing voltages are applied (i.e.; VBB and VCC are open circuited) all transistor currents
must be zero. The transistor will be in thermal equilibrium condition with potential barriers

at the base emitter and the base collector functions respectively. Corresponding
depletion layer widths will be WoBE and WoCB . It is clear from the diagram that p type carriers in the
base region of an n-p-n transistor are trapped in a “potential well” and cannot escape. Similarly, in a p-
n-p transistor p type carriers in the emitter and collector regions are separated by a “potential hill”.
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When biasing voltages are applied as shown in the figure, the base emitter junction (JBE)
becomes forward biased where as the base collector junction is reverse biased. Potential barrier and

depletion layer width at JBE reduces to and respectively. Both these quantities increase at JCB

As the potential barrier at JBE is reduced a large number of minority carriers are introduced
in to Base and the Emitter regions as shown in Fig. 1

.A portion of the minority

carriers reaching the base recombines with majority carriers. The rest, defuse to the edge of the
depletion region at JCB where they are swept away to the collector region by the large electric field.
Under this condition the transistor is said to be in the Active region.

As VBE is increased injected minority charge into the base region increases and so does the base current
and the collector current. For a fixed collector bias voltage VCC, the voltage VCB reduces with increase in
collector current due to increasing drop in the external resistance RC. Therefore, the potential barrier at
JCB starts reducing. At one point JCB becomes forward biased. The potential barriers and depletion layer
widths under this condition are indicated in Fig. 1 by variables with a super script “s”. Due to forward
biasing of JCB there will be minority carrier injection into the base from this junction also as shown in
Fig. 1. The total voltage drop between collector and emitter will be the difference between the forward
bias voltage drops at JBE and JCB. Under this condition the transistor is said to be in the saturation
region.

From the operating principle described above one can form a qualitative idea about the input (iB vs
VBE) and output (iC Vs VCE) characteristics of a transistor. In the following section these characteristics
of an n-p-n transistor will be discussed qualitatively. Similar explanation applies to a p-n-p transistor.

When a biasing voltage VBB of appropriate polarity is applied across the junction JBE the potential
barrier at this junction reduces and at one point the junction becomes forward biased. The current
crossing this junction is governed by the forward biased p-n junction equation for a given collector
emitter voltage. The base current iB is related to the recombination of minority carriers injected into the
base from the emitter. The rate of recombination is directly proportional to the amount of excess
minority carrier stored in the base. Since, in a normal transistor the emitter is much more heavily doped
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compared to the base the current crossing JBE is almost entirely determined by the excess minority
carrier distribution in the base. Thus, it can be concluded that the relationship between iB and VBE will
be similar to the i-v characteristics of a p-n junction diode. VCE, however have some effect on this
characteristic. As VCE increases reverse bias of JCB increases and the depletion region at JCB moves
deeper into the base. The effective base width thus reduces, reducing the rate of recombination in the
base region and hence the base current. Therefore iB for a given VBE reduces with increasing VCE as
shown in Fig. 2(a).

It has been mentioned before that only a fraction (denoted by the letter “∝”) of the total minority
carriers injected into the base reaches junction JCB where they are swept in to the collector region by
the large electric field at JCB. These minority carriers constitute the major component of the total
collector current. The other component of the collector current consists of the small reverse saturation
current of the reverse biased junction JCB.

β is called the large signal common emitter current gain of the transistor and remains fairly constant
for a large range of IC, as shown in Fig. 2 (c). Fig: 2 (b) shows the complete out put characteristics (ic vs
VCE) of an n-p-n transistor. With VBB = 0 or negative there is little injected minority carrier into the base
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from the emitter side. Therefore, iB = 0 and iC is negligibly small. The transistor is said to be in the “cut
off” region under this condition.

As VBB is increased from zero, base current starts flowing. From equations it will be expected that the
collector current should increase proportionately independent of VCE. However Fig 2 (b) does indicate a
slight increase in iC with VCE for a given iB. This is expected because with increasing VCE a larger value
of VBE will be required to maintain a given iB (Fig. 2 (a)). Therefore, the component “∝IE” of collector
current will increase. ICS is ,for all practical purpose, independent of VCE. This is the active or “amplifier
mode” of operation of a transistor.

In the active region as iB increases iC also increases. For a given value of VCC, VCE reduces with
increasing iC due to increased drop in an external load (i.e., Rc in Fig 1). At one point the junction JCB
becomes forward biased. VCE, now is just the difference between the voltages across two forward
biased junction JBE and JCB (a few handed milli volts). This is when the transistor enters the saturation
mode of operation. The ratio iC/iB at the onset of saturation is called βMin and is an important
parameter for a power transistor. In saturation iC is almost entirely determined by the external load
and further increase in iB changes iC or VCE very little.
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Fig. 2: Input and output characteristics of an n – p – n transistor. (a) Input characteristics; (b) Output
characteristics; (c) Current gain[β] characteristics
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UNIT-II

Introduction

Although the large semiconductor diode was a predecessor to thyristors, the modern power electronics
area truly began with advent of thyristors. One of the first developments was the publication of the P-
N-P-N transistor switch concept in 1956 by J.L. Moll and others at Bell Laboratories, probably for use in
Bell’s Signal application. However, engineers at General Electric quickly recognized its significance to
power conversion and control and within nine months announced the first commercial Silicon
Controlled Rectifier in 1957. This had a continuous current carrying capacity of 25A and a blocking
voltage of 300V. Thyristors (also known as the Silicon Controlled Rectifiers or SCRs) have come a long
way from this modest beginning and now high power light triggered thyristors with blocking voltage in
excess of 6kv and continuous current rating in excess of 4kA are available. They have reigned supreme
for two entire decades in the history of power electronics. Along the way a large number of other
devices with broad similarity with the basic thyristor (invented originally as a phase control type device)
have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch (SCS), light
activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse Conducting Thyristor (RCT), Diac, Triac
and the Gate turn off thyristor (GTO).

From the construction and operational point of view a thyristor is a four layer, three terminal, minority
carrier semi-controlled device. It can be turned on by a current signal but can not be turned off without
interrupting the main current. It can block voltage in both directions but can conduct current only in one
direction. During conduction it offers very low forward voltage drop due to an internal latch-up
mechanism. Thyristors have longer switching times (measured in tens of μs) compared to a BJT. This,
coupled with the fact that a thyristor can not be turned off using a control input, have all but eliminated
thyristors in high frequency switching applications involving a DC input (i.e, choppers, inverters).
However in power frequency ac applications where the current naturally goes through zero, thyristor
remain popular due to its low conduction loss its reverse voltage blocking capability and very low control
power requirement. In fact, in very high power (in excess of 50 MW) AC – DC (phase controlled
converters) or AC – AC (cyclo-converters) converters, thyristors still remain the device of choice.
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Basic operating principle of a thyristor

The underlying operating principle of a thyristor is best understood in terms of the “two transistor
analogy” as explained below.

Fig. 2.1: Constructional features of a thysistor (a) Circuit Symbol, (b) Schematic Construction, (c)
Photograph

As shown in Fig 2.1 (b) the primary crystal is of lightly doped n- type on either side of which two p type
layers with doping levels higher by two orders of magnitude are grown. As in the case of power diodes
and transistors depletion layer spreads mainly into the lightly doped n-region. The thickness of this layer
is therefore determined by the required blocking voltage of the device. However, due to conductivity
modulation by carriers from the heavily doped p regions on both side during ON condition the “ON
state” voltage drop is less. The outer n+ layers are formed with doping levels higher then both the p
type layers. The top p layer acls as the “Anode” terminal while the bottom n+ layers acts as the
“Cathode”. The “Gate” terminal connections are made to the bottom p layer.
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As it will be shown later, that for better switching performance it is required to maximize the peripheral
contact area of the gate and the cathode regions. Therefore, the cathode regions are finely distributed
between gate contacts of the p type layer. An “Involute” structure for both the gate and the cathode
regions is a preferred design structure.

Basic operating principle of a thyristor

The underlying operating principle of a thyristor is best understood in terms of the “twotransistor
analogy” as explained below.

Fig. 2.2: Two transistor analogy of a thyristor construction. (a) Schematic Construction, (b) Schematic
division in component transistor (c) Equivalent circuit in terms of two transistors.

a) Schematic construction,

b) Schematic division in component transistor

c) Equivalent circuit in terms of two transistors.

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Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode positive with
respect to the cathode and the gate terminal open. With this voltage polarity J1 & J3 are forward biased
while J2 reverse biased.

Under this condition.

Where ∝1 & ∝2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse saturation
currents of the CB junctions of Q1 & Q2 respectively.

Now from Fig 2.2 (c).

Combining Eq 2.1 & 2.4

Where is the total reverse leakage current of J2.

Now as long as VAK is small Ico is very low and both ∝1 & ∝2 are much lower than unity. Therefore,
total anode current IA is only slightly greater than Ico. However, as VAK is increased up to the avalanche
break down voltage of J2, Ico starts increasing rapidly due to avalanche multiplication process. As Ico
increases both ∝1 & ∝2 increase and ∝1 + ∝2 approaches unity. Under this condition large anode
current starts flowing, restricted only by the external load resistance. However, voltage drop in the
external resistance causes a collapse of voltage across the thyristor. The CB junctions of both Q1 & Q2
become forward biased and the total voltage drop across the device settles down to approximately
equivalent to a diode drop. The thyristor is said to be in “ON” state.
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Just after turn ON if Ia is larger than a specified current called the Latching Current IL, ∝1 and ∝2
remain high enough to keep the thyristor in ON state. The only way the thyristor can be turned OFF is
by bringing IA below a specified current called the holding current (IH) where upon ∝1 & ∝2 starts
reducing. The thyristor can regain forward blocking capacity once excess stored charge at J2 is removed
by application of a reverse voltage across A & K (ie, K positive with respect A).

It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to
cathode) without increasing the forward voltage across the device up to the forward break-over level.
With a positive gate current equation 2.4 can be written as

Combining with Eqns. 2.1 to 2.3

Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and hence VAK).
This is called gate assisted turn on of a Thyristor. This is the usual method by which a

thyristor is turned ON. When a reverse voltage is applied across a thyristor (i.e, cathode positive with
respect to anose.) junctions J1 and J3 are reverse biased while J2 is forward biased. Of these, the
junction J3 has a very low reverse break down voltage since both the n+ and p regions on either side of
this junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported by
junction J1. The maximum value of the reverse voltage is restricted by

a) The maximum field strength at junction J1 (avalanche break down)

b) Punch through of the lightly doped n- layer.

Since the p layers on either side of the n- region have almost equal doping levels the avalanche break
down voltage of J1 & J2 are almost same. Therefore, the forward and the reverse break down voltage of
a thyristor are almost equal.Up to the break down voltage of J1 the reverse current of the thyristor
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remains practically constant and increases sharply after this voltage. Thus, the reverse characteristics of
a thyristor is similar to that of a single diode.

If a positive gate current is applied during reverse bias condition, the junction J3 becomes forward
biased. In fact, the transistors Q1 & Q2 now work in the reverse direction with the roles of their
respective emitters and collectors interchanged. However, the reverse ∝1 & ∝2 being significantly
smaller than their forward counterparts latching of the thyristor does not occur. However, reverse
leakage current of the thyristor increases considerably increasing the OFF state power loss of the device.

If a forward voltage is suddenly applied across a reverse biased thyristor, there will be considerable
redistribution of charges across all three junctions. The resulting current can become large enough to

satisfy the condition ∝1 + ∝2 = 1 and consequently turn on the thyristor. This is called 𝑑𝑣⁄𝑑𝑡 turn on of

a thyristor and should be avoided.

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Steady State Characteristics of a Thyristor

Static output i-v characteristics of a thyristor

Fig. 2.3: Static output characteristics of a Thyristor

The circuit symbol in the left hand side inset defines the polarity conventions of the variablesused in this
figure.

With ig = 0, VAK has to increase up to forward break over voltage VBRF before significant anode current
starts flowing. However, at VBRF forward break over takes place and the voltage across the thyristor
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drops to VH (holding voltage). Beyond this point voltage across the thyristor (VAK) remains almost
constant at VH (1-1.5v) while the anode current is determined by the external load.

The magnitude of gate current has a very strong effect on the value of the break over voltage as shown
in the figure. The right hand side figure in the inset shows a typical plot of the forward break over
voltage (VBRF) as a function of the gate current (Ig)

After “Turn ON” the thyristor is no more affected by the gate current. Hence, any current pulse (of
required magnitude) which is longer than the minimum needed for “Turn ON” is sufficient to effect
control. The minimum gate pulse width is decided by the external circuit and should be long enough to
allow the anode current to rise above the latching current (IL) level.

The left hand side of Fig 2.3 shows the reverse i-v characteristics of the thyristor. Once the thyristor is
ON the only way to turn it OFF is by bringing the thyristor current below holding current (IH). The gate
terminal has no control over the turn OFF process. In ac circuits with resistive load this happens
automatically during negative zero crossing of the supply voltage. This is called “natural commutation”
or “line commutation”. However, in dc circuits some arrangement has to be made to ensure this
condition. This process is called “forced commutation.”

During reverse blocking if ig = 0 then only reverse saturation current (Is) flows until the reverse voltage
reaches reverse break down voltage (VBRR). At this point current starts rising sharply. Large reverse
voltage and current generates excessive heat and destroys the device. If ig > 0 during reverse bias
condition the reverse saturation current rises as explained in the previous section. This can be avoided
by removing the gate current while the thyristor is reverse biased.

The static output i-v characteristics of a thyristor depends strongly on the junction temperature as
shown in Fig 2.4.
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Fig. 2.4: Effect of junction temperature (Tj) on the output i – v characteristics of a thyristor.

Thyristor Gate Characteristics

The gate circuit of a thyristor behaves like a poor quality diode with high on state voltage drop and low
reverse break down voltage. This characteristic usually is not unique even within the same family of
devices and shows considerable variation from device to device. Therefore, manufacturer’s data sheet
provides the upper and lower limit of this characteristic as shown in Fig 2.5.
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Fig. 2.5: Gate characteristics of a thyristor.

Each thyristor has maximum gate voltage limit (Vgmax), gate current limit (Igmax) and maximum

average gate power dissipation limit ( ) . These limits should not be exceeded in order to avoid
permanent damage to the gate cathode junction. There are also minimum limits of Vg (Vgmin) and Ig
(Igmin) for reliable turn on of the thyristor. A gate non triggering voltage (Vng) is also specified by the
manufacturers of thyristors. All spurious noise signals should be less than this voltage Vng in order to
prevent unwanted turn on of the thyristor. The useful gate drive area of a thyristor is then b c d e f g h.

Referring to the gate drive circuit in the inset the equation of the load line is given by

A typical load line is shown in Fig 2.5 by the line S1 S2.

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The actual operating point will be somewhere between S1 & S2 depending on the particular device.

For optimum utilization of the gate ratings the load line should be shifted forwards the curve

without violating or ratings. Therefore, for a dc source E c f represents the optimum load
line from which optimum values of E & Rg can be determined.

It is however customary to trigger a thyristor using pulsed voltage & current. Maximum power
dissipation curves for pulsed operation (Pgm) allows higher gate current to flow which in turn reduces
the turn on time of the thyristor. The value of Pgm depends on the pulse width (TON) of the gate
current pulse. TON should be larger than the turn on time of the thyristor. For TON larger than 100 μs,
average power dissipation curve should be used. For TON less than 100 μs the following relationship
should be maintained.

The magnitude of the gate voltage and current required for triggering a thyristor is inversely
proportional to the junction temperature.

The gate cathode junction also has a maximum reverse (i.e, gate negative with respect to the cathode)
voltage specification. If there is a possibility of the reverse gate cathode voltage exceeding this limit a
reverse voltage protection using diode as shown in Fig 2.6 should be used.
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Fig. 2.6: Gate Cathode reverse voltage protection circuit.

Switching Characteristics of a Thyristor

During Turn on and Turn off process a thyristor is subjected to different voltages across it and different
currents through it. The time variations of the voltage across a thyristor and the current through it
during Turn on and Turn off constitute the switching characteristics of a thyristor.

Turn on Switching Characteristics

A forward biased thyristor is turned on by applying a positive gate voltage between the gate and
cathode as shown in Fig 2.7.
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Fig. 2.7: Turn on characteristics of a thyristor.

Fig 2.7 shows the waveforms of the gate current (ig), anode current (iA) and anode cathode voltage
(VAK) in an expanded time scale during Turn on. The reference circuit and the associated waveforms are
shown in the inset. The total switching period being much smaller compared to the cycle time, iA and
VAK before and after switching will appear flat.

As shown in Fig 2.7 there is a transition time “tON” from forward off state to forward on state. This
transition time is called the thyristor turn of time and can be divided into three separate intervals
namely, (i) delay time (td) (ii) rise time (tr) and (iii) spread time (tp). These times are shown in Fig 4.7 for
a resistive load.

Delay time (td): After switching on the gate current the thyristor will start to conduct over the portion of
the cathode which is closest to the gate. This conducting area starts spreading at a finite speed until the
entire cathode region becomes conductive. Time taken by this process constitute the turn on delay time
of a thyristor. It is measured from the instant of application of the gate current to the instant when the
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anode current rises to 10% of its final value (or VAK falls to 90% of its initial value). Typical value of “td”
is a few micro seconds.

Rise time (tr): For a resistive load, “rise time” is the time taken by the anode current to rise from 10% of
its final value to 90% of its final value. At the same time the voltage VAK falls from 90% of its initial value
to 10% of its initial value. However, current rise and voltage fall characteristics are strongly influenced
by the type of the load. For inductive load the voltage falls faster than the current. While for a capacitive
load VAK falls rapidly in the beginning. However, as the current increases, rate of change of anode
voltage substantially decreases.

If the anode current rises too fast it tends to remain confined in a small area. This can give rise tolocal
“hot spots” and damage the device. Therefore, it is necessary to limit the rate of rise of the ON state
current 𝑑𝑖A/𝑑𝑡 by using an inductor in series with the device. Usual values of maximum allowable

is in the range of 20-200 A/μs.

Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to 100%.
During this time conduction spreads over the entire cross section of the cathode of the thyristor. The
spreading interval depends on the area of the cathode and on the gate structure of the thyristor.

Turn off Switching Characteristics

Once the thyristor is on, and its anode current is above the latching current level the gate loses control.
It can be turned off only by reducing the anode current below holding current. The turn off time tq of a
thyristor is defined as the time between the instant anode current becomes zero and the instant the
thyristor regains forward blocking capability. If forward voltage is applied across the device during this
period the thyristor turns on again. During turn off time, excess minority carriers from all the four layers
of the thyristor must be removed. Accordingly tq is divided in to two intervals, the reverse recovery time
(trr) and the gate recovery time (tqr). Fig 2.8 shows the variation of anode current and anode cathode
voltage with time during turn off operation on an expanded scale.
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Fig. 2.8: Turn off characteristics of a thyristor.

The anode current becomes zero at time t1 and starts growing in the negative direction with the same

till time t2. This negative current removes excess carriers from junctions J1 & J3. At time t2
excess carriers densities at these junctions are not sufficient to maintain the reverse current and the
anode current starts decreasing. The value of the anode current at time t2 is called the reverse recovery
current (Irr). The reverse anode current reduces to the level of reverse saturation current by t3. Total
charge removed from the junctions between t1 & t3 is called the reverse recovery charge (Qrr). Fast
decaying reverse current during the interval t2 t3 coupled with the limiting inductor may cause a
large reverse voltage spike (Vrr) to appear across the device. This voltage must be limited below the
VRRM rating of the device. Up to time t2 the voltage across the device (VAK) does not change
substantially from its on state value. However, after the reverse recovery time, the thyristor regains
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reverse blocking capacity and VAK starts following supply voltage vi. At the end of the reverse recovery
period (trr) trapped charges still exist at the junction J2 which prevents the device from blocking forward
voltage just after trr. These trapped charges are removed only by the process of recombination. The
time taken for this recombination process to complete (between t3 & t4) is called the gate recovery
time (tgr). The time interval tq = trr + tgr is called “device turn off time” of the thyristor.

No forward voltage should appear across the device before the time tq to avoid its inadvertentturn on.
A circuit designer must provide a time interval tc (tc > tq) during which a reverse voltageis applied across
the device. tc is called the “circuit turn off time”.

The reverse recovery charge Qrr is a function of the peak forward current before turn off and its rate of

decrease . Manufacturers usually provide plots of Qrr as a function of for different values of peak

forward current. They also provide the value of the reverse recovery current Irr for a given IA and .
Alternatively Irr can be evaluated from the given Qrr characteristics following similar relationships as in
the case of a diode.

As in the case of a diode the relative magnitudes of the time intervals t1 t2 and t2 t3 depends on the
construction of the thyristor. In normal recovery “converter grade” thyristor they are almost equal for a
specified forward current and reverse recovery current. However, in a fast recovery “inverter grade”
thyristor the interval t2 t3 is negligible compared to the interval t1 t2. This helps reduce the total turn
off time tq of the thyristor (and hence allow them to operate at higher switching frequency). However,
large voltage spike due to this “snappy recovery” will appear across the device after the device turns off.
Typical turn off times of converter and inverter grade thyristors are in the range of 50-100 μs and 5-50
μs respectively.

As has been mentioned in the introduction thyristor is the device of choice at the very highest power
levels. At these power levels (several hundreds of megawatts) reliability of the thyristor power converter
is of prime importance. Therefore, suitable protection arrangement must be made against possible
overvoltage, overcurrent and unintended turn on for each thyristor. At the highest power level (HVDC
transmission system) thyristor converters operate from network voltage levels in excess of several
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hundreds of kilo volts and conduct several tens of kilo amps of current. They usually employ a large
number of thyristors connected in series parallel combination. For maximum utilization of the device
capacity it is important that each device in this series parallel combination share the blocking voltage
and on state current equally. Special equalizing circuits are used for this purpose.

Thyristor ratings

Some useful specifications of a thyristor related to its steady state characteristics as found in a typical
“manufacturer’s data sheet” will be discussed in this section.

Voltage ratings

Peak Working Forward OFF state voltage (VDWM): It specifics the maximum forward (i.e,anode positive
with respect to the cathode) blocking state voltage that a thyristor can withstandduring working. It is
useful for calculating the maximum RMS voltage of the ac network inwhich the thyristor can be used. A
margin for 10% increase in the ac network voltage should be considered during calculation.

Peak repetitive off state forward voltage (VDRM): It refers to the peak forward transientvoltage that a
thyristor can block repeatedly in the OFF state. This rating is specified at amaximum allowable junction
temperature with gate circuit open or with a specified biasingresistance between gate and cathode. This
type of repetitive transient voltage may appear acrossa thyristor due to “commutation” of other
thyristors or diodes in a converter circuit.

Peak non-repetitive off state forward voltage (VDSM): It refers to the allowable peak value ofthe
forward transient voltage that does not repeat. This type of over voltage may be caused due toswitching
operation (i.e, circuit breaker opening or closing or lightning surge) in a supplynetwork. Its value is
about 130% of VDRM. However, VDSM is less than the forward break over voltage VBRF.

Peak working reverse voltage (VDWM): It is the maximum reverse voltage (i.e, anode negative with
respect to cathode) that a thyristor can with stand continuously. Normally, it is equal to the peak
negative value of the ac supply voltage.
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Peak repetitive reverse voltage (VRRM): It specifies the peak reverse transient voltage that may occur
repeatedly during reverse bias condition of the thyristor at the maximum junction temperature.

Peak non-repetitive reverse voltage (VRSM): It represents the peak value of the reverse transient
voltage that does not repeat. Its value is about 130% of VRRM. However, VRSM is less than reverse
break down voltage VBRR.

Fig 2.9 shows different thyristor voltage ratings on a comparative scale.

Fig. 2.9: Voltage ratings of a thyristor.

Current ratings

Maximum RMS current (Irms): Heating of the resistive elements of a thyristor such as metallic joints,
leads and interfaces depends on the forward RMS current Irms. RMS current rating is used as an upper
limit for dc as well as pulsed current waveforms. This limit should not be exceeded on a continuous
basis.

Maximum average current (Iav): It is the maximum allowable average value of the forward current such
that

i. Peak junction temperature is not exceeded

ii. RMS current limit is not exceeded

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Manufacturers usually provide the “forward average current derating characteristics” which shows Iav
as a function of the case temperature (Tc ) with the current conduction angle φ as a parameter. The
current wave form is assumed to be formed from a half cycle sine wave of power frequency as shown in
Fig 2.10.

Fig. 2.10: Average forward current derating characteristics

Maximum Surge current (ISM): It specifies the maximum allowable non repetitive current the device can
withstand. The device is assumed to be operating under rated blocking voltage, forward current and
junction temperation before the surge current occurs. Following the surge the device should be
disconnected from the circuit and allowed to cool down. Surge currents are assumed to be sine waves of
power frequency with a minimum duration of ½ cycles. Manufacturers provide at least three different
surge current ratings for different durations.
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Alternatively a plot of IsM vs. applicable cycle numbers may also be provided.

Maximum Squared Current integral : This rating in terms of A2S is a measure of the energy the
device can absorb for a short time (less than one half cycle of power frequency). This rating is used in
the choice of the protective fuse connected in series with the device.

Latching Current (IL): After Turn ON the gate pulse must be maintained until the anode current reaches
this level. Otherwise, upon removal of gate pulse, the device will turn off.

Holding Current (IH): The anode current must be reduced below this value to turn off the thyristor.

Maximum Forward voltage drop (VF): Usually specified as a function of the instantaneous forward
current at a given junction temperature.

Average power dissipation Pav): Specified as a function of the average forward current (Iav) for different
conduction angles as shown in the figure 2.11. The current wave form is assumed to be half cycle sine
wave (or square wave) for power frequency.
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Fig. 2.11: Average power dissipation vs average forward current in a thyristor.

In the above diagram

Gate Specifications

Gate current to trigger (IGT): Minimum value of the gate current below which reliable turn on of the
thyristor can not be guaranteed. Usually specified at a given forward break over voltage.

Gate voltage to trigger (VGT): Minimum value of the gate cathode forward voltage below which reliable
turn on of the thyristor can not be guaranteed. It is specified at the same break over voltage as IGT.

Non triggering gate voltage (VGNT): Maximum value of the gate-cathode voltage below which the
thyristor can be guaranteed to remain OFF. All spurious noise voltage in the gate drive circuit must be
below this level.
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Peak reverse gate voltage (VGRM): Maximum reverse voltage that can appear between the gate and the
cathode terminals without damaging the junction.

Average Gate Power dissipation (PGAR): Average power dissipated in the gate-cathode junction should
not exceed this value for gate current pulses wider than 100 μs.

Peak forward gate current (IGRM): The forward gate current should not exceed this limit even on
instantaneous basis.
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UNIT-III

Thyristors are semi controlled devices which can be turned ON by applying a current pulse at its gate
terminal at a desired instance. However, they cannot be turned off from the gate terminals. Therefore,
the fully controlled converter continues to exhibit load dependent output voltage / current waveforms
as in the case of their uncontrolled counterpart. However, since the thyristor can block forward voltage,
the output voltage / current magnitude can be controlled by controlling the turn on instants of the
thyristors. Working principle of thyristors based single phase fully controlled converters will be
explained first in the case of a single thyristor half wave rectifier circuit supplying an R or R-L load.
However, such converters are rarely used in practice.

Full bridge is the most popular configuration used with single phase fully controlled rectifiers. Analysis
and performance of this rectifier supplying an R-L-E load (which may represent a dc motor) will be
studied in detail in this lesson.

Single phase fully controlled half-wave rectifier(Resistive load)

Fig 3.1 single phase half wave fully controlled converter supplying R load
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Fig.3.1(a) shows the circuit diagram of a single phase fully controlled halfwave rectifier supplying a
purely resistive load. At ωt = 0 when the input supply voltage becomes positive the thyristor T becomes
forward biased. However, unlike a diode, it does not turn ON till a gate pulse is applied at ωt = α.
During the period 0 < ωt ≤ α, the thyristor blocks the supply voltage and the load voltage remains zero
as shown in fig 3.1(b). Consequently, no load current flows during this interval. As soon as a gate pulse
is applied to the thyristor at ωt = α it turns ON. The voltage across the thyristor collapses to almost zero
and the full supply voltage appears across the load. From this point onwards the load voltage follows
the supply voltage. The load being purely resistive the load current io is proportional to the load
voltage. At ωt = π as the supply voltage passes through the negative going zero crossing the load voltage
and hence the load current becomes zero and tries to reverse direction. In the process the thyristor
undergoes reverse recovery and starts blocking the negative supply voltage. Therefore, the load voltage
and the load current remains clamped at zero till the thyristor is fired again at ωt = 2π + α. The same
process repeats there after.

From the discussion above and Fig 3.1 (b) one can write
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Similar calculation can be done for i0. In particulars for pure resistive loads FFio = FFvo.

Resistive-Inductive load

Fig 3.2 (a) and (b) shows the circuit diagram and the waveforms of a single phase fully controlled half
wave rectifier supplying a resistive inductive load. Although this circuit is hardly used in practice its
analysis does provide useful insight into the operation of fully controlled rectifiers which will help to
appreciate the operation of single phase bridge converters to be discussed later.
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Fig 3.2 single phase half wave fully controlled converter supplying R-L load

As in the case of a resistive load, the thyristor T becomes forward biased when the supply voltage
becomes positive at ωt = 0. However, it does not start conduction until a gate pulse is applied at ωt = α.
As the thyristor turns ON at ωt = α the input voltage appears across the load and the load current starts
building up. However, unlike a resistive load, the load current does not become zero at ωt = π, instead it
continues to flow through the thyristor and the negative supply voltage appears across the load forcing
the load current to decrease. Finally, at ωt = β (β > π) the load current becomes zero and the thyristor
undergoes reverse recovery. From this point onwards the thyristor starts blocking the supply voltage
and the load voltage remains zero until the thyristor is turned ON again in the next cycle. It is to be
noted that the value of β depends on the load parameters. Therefore, unlike the resistive load the
average and RMS output voltage depends on the load parameters. Since the thyristors does not
conduct over the entire input supply cycle this mode of operation is called the “discontinuous
conduction mode”.
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However, IORMS can not be obtained from VORMS directly. For that a closed from expression for i0 will be
required. The value of β in terms of the circuit parameters can also be found from the expression of io.
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Equation of i0 can be used to find out IORMS. To find out β it is noted that

Above equation can be solved to find out β

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Single phase fully controlled bridge converter

Fig 3.3 single phase fully controlled bridge converter supplying RLE load (a) circuit diagram (b)
conduction table.

Fig 3.3 (a) shows the circuit diagram of a single phase fully controlled bridge converter. It is one of the
most popular converter circuits and is widely used in the speed control of separately excited dc
machines. Indeed, the R–L–E load shown in this figure may represent the electrical equivalent circuit of
a separately excited dc motor. The single phase fully controlled bridge converter is obtained by
replacing all the diode of the corresponding uncontrolled converter by thyristors. Thyristors T1 and T2
are fired together while T3 and T4 are fired 180º after T1 and T2. From the circuit diagram of Fig 10.3(a)
it is clear that for any load current to flow at least one thyristor from the top group (T1, T3) and one
thyristor from the bottom group (T2, T4) must conduct. It can also be argued that neither T1T3 nor T2T4
can conduct simultaneously. For example whenever T3 and T4 are in the forward blocking state and a
gate pulse is applied to them, they turn ON and at the same time a negative voltage is applied across T1
and T2 commutating them immediately. Similar argument holds for T1 and T2.

For the same reason T1T4 or T2T3 can not conduct simultaneously. Therefore, the only possible
conduction modes when the current i0 can flow are T1T2 and T3T4. Of coarse it is possible that at a
given moment none of the thyristors conduct. This situation will typically occur when the load current
becomes zero in between the firings of T1T2 and T3T4. Once the load current becomes zero all
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thyristors remain off. In this mode the load current remains zero. Consequently the converter is said to
be operating in the discontinuous conduction mode.

Fig 3.3(b) shows the voltage across different devices and the dc output voltage during each of these
conduction modes. It is to be noted that whenever T1 and T2 conducts, the voltage across T3 and T4
becomes –vi. Therefore T3 and T4 can be fired only when vi is negative i.e, over the negative half cycle
of the input supply voltage. Similarly T1 and T2 can be fired only over the positive half cycle of the input
supply. The voltage across the devices when none of the thyristors conduct depends on the off state
impedance of each device. The values listed in Fig 3.3 (b) assume identical devices.

Under normal operating condition of the converter the load current may or may not remain zero over
some interval of the input voltage cycle. If i0 is always greater than zero then the converter is said to be
operating in the continuous conduction mode. In this mode of operation of the converter T1T2 and
T3T4 conducts for alternate half cycle of the input supply. However, in the discontinuous conduction
mode none of the thyristors conduct over someportion of the input cycle. The load current remains
zero during that period.

Operation in the continuous conduction mode

As has been explained earlier in the continuous conduction mode of operation i0 never becomes zero,
therefore, either T1T2 or T3T4 conducts. Fig 3.4 shows the waveforms of different variables in the
steady state. The firing angle of the converter is α. The angle θ is given by

It is assumed that at t = 0-T3T4 was conducting. As T1T2 are fired at ωt = α they turn on commutating
T3T4 immediately. T3T4 are again fired at ωt = π + α. Till this point T1T2 conducts. The period of
conduction of different thyristors are pictorially depicted in the second waveform (also called the
conduction diagram) of Fig 3.4.
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Fig 3.4 Waveform of single phase fully controlled bridge converter in continuous conduction mode.
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The dc link voltage waveform shown next follows from this conduction diagram and the conduction
table shown in Fig 3.3(b). It is observed that the emf source E is greater than the dc link voltage till ωt =
α. Therefore, the load current i0 continues to fall till this point. However, as T1T2 are fired at this point
v0 becomes greater than E and i0 starts increasing through R-L and E. At ωt = π – θ v0 again equals E.
Depending upon the load circuit parameters io reaches its maximum at around this point and starts
falling afterwards. Continuous conduction mode will be possible only if i0 remains greater than zero till
T3T4 are fired at ωt = π + α where upon the same process repeats. The resulting i0 waveform is shown
below v0. The input ac current waveform ii is obtained from i0 by noting that whenever T1T2 conducts
ii = i0 and ii = - i0 whenever T3T4 conducts. The last waveform shows the typical voltage waveform
across the thyristor T1. It is to be noted that when the thyristor turns off at ωt = π + α a negative
voltage is applied across it for a duration of π – α. The thyristor must turn off during this interval for
successful operation of the converter.

It is noted that the dc voltage waveform is periodic over half the input cycle. Therefore, it can be
expressed in a Fourier series as follows.
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Fourier series expression of v0 is important because it provides a simple method of estimating individual
and total RMS harmonic current injected into the load as follows:

The impedance offered by the load at nth harmonic frequency is given by

From above equations it can be argued that in an inductive circuit IonRMS → 0 as fast as 1/n2. So

in practice it will be sufficient to consider only first few harmonics to obtain a reasonably accurate
estimate of IOHRMS. This method will be useful, for example, while calculating the required current
derating of a dc motor to be used with such a converter.

However to obtain the current rating of the device to be used it is necessary to find out a closed form
expression of i0. This will also help to establish the condition under which the converter will operate in
the continuous conduction mode.

To begin with we observe that the voltage waveform and hence the current waveform is periodic over
an interval π. Therefore, finding out an expression for i0 over any interval of length π will be sufficient.
We choose the interval α ≤ ωt ≤ π + α.
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Now at steady state since i0 is periodic over the chosen interval. Using this boundary
condition we obtain

Fig 3.5 shows the waveform of ii in relation to the vi waveform.

Fig 3.5 the input current and its fundamental component

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It will be of interest to find out a Fourier series expression of ii. However, using actual expression for ii
will lead to exceedingly complex calculation. Significant simplification can be made by replacing i0 with
its average value I0. This will be justified provided the load is highly inductive and the ripple on i0 is
negligible compared to I0. Under this assumption the idealized waveform of ii becomes a square wave
with transitions at ωt = α and ωt = α + π as shown in Fig 3.5. ii1 is the fundamental component of this
idealized ii. Evidently the input current displacement factor defined as the cosine of the angle between
input voltage (vi) and the fundamental component of input current (ii1) waveforms is cosα (lagging).

It can be shown that

Therefore, the rectifier appears as a lagging power factor load to the input ac system. Larger the ‘α’
poorer is the power factor. The input current ii also contain significant amount of harmonic current (3rd,
5th, etc) and therefore appears as a harmonic source to the utility. Exact composition of the harmonic
currents can be obtained by Fourier series analysis of ii and is left as an exercise.

Operation in the discontinuous conduction mode

So far we have assumed that the converter operates in continuous conduction mode without paying
attention to the load condition required for it. In figure 10.4 the voltage across the R and L component
of the load is negative in the region π - θ ≤ ωt ≤ π + α. Therefore i0 continues to decrease till a new pair
of thyristor is fired at ωt = π + α. Now if the value of R, L and E are such that i0 becomes zero before ωt
= π + α the conduction becomes discontinuous. Obviously then, at the boundary between continuous
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and discontinuous conduction the minimum value of i0 which occurs at ωt = α and ωt = π + α will be
zero. Putting this condition in (3.26) we obtain the condition for continuous conduction as.

Fig 3.6 shows waveforms of different variables on the boundary between continuous and discontinuous
conduction modes and in the discontinuous conduction mode. It should be stressed that on the
boundary between continuous and discontinuous conduction modes the load current is still continuous.
Therefore, all the analysis of continuous conduction mode applies to this case as well. However in the
discontinuous conduction mode i0 remains zero for certain interval. During this interval none of the
thyristors conduct. These intervals are shown by hatched lines in the conduction diagram of Fig 3.6(b).
In this conduction mode i0 starts rising from zero as T1T2 are fired at ωt = α. The load current continues
to increase till ωt = π – θ. After this, the output voltage v0 falls below the emf E and i0 decreases till ωt
= β when it becomes zero. Since the thyristors cannot conduct current in the reverse direction i0
remains at zero till ωt = π + α when T3 and T4 are fired. During the period β ≤ ωt ≤ π + α none of the
thyristors conduct. During this period v0 attains the value E.
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Performance of the rectifier such as VOAV, VORMS, IOAV, IORMS etc can be found in terms of α, β and θ. For
example
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It is observed that the performance of the converter is strongly affected by the value of β. The value of β
in terms of the load parameters (i.e, θ, φ and Z) and α can be found as follows.

Given φ, α and θ, the value of β can be found by solving above equation

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Operating principle of 3 phase fully controlled bridge converter

A three phase fully controlled converter is obtained by replacing all the six diodes of an uncontrolled
converter by six thyristors as shown in Fig. 3.7 (a)

For any current to flow in the load at least one device from the top group (T1, T3, T5) and one from the
bottom group (T2, T4, T6) must conduct. It can be argued as in the case of an uncontrolled converter
only one device from these two groups will conduct.

Then from symmetry consideration it can be argued that each thyristor conducts for 120° of the input
cycle. Now the thyristors are fired in the sequence T1 → T2 → T3 → T4 → T5 → T6 → T1 with 60°
interval between each firing. Therefore thyristors on the same phase leg are fired at an interval of 180°
and hence can not conduct simultaneously. This leaves only six possible conduction mode for the
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converter in the continuous conduction mode of operation. These are T1T2, T2T3, T3T4, T4T5, T5T6,
T6T1. Each conduction mode is of 60° duration and appears in the sequence mentioned. The
conduction table of Fig. 3.7 (b) shows voltage across different devices and the dc output voltage for
each conduction interval. The phasor diagram of the line voltages appear in Fig. 3.7 (c). Each of these
line voltages can be associated with the firing of a thyristor with the help of the conduction table-1. For
example the thyristor T1 is fired at the end of T5T6 conduction interval. During this period the voltage
across T1 was vac. Therefore T1 is fired α angle after the positive going zero crossing of vac. Similar
observation can be made about other thyristors. The phasor diagram of Fig. 3.7 (c) also confirms that all
the thyristors are fired in the correct sequence with 60° interval between each firing.

Fig. 3.8 shows the waveforms of different variables (shown in Fig. 3.7 (a)). To arrive at the waveforms it
is necessary to draw the conduction diagram which shows the interval of conduction for each thyristor
and can be drawn with the help of the phasor diagram of fig. 3.7 (c). If the converter firing angle is α
each thyristor is fired “α” angle after the positive going zero crossing of the line voltage with which it’s
firing is associated. Once the conduction diagram is drawn all other voltage waveforms can be drawn
from the line voltage waveforms and from the conduction table of fig. 3.7 (b). Similarly line currents can
be drawn from the output current and the conduction diagram. It is clear from the waveforms that
output voltage and current waveforms are periodic over one sixth of the input cycle. Therefore this
converter is also called the “six pulse” converter. The input current on the other hand contains only
odds harmonics of the input frequency other than the triplex (3rd, 9th etc.) harmonics. The next section
will analyze the operation of this converter in more details.
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Fig. 3.8

Analysis of the converter in the rectifier mode

The output voltage waveform can be written as

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The input phase current ia is expressed as

From Fig. 3.8 it can be observed that i0 itself has a ripple at a frequency six times the input frequency.
The closed from expression of i0, as will be seen later is some what complicated However, considerable
simplification in the expression of ia can be obtained if i0 is replaced by its average value I0. This
approximation will be valid provided the ripple on i0 is small, i.e, the load is highly inductive. The
modified input current waveform will then be ia which can be expressed in terms of a Fourier series as
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From fig 3.8

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From fig 3.8

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To find out the condition for continuous conduction it is noted that in the limiting case of continuous
conduction.

then i0 is minimum at ωt = α. ∴ Condition for continuous conduction is

. However discontinuous conduction is rare in these conversions and will not be discussed
any further.

Higher pulse number converters and dual converter

The three phase fully controlled converter is widely used in the medium to moderately high power
applications. However in very large power applications (such as HV DC transmission systems) the device
ratings become impractically large. Also the relatively low frequency (6th in the dc side, 5th and 7th in
the ac side) harmonic voltages and currents produced by this converter become unacceptable.
Therefore several such converters are connected in series parallel combination in order to increase the
voltage / current rating of the resulting converter. Furthermore if the component converters are
controlled properly some lower order harmonics can be eliminated both from the input and output
resulting in a higher pulse converter.
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Fig 3.9

Fig. 3.9(a) schematically represents series connection of two six pulse converters where as Fig. 3.9(b)
can be considered to be a parallel connection. The inductance in between the converters has been
included to limit circulating harmonic current. In both these figures CONV – I and CONV – II have
identical construction and are also fired at the same firing angle α. Their input supplies also have same
magnitude but displaced in phase by an angle φ. Then one can write
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Therefore for Fig 3.9(a)

Now if cos 3Kφ = 0 for some K then the corresponding harmonic disappear from the fourier series
expression of v0.

In particular if φ = 30° then cos 3Kφ = 0 for K = 1, 2, 3, 5……. This phase difference can be obtained by
the arrangement shown in Fig. 3.9(c).

It can be seen that the frequency of the harmonics present in the output voltage has the form

12ω, 24ω, 36ω ………..

Similarly it can be shown that the input side line current iABC have harmonic frequency of the form

11ω, 13ω, 23ω, 25ω, 35ω, 37ω, ………….

Which is the characteristic of a 12 pulse converter.

In a similar manner more number of 3 phase 6 pulse converters can be connected in series / parallel and
the φ angle can be adjusted to obtain 18 and 24 pulse converters.
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One of the shortcomings of a three phase fully controlled converter is that although it can produce both
positive and negative voltage it can not supply current in both directions. However, some applications
such as a four quadrant dc motor drive require this capability from the dc source. This problem is easily
mitigated by connecting another three phase fully controlled converter in anti parallel as shown in Fig.
3.10 (a). In this figure converter-I supplies positive load current while converter-II supplies negative load
current. In other words converter-I operates in the first and fourth quadrant of the output v – i plane
whereas converter-II operates in the third and fourth quadrant. Thus the two converters taken
together can operate in all four quadrants and is capable of supplying a four quadrant dc motor drive.
The combined converter is called the Dual converter.

Fig 3.10
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Obviously since converter-I and converter-II are connected in anti parallel they must produce the same
dc voltage. This requires that the firing angles of these two converters be related as

α2 = π – α1

Although above Equations ensures that the dc voltages produced by these converters are equal the
output voltages do not match on an instantaneous basis. Therefore to avoid a direct short circuit
between two different supply lines the two converters must never be gated simultaneously. Converter-I
receives gate pulses when the load current is positive. Gate pulses to converter-II are blocked at that
time. For negative load current converter-II thrusters are fired while converter-I gate pulses are
blocked. Thus there is no circulating current flowing through the converters and therefore it is called
the non-circulating current type dual converter. It requires precise sensing of the zero crossing of the
output current which may pose a problem particularly at light load due to possible discontinuous
conduction. To overcome this problem an inter phase reactor may be incorporated between the two
converters. With the inter phase reactor in place both the converters can be gated simultaneously with
α2 = π – α1. The resulting converter is called the circulating current type dual converter.