DEPARTMENT

OF
ELECTRONICS & COMMUNICATION ENGINEERING

ECE 452 – VHDL and CAD LAB

LABORATORY MANUAL

R.V.R. & J.C. COLLEGE OF ENGINEERING

(Approved by AICTE)
(Affiliated to Nagajuna University)
CHANDRAMOULIPURAM::CHOWDAVARAM
GUNTUR – 522 019
CONTENTS

VHDL modeling and Synthesis of the following Experiments

1. Logic Gates
2. Modulo-N Synchronous/Asynchronous up down Counters
3. Multiplexers/De- Multiplexers
4. Design of ALU
5. 8 to 3 Priority Encoder/ BCD to 7 Segment Decoder
6. 4 bit Magnitude Comparator
7. Parity Generator
OBJECTIVES

Active-VHDL is an integrated environment designed for development of VHDL designs. The

core of the system is a VHDL simulator. Along with debugging and design entry tools, it makes
up a complete self-sufficient system that allows you to write, debug and simulate VHDL code.
Based on the concept of a design, Active-VHDL allows you to organize your VHDL resources
into a convenient and clear structure.

Standards Supported

VHDL

The VHDL simulator implemented in Active-VHDL supports the VHDL-93 language standard.
Some language constructs are not supported in this release.

VITAL

The simulator provides built-in acceleration for VITAL packages version 3.0. The VITAL-
compliant models can be annotated with timing data from SDF files. SDF files must comply with
OVI Standard Delay Format Specification Version 2.1.

AVHDL Command Language

All operations in Active-VHDL can be performed using Active-VHDL command language.

Active-VHDL accepts all commands used by Model Technology V-System ™. The commands
that are inapplicable or not supported in the Active-VHDL environment are also accepted but
have no effect on the operation of the application.

Hardware and Software Requirements

Active-VHDL requires:

· A Pentium PC

· 32 MB physical memory (64 MB recommended)

· Microsoft Windows 95 or Windows NT 4.0 with Service Pack 3 for Windows NT 4.0

· A hard disk drive with at least 100 MB spare capacity (for full installation)
Active-VHDL Components

All Active-VHDL components are embedded into a unified graphical environment referred to as
framework. The framework provides workspace and is a communication environment for all
system components. Except for the simulation kernel, each Active-VHDL tool is implemented in
a separate window. The following is a brief description of Active-VHDL components:

Tool Description

Console The Console window is an interactive input-output text device that:

· Provides entry for Active-VHDL commands.
· Outputs messages generated by Active-VHDL tools.

Design Browser The Design Browser window displays the current design contents, that is:
· Resource files attached to the design.
· The contents of the default working library of the design.
·The structure of the design unit selected for simulation.
·Signals and variables declared within a selected region of the current design.

HDL Editor The HDL Editor is a text editor designed for VHDL source files. It displays
specific syntax categories in different colors. The editor is tightly integrated with the simulator to
enable debugging source code.

Language Assistant The Language Assistant is an auxiliary tool that provides a number of
VHDL templates modeling typical logic primitives and functional blocks. It is integrated with
the HDL Editor so that you can automatically insert desired templates into edited source files.
Language Assistant allows you to define your own templates.

State Editor The State Editor is a graphical tool designed to edit state machine diagrams. The
editor implements automatic translation of graphically designed diagrams into VHDL code.

Waveform Editor The Waveform Editor displays the results of a simulation run as signal
waveforms. It allows you to graphically edit waveforms so as to create desired test vectors.

List The List window displays the results of a simulation run in a tabled text form. It allows
you to trace simulation results with delta-cycle accuracy.

Watch The Watch window displays the current values of selected signals and variables during
simulation.

Processes The Processes window displays the current status of concurrent processes in the
elaborated design during simulation.

Library Manager The Library Manager is designed to manage VHDL libraries and their
contents.
Design Explorer The Design Explorer facilitates management of Active-VHDL designs so
that you do not have to worry about physical locations of design files on your computer.

Script Editor The Script Editor is a text editor with built-in debugger designed for editing of
VBA basic scripts implementing Active-VHDL commands.

Active-VHDL Command Language

All operations performed by Active-VHDL can be initiated either from the user interface or by
execution of Active-VHDL commands. The commands must be entered in the Console window.
The Console window supports batch processing, which means you can execute macro files
containing sequences of Active-VHDL commands. The syntax of the Active-VHDL command
language is compatible with that implemented in the Model Technology V-System™. This
allows you to run macros created originally for the V-System™. The V-System™ commands
that are inapplicable or not supported in the Active-VHDL environment are also accepted but
have no effect on the operation of the program.

To execute a macro command, you should enter it in the Console window along with required
parameters (if any). To execute a macro file, enter the do command with the macro file name as a
parameter. Note that the do command can appear within another macro file, which allows you to
nest macros.
Using Active-VHDL

Compilation:

Compilation is a process of analysis of a source file(s).

Order of Analysis

Sequence in which source files attached to a design are compiled does matter. Rules presented
here are consequences of the visibility rules imposed by VHDL.

· A primary design unit must be compiled prior to the compilation of any corresponding
secondary unit. For example, an entity declaration should be compiled prior to the compilation of
its architecture bodies.

· A primary unit whose name is referenced within a given design unit must be compiled
prior to the compilation of the given design unit. For example an entity (and its architecture
bodies) used as a component in another architecture body should be compiled prior to the
compilation of this architecture body.

In each case, the second unit depends on the first unit. If these rules are not obeyed during
compilation, the compiler will warn you of violations of the dependence rules. The elaboration of
a model in the simulator will fail if the dependence rules were violated during the compilation of
components of the elaborated model.

Each design in Active-VHDL has its default working library. The library has the same name as
the design. If you do not specify a different working library for a given file, its contents will be
compiled into the default working library.

Compilation Methods

Active-VHDL allows you to compile design source files in several manners:

Source files can be compiled individually. Menu command: Design /Compile

All source files can be compiled in one go. In such case, the files are compiled in the order they
appear on the Files tab of the Design Browser window (from the uppermost to the
lowermost).Menu command: Design /Compile All

All source files can be compiled in one go with prior reorder. The files are reordered so as to
ensure the proper order of analysis. Menu command: Design /Compile All with File Reorder
Designs

What is a Design?

Active-VHDL allows your design resource files (source files, output files with simulation results,
etc.) to be organized into named collections called designs. A design comprises the following
data:

· Source files, state diagram files, test bench files, log files, output files (with simulation results)
and other documents attached to the design by the user.

· Default working library of the design.

· Configuration data defining the current layout of the framework workspace.

· Project description file (with default extension ADF).

All the design data files mentioned above are normally stored in a common directory referred to
as a design directory. The name of a design is determined by the name of a project description
file. As Active-VHDL supports long file names, the limitation on design names are the same as
those pertaining to long file names. Note that a design can include files from outside the design
directory – project description files stores file paths to such externally located documents.

When you start Active-VHDL, you have to choose a design you will be working on. You always
work with one design at a time. Of course, during a session with Active-VHDL, you can change
designs. When you open a design, Active-VHDL restores the layout of the user interface as it has
been set during the last session with the design.

Design Libraries

The simulator does not simulate the VHDL source code directly. A design entity you are going
to simulate must be compiled into a design library first. Only the data stored in a design library
after errorless compilation can be read by the simulator.

There are two classes of design libraries: working libraries and resource libraries. A working
library is the library into which the library units resulting from the analysis of a source file are
placed. A resource library is a library containing library units that are referenced within the
source file being analyzed. Only one library may be the working library during the analysis of a
source file; in contrast, any number of libraries (including the working library itself) may be
resource libraries during such an analysis.

Logical names of resource libraries are listed in the library clause preceding a design unit in
source code. For example, the following statement:
library IEEE,PRIMITIVES;

makes all design units residing in libraries IEEE and PRIMITIVE visible to the design unit that
follows the statement. In addition, each design unit is assumed to be preceded by the following
implicit statements, even if they do not appear in source code:

library STD, WORK;

use STD. STANDARD.all;

The first statement makes visible design units residing in the standard library STD and in the
working library. The logical name WORK always denotes the working library, that is, the library
into which the source file is currently being compiled, irrespective of the actual logical name of
this library. The second statement makes all declarations in the package STANDARD visible.

Example

Assume the file Simple.vhd, which is compiled into the library TEST, contains the following
code:

library IEEE, PRIMITIVES;

use WORK.GLOBAL_SIGNALS.all;
use PRIMITIVES.GATES.all;

entity CELL_X is
...
end entity CELL_X;

Standard Libraries

Active-VHDL comes with a set of standard VHDL libraries. Apart from the libraries describing
the predefined language environment (library STD with packages STANDARD and TEXTIO),
provided are libraries supporting STD_LOGIC_1164 multi-value logic system and vendor-
specific libraries. All the standard libraries are stored in the VHDL directory located within the
Active-VHDL installation directory.

Overview of Library Structure

VHDL defines a library as an implementation-dependent storage facility for previously analyzed

design units. An implementation must provide a mechanism to associate a library logical name
with the library data stored physically on the system. The logical name is the one used to
reference a library in the source code. For example, the following library clause:

library XCL;
makes all the library units contained in the XCL library visible to the design unit following the
clause. The user does not have to know how the XCL library is physically stored on the disk.

In Active-VHDL, each design library consists of two files:

· The library index file (with extension LIB), which contains information about library
units stored in a library.

· The library data file (with extension MGF), which contains pre-elaborated code resulting
from the analysis of source code.

Simulation

Initialization of Simulation

Once you have successfully compiled all needed design units, you can launch simulation. The
three steps that precede the actual simulation are:

· Selection of the top-level design unit

· Elaboration

· Initialization

First, you have to select a library unit that will be used to build the simulation model. You can
specify either directly an entity-architecture pair or a configuration. In case of hierarchical
models, in which the top-level entity instantiates another entities, the simulator automatically
loads additional design entities following the default binding indication rules (see LRM, section
5.5.2) or explicit binding indication specified in a configuration (if you have chosen to load a
configuration).

To select the top-level design unit, use Design Browser. If no unit has been selected and you run
the simulator anyway, it will prompt you in a dialog box to select the top-level unit.

The Initialize Simulation command in the Simulation menu launches elaboration and
initialization of the simulation model. During elaboration, the simulator loads design entities and
builds the simulation model in the computer memory. During the initialization, all objects in the
model (signals, variables, etc.) acquire their initial values (either default or explicitly specified)
and all concurrent processes are executed once until their suspension.
Continuous Simulation

There are three ways to perform continuous simulation:

The Simulation /Run command runs simulation for an unspecified amount of time. The
simulation ends when either of these conditions is met:· The current simulation time equals
TIME’HIGH.· No events nor resumption of any process are scheduled.
The Simulation /Run For command advances simulation by a specified time step.
The Simulation /Run Until command advances simulation until a specified time point.
In each of the above cases, you can break the simulation using the Stop command or by clicking .
Active-VHDL provides the following tools to observe the simulation results:

· Watch window

· Waveform window

· List window

Ending and Restarting Simulation

After you have simulated your design, you should end the simulation. The Simulation /End
Simulation menu command releases memory space occupied by the model and disables the
simulator.
If you want to repeat simulation, you do not have to reload the simulation model into the
simulator. Instead, you should reinitialize the simulation model using the Simulation /Restart
Simulation menu command or by clicking .

Debugging VHDL Code - Overview

Active-VHDL provides several mechanisms for debugging VHDL code. You can:

· Execute the VHDL code of a model statement-by-statement (step simulation).

· Set code breakpoints.

· Set signal breakpoints.