Logic Synthesis and Optimization VLSI User’s Manual

Chapter 7 Logic Synthesis and Optimization

Typically, the sequence of well-defined steps used to synthesize a system’s behavioural description in a
Hardware Description Language into a gate-level design targeting a specific technology design-kit would
be run from a script of commands that have been saved to a text file. In this chapter, we illustrate many of
the steps used during synthesis by demonstrating them using a graphical user interface or command-line
entry to the Synopsys Design Compiler. These steps will be recorded in a file in your work directory, so
you may edit this and customize it as required for other projects. The example we will work through here
and in the next chapter will use the TSMC CMOSP18 process technology and the Artisan 3.0 libraries for
this technology, but where possible we will describe the set-up for the TSMC CMOSP35 technology as
well.

7.1 Available libraries

When synthesizing a design from a behavioural (or other high-level) representation of a system, we need to
target a specific technology, with libraries of building blocks that have been designed to be fabricated using
that technology. The synthesis programs read information from library files and can select appropriate

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replacements for “generic” building blocks. These libraries can include all of the mask data for all of the
cells in the library, but more often when we use commercially designed libraries we see only a “black-box”
representation of the library cells, so named because the layout, extracted and schematic views are not
available to designers; the details within the cells is hidden from view. This makes it impossible to reverse-
engineer, but it also makes it difficult for designers to examine a completed design. The black-box library
information, often in the form of an abstract view, provides sufficient information about the cells contents
(pin locations, metal levels required for connecting to the pins, and blockages or “keep-out” regions indi-
cating areas where over-the-cell routing is prohibited) for the automated synthesis and place-and-route
tools to help you prepare designs that are physically correct: the completed designs should violate no
design rules, and all timing constraints will be satisfied. In some cases the library information will provide
simulatable transistor-level netlists of all library cells, but for advanced technologies this information will
be missing.

7.1.1 CMOSP18

The CMOSP18 technology distributed by CMC only contains older black-box libraries for standard cells
and the I/O pads. In the examples worked in this chapter we will use a newer set of commercially available
black-box libraries known as the Artisan version 3.0 standard cell and I/O libraries.

7.1.2 CMOSP35

In the CMOSP35 technology distributed by CMC, two sets of standard cell libraries are available: wcells
and the black-box libraries (tcb773pwc and tpd773pnwc). The wcells library was developed at CMC, while
the black-box libraries are commercial libraries. The default technology library path for Synopsys is set to
access the wcells library. If you wish to use the black-box libraries, you will need to make appropriate
changes in the .synopsys_dc.setup file mentioned below for this technology.

7.2 Environment Settings

Access to the Synopsys Design Analyzer, used for synthesis and optimization, requires that you
% source /CMC/tools/CSHRCs/Synopsys

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 VLSI User’s Manual Logic Synthesis and Optimization

The graphical user interface, design_analyzer, and the scripting interface, dc_shell, both require two tech-
nology-specific set-up files in your work directory. To set these up, you can copy the appropriate set-up
files depending on your technology choice. (Note the space followed by a ‘.’ at the end of all of the “cp”
commands.)

CMOSP18: % cp /CMC/kits/VRGlocal/demo/synopsys/.synopsys_dc.setup .
% cp /CMC/kits/VRGlocal/demo/synopsys/.synopsys_vss.setup .
CMOSP35: % cp /CMC/kits/cmosp35/synopsys/dotfiles/.synopsys_dc.setup .
% cp /CMC/kits/cmosp35/synopsys/dotfiles/.synopsys_vss.setup .

In addition, you will need to create a directory named “Work” to hold intermediate files:
% mkdir ./Work

7.3 Starting design_analyzer

1. Invoke the graphical user interface to the synthesis program using
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% design_analyzer &

2. Select Setup→Defaults... to bring up the Defaults dialog window.

a. Feel free to fill in the Designer and Company fields.
b. The Search Path specifies a list of filesystem paths that design_analyzer will search for any
design files required for synthesizing the design. It is filled in using technology-specific filesys-
tem paths indicated in your .synopsys_dc.setup file. If you have your design files in
other locations, you can add these to this field.
c. The Link Library field specifies the names of libraries that will be linked to your design.
d. The default values in other fields should be fine. Click OK to continue.
Note: Environmental settings are per session settings, you will need to re-enter them every time
you start Design Compiler. To make the respective settings default for all future sessions, edit
your .synopsys_dc.setup file instead.

3. Select File→Read... and select your design files from the drop-down list. A log window echoing
load messages will appear. Notice the icon at the center of the Design Analyzer window. The
expression inside the box indicates that the design has not yet been compiled to a gate level netlist.

4. For a design that consists of multiple files, read in each file, one at a time. Then select the top level
module in the Design Analyzer window and select Analysis→Link Design...

5. After loading all necessary HDL files, it is wise to check the design for errors that might have not
become apparent during simulation before synthesis. Select Analysis→Check Design and con-
firm the default check settings. A return value of ‘1’ indicates that the were no warnings or errors
in the design.

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Logic Synthesis and Optimization VLSI User’s Manual

7.4 Explore the Design Hierarchy

You can, at any time, explore your design hierarchy in Design Analyzer by selecting various modules in
your design and using the short-cut buttons shown on the left side of the window. From the top, the icons
represent
• Designs view: indicates the designs that have been loaded into memory.
• Symbol view: shows a symbolic representation of the design, including input and output ports.
Attributes (showing design-specific information such as the arrival times and strengths of input sig-
nals), and constraints (design-specific requirements or goals for the optimizer such as the maximum
circuit area or the maximum signal propagation time through the circuit to one or more outputs) may
be set while viewing this representation.
• Schematic view: shows the composition of the design. Components may be gates or subdesigns.
• Text view: This is disabled in this version of the design_analyzer.

The next two icons allow you to move up or down in the design hierarchy.

7.5 Prepare the Design for Synthesis

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Before synthesizing the design, specify any attributes or constraints for your design:

7.5.1 Specify clock pin and signal

If your design includes a clock signal:

1. Select the top level module in your design hierarchy. Display its symbol view.

2. Select the pin corresponding to the clock pin.

3. Select Attributes→Clocks→Specify, which will bring up the Specify Clock dialog window.

4. Ensure that the Don’t Touch Network check-box is checked. This will prevent Design Analyzer
from optimizing the clock tree by inserting buffers; buffers will be inserted using a different tool,
during the floor planning, placement, and routing.

5. Specify the Period of the clock, in nanoseconds, and specify the position of the positive Edge, also
in nanoseconds.

6. Click Apply to apply the settings, notice that your clock pin now has a red square wave signal.
Click Cancel to close the Specify Clock dialog window.

7.5.2 Specify operating environment: input drive strength and output loading

Ideal circuits may have their inputs driven strongly, and no output loading. Real world circuitry should be
synthesized with more-realistic values. You can specify the input drive strength:

1. Select the top level module in your design, and drop down into its symbol view.

2. Select an input pin, then

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 VLSI User’s Manual Logic Synthesis and Optimization

• Select Attributes→Operating Environment→Drive Strength...

• In the Drive Strength dialog window, turn on Same Rise and Fall and specify a Rise Strength
of 30. This value is measured in delay (ns) per load (pF); the drive strength increases as the
value approaches 0.
• Click Apply and then Cancel.
Note: If several pins will have the same drive strength, you can select multiple pins by SHIFT-
left-clicking on all of the similar pins before specifying the Drive Strength and clicking Apply.

The load on an output pin will impact the timing of the pin. Therefore, it is a good idea to provide the syn-
thesis tool with an estimated capacitive load each output pin will experience after manufacturing. To spec-
ify the load on an output pin:

1. Select the top level module in your design, and drop down into its symbol view.

2. Select each output pin, one at a time, and perform the following
• Select Attributes→Operating Environment→Load, which will bring up the Load dialog
window.
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• Specify the expected Capacitive Load on the pin in pF

• Click Apply to apply the capacitive value to the selected output port.
• With the Load dialog window still open, you can select another output pin on your schematic,
and specify its output load as well, by specifying the estimated Capacitive Load and then
clicking Apply
• When completed, click Cancel to close the Load dialog window.
Note: If several pins will have the same load, you can select multiple pins by SHIFT-left-click-
ing on all of the similar pins before specifying the Load and clicking Apply.

7.5.3 Specify area constraints

1. Select the top level module in your design hierarchy.

2. Select Attributes→Optimization Constraints→Design Constraints. The Design Constraints

dialog window will appear.

3. Set the Max Area field to 0. This will force Design Compiler to optimize the design for the small-
est silicon area.

4. Click Apply to confirm the settings, and then Cancel to close the dialog window.
Note: On some versions of design_analyzer, this command fails with an error related to fault
coverage, due to a problem with one of the installed scripts. To avoid this error, you can type
this command instead, into the bottom line of the Command Window:
set_max_area 0

7.5.4 Specify timing constraints

1. Select the top level module in your design hierarchy.

2. Double-click on your top-level module to descend into its symbolic or schematic view.

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Logic Synthesis and Optimization VLSI User’s Manual

3. Select Attributes→Optimization Constraints→Timing Constraints. The Timing Constraints

dialog window will appear.

4. Make sure the check box for Same Rise and Fall is selected.

5. Specify the Maximum Delay to be 0. This will force Design Compiler to optimize the design for
the fastest possible path delay, and hence clock frequency.

6. Click Apply to confirm the settings, and then Cancel to close the dialog window.

7.5.5 Conflicting optimization goals

We have just specified potentially conflicting optimization goals: a minimum size circuit with a maximum
clock frequency. By default, Design Compiler tries to satisfy these goals by optimizing for timing, then
design area. If you’d like to change the default optimization goal priorities, refer to the on-line documenta-
tion.

7.5.6 Multiple use of sub blocks

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If you call a sub-block more than once in the top level of a design, the Design Compiler will ask you to
execute the uniquify command (Edit→Uniquify→Hierarchy) before synthesizing the design. If you run
this command, Design Compiler will generate independent blocks, each with a unique suffix. Each block
will then be optimized individually. For example, if you use a full adder block, FA, several times in a mul-
tiplier design, the uniquify command will generate a set of individual full adders with names FA1, FA2, etc.

7.6 Synthesize your design

1. Select Tools→Design Optimization... which will bring up the Design Optimization dialog win-
dow.

2. Select the desired Map Effort. A high mapping effort will specify that Design Compiler should
spend more time trying to meet the specified design optimization goals.

3. Do not select Verify Design. In theory, this option performs automatic RTL versus gate level design
comparison. However, it takes an extremely long time, especially at higher Verify Effort settings.

4. Click OK to begin the optimization. As the optimization progresses, the Command Window will
be updated with the synthesis progress.

When selected, Boundary Optimization allows Design Compiler to make logic and gate level optimizations
across module boundaries. If this option is not checked, each module will be optimized irrespective of
what it is connected to, or what modules it contains inside. However, boundary optimizations might change
the pin-outs of some modules. Refer to the on-line documentation before using Boundary Optimization,
especially when using external black-box modules, such as memories or black-box standard-cell libraries.

7.6.1 Evaluate optimized results

1. Select the top-level module.

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 VLSI User’s Manual Logic Synthesis and Optimization

2. Select Analysis→Report, which will bring up the Report dialog window.

3. Select the check-boxes corresponding to the information you would like the report to provide, such
as Constraints, Area and Timing.

4. Click Apply to have Design Analyzer generate a report.

The report will provide you with information such as what the design constraints where, and whether they
have been met. Other information, such as the longest path (critical path) in your design is provided as
well. To see the critical path in your design, bring up the schematic view of your design and select
Analysis→Highlight→Critical Path.

At this point, you can save your design as converter_gates.v or converter_gates.vhd

A script is available in /CMC/kits/VRGlocal/demo/synopsys/converter_build.script

which contains directives which, when run using Setup→Execute Script... will build these two files.

7.7 Testability
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At this stage of the design, we are ready to add some features to the design which will be useful after our
chip has been fabricated, packaged, and returned to us for testing. At this time, these features are beyond
the scope of this manual.

If you wish to investigate these for your own projects, some Design For Test Tools are available here from
Mentor. To access these, you may
% source /CMC/tools/CSHRCs/dft

Some of the tools available include

• dftadvisor: for Scan Chain Insertion:
• fastscan: for Automatic Test Pattern Generation

Some sample files for this design are available in /CMC/kits/VRGlocal/demo/dft/

7.8 Adding Input and Output Pads

The digital logic on your microchip will inevitably have to communicate with the outside world. This com-
munication is facilitated via buffers and pads, which could include high current inverters with over-voltage
or electrostatic discharge diode (ESD) protection. Information about the types of pads provided for the
CMOSP18 technology is provided in the file
/CMC/kits/artisan.3.0/FE/doc/

Information about the types of pads provided for the CMOSP35 technology is provided in
/CMC/kits/cmosp35/doc/blackbox/tpz773pn_150a/tpz773pntc/html/index.html

Pads can be manually inserted into your HDL code before synthesis, by using the appropriate model name
for the pad. Alternatively, if the libraries are set up correctly, you can utilize the automatic pad insertion

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Logic Synthesis and Optimization VLSI User’s Manual

capabilities provided by Design Analyzer. However, for either case, you will still need to specify an esti-
mate of the expected output load for each output pin.
Note: Automatic pad insertion can cause weird synthesis results when an output pin serves as
input to internal logic as well. One way to avoid this is to avoid the use of register type signals
as outputs, see Fig. 7.1 and Fig. 7.2 for example code illustrating proper use of registered sig-
nals as outputs.

//This style will cause pad insertion problems

module bad ( clock, reset, out );
input clock, reset;
output out;
reg out;

always @(posedge clock) begin

...
out <= ... // f(out)
...
end
endmodule;

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Figure 7.1: Bad Style of Coding for Pad Insertion

//This style will not cause pad insertion problems

module good ( clock, reset, out );
input clock, reset;
output out;
reg insideRegister; // New!

assign out = insideRegister; // New!

always @(posedge clock) begin

...
insideRegister <= ... // f(insideRegister) //New!
...
end
endmodule;

Figure 7.2: Good Style of Coding for Pad Insertion

7.8.1 Manual Pad Insertion

By preparing a “wrapper” Verilog file defining the chip-level representation of the design, we can simplify
the addition of pads to a synthesized design. For example, our synthesized converter_gates.v file
shows a top-level module converter and the definitions of its inputs and outputs. We can prepare a
chip-level module as shown in Fig. 7.3. Note that this is only a fragment of the wrapper file; the full ver-
sion is available at /CMC/kits/VRGlocal/demo/converter_chip_wrapper.v

Run this Unix command to create the file converter_pads.v, a complete Verilog description of the
chip to be used with other tools:
% cat converter_gates.v converter_chip_wrapper.v > converter_pads.v

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 VLSI User’s Manual Logic Synthesis and Optimization

module converter_chip ( clk, zero, one, ... );

input clk, zero, one, ... ;
output \segs[7] , \segs[6] , \segs[5] , ... ;
wire clk_top, zero_top, one_top, segs_7_top, segs_6_top,
segs_5_top, ... ;

-- Insert input pads:

-- pad-name, instance-name, input-pad-connection, core-wire
PDIDGZ u_clk ( .PAD( clk ), .C(clk_top) );
PDIDGZ u_zero ( .PAD( zero ), .C(zero_top) );
PDIDGZ u_one ( .PAD( one ), .C(one_top) );
...
-- Insert output pads:
-- pad-name, instance-name, core-wire, output-pad-connection
PDO08CDG u_segs7 ( .I(segs_7_top), .PAD(\segs[7] ) );
PDO08CDG u_segs6 ( .I(segs_6_top), .PAD(\segs[6] ) );
PDO08CDG u_segs5 ( .I(segs_5_top), .PAD(\segs[5] ) );
...
-- Instantiate the synthesized module
converter u_converter (
.clk (clk_top), .zero (zero_top), .one (one_top), ...
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.\segs[7] (segs_7_top), .\segs[6] (segs_6_top),

.\segs[5] (segs_5_top), ...
);
endmodule

Figure 7.3: Chip-level module including I/O pads

7.8.2 Automatic Pad Insertion

To automatically insert appropriate input, output, and bidirectional pads into your design1, you can per-
form the following steps:

1. Double click on a pin to bring up the Input/Output Port Attributes dialog window.

2. Make sure the Port Is Pad check-box is selected.

3. Click on Port Pad Attributes... button to bring up the Port Pad Attributes dialog window.

4. Make sure that the Build New Pad radio button is selected. Alternatively, you can specify a specific
pad to use as well. Refer to the Design Analyzer on-line manual for information about other
options in the form.

5. Click OK to close the Port Pad Attributes window.

6. Click Apply to confirm the changes for the selected port.

7. With the Input/Output Port Attributes window still open, you can continue changing the attributes
for other input or output ports.
Note: You cannot use the Output Port Attributes window to set attributes for input or bi-direc-

1. This works for the CMOSP18 design-kit, but attempts to try this in CMOSP35 designs will cause
errors. Input pads will be inserted, but insertion of output pads will fail.

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Logic Synthesis and Optimization VLSI User’s Manual

tional ports, and vice versa. You will need to close the current window, and double click on the
pin for which you wish to change attributes, to open up its corresponding attribute window.

8. Click Cancel to close the Port Attributes window.

This has not yet inserted the pads, but only specified ports that should have pads automatically connected
to them. To actually insert pads select Edit→Insert Pads to bring up the Insert Pads dialog window.

9. Click OK in the Insert Pads dialog window.

10. Now that you’ve inserted pads, you will need to re-optimize the design once more to make sure
that no timing has been violated. Select Tools→Design Optimization to bring up the Design Opti-
mization dialog window.

11. Select the Map Effort you’d like to use, medium should suffice, and click OK to re-optimize your
design.

At this stage, you can save your design as converter_final.v or converter_final.vhd

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Also, save the constraints by typing these two commands into the command window:
write_constraints -cover_design -format sdf-v2.1 -output converter.sdf
write_sdc converter.sdc

7.9 Transfer Synopsys Design to Cadence IC tool via Verilog

1. Start the Cadence IC tool, then select File→Import→Verilog...

2. In the pop-up form, specify

a. Target Library Name is the name of an existing Cadence library where you want to import the
schematic
b. Reference Libraries should include the names of any standard cell libraries or pad libraries ref-
erenced in your Verilog file
c. Verilog Files to Import: indicate the name of your verilog file
d. Explore the other options; default values should work well
e. Click OK to continue.
f. On completion, examine the VerilogIn.log file for problems.

7.10 Transfer Cadence IC tool Schematic to Synopsys via EDIF

1. Start the Cadence IC tool, select File→Export→EDIF 200...

2. In the pop-up form, specify

a. The Library, Cell name, View Name of the schematic to export
b. External Libraries should list the names of standard cell libraries or pad libraries used
c. Output File is the filename to use to save the data

3. In the Synopsys tools, load the EDIF file and save the design.

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 VLSI User’s Manual Automated Place-and-Route

Chapter 8 Automated Place-and-Route

This chapter demonstrates software that can be used to take a synthesized design from netlist through floor
planning, cell placement and automated routing, to create a “correct by construction” chip layout. These
tools are very complex, and have many options designers can use to customize their designs; we demon-
strate only a very simple flow and leave further investigation of these options to the reader.

The Cadence place-and-route tool is “EDI”, or “Encounter Digital Implementation”, also known as,
Encounter or “SOC Encounter”.

You will need a Verilog gate level netlist of your design as well as design constraint information before
beginning floor planning. To demonstrate the required steps, we will continue to use the converter design
from the previous chapters.

8.1 Environment Settings

If you have not done so yet, you can set up your design session using the UNIX command
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% source /CMC/tools/CSHRCs/Cadence.EDI

8.2 Required Information

Cadence Encounter requires various information before you can use it:
• a gate-level Verilog netlist: We will continue with the example we have been building over the last few
chapters, converter_pads.v
• information about the technology and the physical libraries you will be using. These are usually set up
as Library Exchange Format (LEF) files to describe the technology, a standard-cell library, perhaps a
separate library of I/O pads, and possibly a library of cells for elimination of antenna effects in wiring.
In many cases, these “physical” libraries are proprietary; the companies who supply these often pro-
vide us with only a “black-box” representation of the gates within, instead of providing full mask lay-
outs for the gates. The black-box representations supply sufficient information to allow designers and
place-and-route tools to use them correctly.
• timing libraries, describing the time delays between inputs and outputs of all of the library cells, and
the names of library cells that will be used for buffers and delays
• a file describing the location of input and output pads in your design
• names of power and ground networks
• clock-tree information
• information about constraints

This information can be set up manually, but a template for a specific technology will help. You can create
a work directory named EDI and copy a sample set-up file and related information using
% mkdir EDI
% cd EDI
% cp /CMC/kits/VRGlocal/demo/EDI/CMOSP18/* .

(Note the space followed by the “.” at the end of the final command.)

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You should see five files in your EDI directory:

• converter_pads.v : this is the chip-level Verilog description of the converter design, including pads
• converter.conf : this configuration file for Encounter contains much of the set-up, specifying the loca-
tions of various files, including the Verilog netlist, the LEF files, the TLF (timing) files, the file
describing the location of the I/O pads; it also defines the power and ground networks
• converter.io : the file describing the location of I/O pads
• converter_chip.ctstch : a file describing the clock-tree
• constr.sdc : a file describing constraints

8.2.1 Specifying Pad Locations: converter.io

Unless you are targeting high-density packaging for a system on chip design with hundreds or thousands of
pins, the periphery of your chip’s floor plan will consist of a single ring of input/output pad circuitry. The
pad cells will have power busses running through them to provide power and ground connections for the
standard cells in the core of the system (“VDDCORE” and “VSSCORE” networks), and could also have
busses running through them to provide separate power and ground connections to the input/output pads
(“VDDRING” and “VSSRING” networks). In most modern technologies, I/O pads are designed to be

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butted against each other -- the LEF (library) information usually does not indicate where these busses run
within the I/O cells, so there is no way to automatically route these busses. So, continuity of the I/O ring is
important. Pads must abut in order to guarantee continuity of n-wells as well as various metal layers used
for I/O and core power distribution. Corner cells provide connectivity for the I/O ring at the corners of the
design; their locations must be defined in this file.

There are two types of system designs:

• a pad limited design has a large number of inputs, outputs, and power and ground connections occupy-
ing a majority of the design, with a core (the actual logic cells and wiring) occupying only a small por-
tion of the design;
• a core limited design has a relatively large core area, with I/O connections not as densely packed as in
the previous case

If your design is core limited, the gaps between the pad cells can be filled in by inserting pad filler cells
(named PFEED20) or by adding additional cells to provide more connections to power or ground. Other
constraints imposed by manufacturers (e.g. minimum pitch of bonding pads to ensure that the chip can be
packaged properly) may also require that you insert additional filler cells.

Examine the converter.io file. Each pad is defined using this general template:
Pad: pad_instance_name side|corner [cellname]

where pad_instance_name is a unique instance name of a pad, side|corner can be a compass

bearing (N, W, S, or E for normal I/O pads, or NW, SW, NE, SE for corner cells). cellname is an
optional parameter specifying the name of the pad cell from the I/O library.
Note: The Artisan library I/O pad cells do not include the actual pad that will be connected by a
wire-bond to the package; the PAD cells (PADIZ40 and PADOZ40) must be added separately,
with connections to the “PAD” pin on each I/O pad cell.

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8.3 Importing Your Design

1. Start First Encounter by issuing this command in a terminal window:
% encounter
This should open a graphic window for the tool showing several regions:
• one large region, which will be used to show a representation of your design
• top row: banner menu items
• first row below: icons for some commonly-used functions
• second row below: icons for various tools
• far right side of the second row: icons for floorplan, amoeba, or physical views of the design
• right side at bottom: the “world view” -- showing what area of the design is visible in the large
region
• right side: a region allowing you to change the visibility and selectability of various parts of the
design.
The text terminal where you started encounter will display status messages, but can also be used
for typing commands.
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2. Select File→Import Design... from the banner menu of the Encounter widow

3. In the Design Import dialog window click Load... (at the bottom) and select converter.conf, then
click Open. This reads the configuration file and fills in various fields in the Design Import dialog
window. Click OK to use these files.

The large region should show a floorplan of your design, with pad cells placed as specified in the con-
verter.io file. In the middle is the region where the core cells will be placed. Between the core and the I/O
ring is a gap, which will be used to route power and ground networks supplying the core cells, as well as
for wiring from pad cells to the core circuitry.

Save this initial imported design, using File→Save Design... and changing the name to 0_imported.enc
You will be able to return to this initial saved version (or any other saved version) if you find problems in
later stages. The steps shown in the remaining parts of this chapter are typical of any design flow. Some
steps allow more customization than others; we will only touch on the main issues.

8.4 Initial Floorplan

The initial floorplan is adjustable. You can change various aspects of this floorplan using
Floorplan→Specify Floorplan... In the Specify Floorplan dialog window, you can adjust the aspect ration
of the core, the core utilization, the core row spacing and orientation, and many other parameters. After
making changes, you can Apply them, or Cancel any changes.

8.5 Placement of Pre-Built Blocks

In some cases, you might have memories and other pre-designed fixed blocks which have to be placed in
the core placement region. Prototype placement is capable of placing macros as well as standard cells in
the placement area, but if you wish to do so you may move memories and other fixed macros around, by
selecing the block and clicking the move/resize/reshape icon in the tools list: it looks like a cross with
arrow heads.

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To decrease the amount of routing congestion around these blocks and to prevent placement of standard
cells too close to these blocks it is also a good idea to specify a block halo around them: No cells will be
placed inside a block halo. To specify a block halo, select a cell and then select Floorplan→Edit Floor-
plan→Edit Halo→... Fill in the pop-up form appropriately.

8.6 Power Rings and Stripes

Power rings are used to route power busses around the periphery of the core, to make power and ground
easily accessible to all areas of the core. For larger designs, where the current in the power and ground nets
routed through standard-cell rows can exceed the current-carrying capacity of the metal power and ground
connections, power stripes can be run vertically over the rows of standard cells if the metal layer used for
these are selected carefully. These ring and stripe traces are thicker and can therefore carry more current.
Although, as previously mentioned, a core power ring exists in the pad ring, it is not accessible to the rout-
ing engine, and you cannot make connections to it directly except by a connection to

To create a power ring:

1. Select Power→Power Planning→Add Ring...

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2. In the Add Rings dialog window, enter the names of the power nets for which you’d like a ring cre-
ated (if they’re not there already): VSS VDD.

3. Select the ring type: For a core ring around your placement area, select core ring(s) contouring
followed by Around core boundary. You probably don’t want a ring contouring the I/O boundary,
as this might cause problems with pad routing connections. (If you have predesigned blocks, you
might block rings around these separately.)

4. Specify the ring configuration by specifying the types of metal layers you’d like to use for the dif-
ferent sides of the ring. Specify the width and spacing of the metal layers as well. Default values
should be satisfactory for most design, but you may increase the width and spacing of the rings.

5. Choose center in channel for the ring offset.

6. Click OK to create the power rings.

7. Select Power→Power Planning→Add Stripes... to add vertical stripes across the core region.
Try to select the number of stripes and their spacing such that they do not align with power pad
cells, to minimize potential problems later. In this example, add one set, offset by 75 microns from
the left of the core area.

8. Save the design as 1_power.enc

8.7 Trial Placement and Routing

At this point we are ready to test the placement of core cells. For complex designs it is advisable to run
prototype placement first, before committing CPU resources to running a full blown placement. Prototype
placement will give you a sense of how the standard cells will be arranged, so you can get a determine
whether or not you need to adjust floorplanning parameters for a more or less aggressive core utilization.

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1. Select Place→Place Standard Cell...

2. In the Place dialog window, choose Run Placement in Floorplan Mode: a prototyping effort is a
good place to start for large designs to determine if the cells can be placed successfully. Use the
Run Full Placement level for a final placement run later, or for simple designs.

3. Click OK to start the placement engine. The core area will contain boxes representing the cells
that have been placed. (You might need to change the view to “Physical View”, by selecting the
icon at the far right side of the Tools icon row.)

Run a trial route and simple timing verification to determine if there are any major problems:

4. Select Route→Trial Route... and use the default values; click OK to continue.

5. Select Timing→Extract RC and turn off the Save Cap to check-box; click OK to continue.

6. Click Timing→Timing Analysis...

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In the Timing Analysis window, select Use Existing Extraction and Timing Data, then click OK to
continue. Ensure that there are no timing violations. If timing constraints are not met, you can try
re-doing the Placement with a higher Placement Effort Level.

7. Run a Placement with a Placement Effort Level of High and re-run the Trial Route, ExtractRC
and Timing Analysis

8. Save this design as 2_placed

8.8 Clock Tree Insertion

Insertion of a clock tree is an important step in the design of your system, to ensure a perfectly synchro-
nized clock throughout the layout of the design. This is a complex step, but a sample is shown below.

When you started this chapter, you copied several files from the demonstration directory, including the file
converter_chip.ctstch This clock tree specification file allows you to specify many parameters, including
the depth of the clock tree, how many instances there are at each level, and the type and strength of the
buffers at each level. For your own designs, you will have to create your own clock tree specification file,
but you can use this clock tree specification file as a starting point.
AutoCTSRootPin u_clk/C
MaxDelay 2ns
MinDelay 0ns
SinkMaxTran 100ps
BufMaxTran 150ps
MaxSkew 30ps
NoGating rising
MaxDepth 7
Buffer CLKBUFX20 CLKINVX20 CLKBUFX16 CLKINVX16 CLKBUFX12
+ CLKINVX12 CLKBUFXL CLKINVXL CLKBUFX8 CLKINVX8 CLKBUFX4 CLKINVX4
+ CLKBUFX3 CLKINVX3 CLKBUFX2 CLKINVX2 CLKBUFX1 CLKINVX1
End

Figure 8.1: Sample Clock-Tree Specification, converter_chip.ctstch

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A brief description:
• AutoCTSRootPin u_clk/CRoot pin specifies the pin where the clock tree begins. Here it is specified
by u_clk, the instance name of the clock pad, and C the port of the pad.
• MaxDelay 2ns Maximum delay to tolerate from clock path beginning to end.
• MinDelay 0ns Minimum delay to tolerate from clock path beginning to end.
• MaxSkew 30ps Maximum clock skew in between different leaf nodes on the clock tree.
• NoGating rising Specifies whether clock gating is being used in the design.
• MaxDepth 7 Depth of the clock tree
• Buffer CLKBUFX20 CLKINVX20 CLKBUFX16... Names of buffers to use in the clock tree.
• End End the specific file.

You can check to see if this clock timing information was read correctly when you ran the Design Import.
Use Timing→Report→Clock Waveform... and click OK. This will show whether a clock signal is recog-
nized from the constraints file.

Now we are ready for clock-tree synthesis. Load the clock-tree specification file and synthesize the tree:

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1. Select Clock→Synthesize Clock Tree...

2. In the Specify Clock Tree dialog window, enter the file name of the clock tree specification file into
the provided field: converter_chip.ctstch

3. Click OK to load the file. Check the terminal window from which you started Encounter for any
error messages. You can check to see if this clock timing information was read correctly when you
ran the Design Import. Use Timing→Report→Clock Waveform... and click OK. This will show
a summary of clocks in your terminal window.Select Clock→Synthesize Clock Tree...

4. In the Synthesize Clock Tree dialog window, review the options and click OK to generate the
clock tree. Clock buffers will be inserted in between placed cells where required in order to meet
the timing specifications you provided.

5. Examine the clock-tree using Clock→Display→Display Clock Tree...

Click Apply to examine the clock phase delay in the layout
Change the Display Selection by clicking the check-box beside Display Clock Tree, then click
OK
Change the Display Selection to Display Min/Max Paths and click OK
Clear the clock display using Clock→Display→Clear Clock Tree Display

6. Save your clocked design, 3_clock.

8.9 The Golden Netlist

The design now contains all of the components that will be used in the final layout. Save this using
Design→Save→Netlist...
Change the name of the file to converter_chip_gold.v and click OK

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8.10 Routing
8.10.1 Route Power Nets

The rows of standard cells have power and ground rails running through them, but these must be connected
to each other and to the power rings (and to power stripes, if used). In addition, the I/O pads providing
power and ground connections must be connected to the power rails:

1. To complete the power rails in rows where standard cells are used select the Special Routing tool,
Route→Special Route...

2. Click OK to complete the power routing. You might see warnings indicating that the design has no
block pins to be routed. These are expected, because we have no pre-placed blocks in this exam-
ple. You may eliminate these warnings by turning off the check-boxes beside “Block Pins” in the
SRoute dialog window before routing power.

3. Save the design as 4_power

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8.10.2 Routing of Remaining Nets

The final stage of routing, global and detail routing, makes the connections between all of the standard
cells and I/O pad cells as indicated in the netlist.

1. Select Route→NanoRoute→Route... There are many options in the NanoRoute dialog window,
which are described fully in the on-line documentation. For this example, we will use the default
values, with one exception: Under Concurrent Routing Features we will turn on the check-box
beside Timing Driven

2. Click OK
All of the routing should be complete now.

3. Save the design as 5_routed

8.11 Place Filler Cells

Note that there are gaps between cells in the standard-cell rows. These cells are typically designed to
require abutment with other cells or to be placed on a specific grid to prevent possible design rule viola-
tions (e.g. violation of minimum spacing requirements for adjacent n-wells), but forcing a minimum spac-
ing between cells is not practical for area constrained designs. Instead, we make use of filler cells -- non-
functional blocks providing n-well and/or p-well continuity between cells -- between non-abutted cells,
thus eliminating the possibility of design rule spacing violations.

1. Select Place→Physical Cell→Add Filler...

2. In the Add Filler dialog window, click Select to view a list of possible filler cells.

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3. To select all of the possible filler cells in the new Select Filler Cells dialog window, so wider cells
will be used to fill in wide gaps as appropriate, you can select each one individually and click Add
to make it available for the automated placer, or select all of them at once using this method:
a. Left-click on the name of the cell at the top of the list
b. SHIFT-left-click on the name of the cell at the bottom of the list, so all are highlighted
c. Click Add
d. Click Close to proceed

4. In the Add Filler dialog window, click OK. You might need to refresh the layout window to view
the results.

5. Save the design as 6_filler

8.12 Optional: Metal Fill (if necessary -- CMRF8SF)

Most modern technologies require that the design meets minimum density requirements for metal layers
(and possibly others) to ensure that the deposition and patterning of the metals on the wafer during fabrica-

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tion have a consistent topography. This can be done in the DFII layout environment or here in Encounter.

8.13 Verification
You can verify various aspects of the final design:

1. Select Verify→Verify Connectivity...

This ensures that all connections are correct.

2. Select Verify→Verify Geometry...

This ensures that there are no design rule violations

3. Select Verify→Verify Process Antenna...

During fabrication, metal layers are deposited and etched to provide signal wiring; during etching,
electrical charge can build up on these metal layers. When this charge builds up sufficiently, the
gate oxide at transistor gates may be damaged, adversely affecting yield.

8.14 Final Timing Analysis

1. Select Timing→Extract RC and turn off the Save Cap to check-box; click OK to continue.

2. Click Timing→Timing Analysis...

In the Timing Analysis window, select Use Existing Extraction and Timing Data then click OK to
continue. Ensure that there are no violating paths.

8.15 Saving the Design

1. Save the design as 7_final.enc

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2. Optional, possibly required for some technologies like CMRF8SF:

In the shell window where you started encounter, type
set dbgOutLefVias 1
to eliminate a bug, where some vias are not written out properly when writing a DEF file

3. Select Design→Save→DEF...
Change the version number to use 5.5 if exporting to Cadence IC5, because that tools does not
understand newer versions of the DEF language. Keep the other default values and provide a file-
name in which to store the Design Exchange Format (DEF) file. Click OK.

4. Select Design→Save→GDS...
Keep the default values and provide a filename in which to store the Stream/GDS file. Click OK.
(In order to use this GDS file to import a design into Cadence IC tools, other work will be neces-
sary; that work will not be covered in this manual.

8.16 Importing the Design into Cadence IC tools

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8.16.1 Creating a Layout cellview by importing a DEF file

1. Start by creating a new work directory to hold the Cadence IC tools version of this design, and
starting a Cadence IC tools session
% mkdir Cadence ; cd Cadence
% startCds -t cmosp18

2. Ensure that the cds.lib file in your work directory includes references to the two cell libraries:
DEFINE artisan_sc_30 /CMC/kits/artisan.3.0/FAB/artisan_sc_30
DEFINE artisan_io_30 /CMC/kits/artisan.3.0/FAB/artisan_io_30

3. Create a new library, into which you will import the DEF file. To read the DEF correctly, you must
(temporarily) attach your library to cmosp18_defin_techlib like this:
Use CIW→File→New→Library...
Library name: Converter
Attach to: cmosp18_defin_techlib
... and click OK

4. Use CIW→File→Import→DEF...
Library Name: Converter
Cell Name:converter_chip
View Name: autoLayout
Use Ref. Library Names:artisan_sc_30 artisan_io_30
DEF File Name: ../converter_chip.def
... and click OK
Upon successful completion, the Library Manager should indicate that there exists a cell with the
name of your design, with a view autoLayout, but beware: the cell only exists in memory, and
has not been save to disk yet! To save the data, open the autoLayout cellview and use

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Design→Save.

At this point, the design will have a property associated with it which indicates that the design was created
using one of the place-and-route tools, so when you use the IC tools to try to open the design, an old place-
and-route tool “takes over”, installing its own bindkeys and banner menus. In our design environment, we
wish to use the normal Layout tool menus and bindkeys, so we need to remove that “special” property:

5. In the layout window, select Tools→Layout to change the menus to those used in the Layout tool.

6. Select Design→Properties... and then select the Property check-box in the Edit Cellview Proper-
ties dialog window.

7. Scroll down until you see the property name viewSubType with a value of designPlanC3. Left-
click on the property name (viewSubType) to highlight it, then click the Delete button at the bottom
of the window. Click OK to close this window.

8. Save the design, using Design→Save As... and save the design with a cellview of layout.

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Note: Spelling and case of the letters is significant!

9. Close the autoLayout view of the design

10. Continue by opening the layout view of the design.

8.16.2 Creating a Schematic cellview by importing a Verilog file

1. Use File→Import→Verilog...

2. In the pop-up form, specify

a. Target Library Name, the name of the library into which you want to import the design
b. Reference Libraries should include basic and the names of any standard cell libraries and pad
libraries used in the design.
c. Click OK to continue.

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