Xilinx HDL Synthesis

Flow

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 HDL Flow - Design Entry
CIC

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 HDL Flow - Synthesis
CIC

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 HDL Flow - Implementation & Programming
CIC

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 Top-level Design I CIC

! HDL Flow projects do not require the designation of

a top-level design until synthesis.
! Only VHDL or Verilog source files can be added to an
HDL Flow project.
! VHDL and Verilog source files can be created by the
HDL Editor, Finite State Machine Editor, or other text
editors.
! When you initiate the synthesis phase, you designate
one of the project's entities (VHDL) or modules
(Verilog) as the top-level of the design.
! The list of entities and modules is automatically
extracted from all the HDL source files added to the
project.

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 Top-level Design II CIC

! All HDL designs and modules below the top-level file

are elaborated and optimized.
! HDL designs can contain underlying LogiBLOXs,
schematics (EDIF files), ABEL modules, and XNF files
that are instantiated in the VHDL and Verilog code as
"black boxes."
! Black box modules are not elaborated and optimized
during synthesis.
! Refer to the "Black Box Instantiation" section for more
information on Black Boxes.

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 Create a HDL Project CIC

! New a Project
! Start Foundation Express and Select “Create a New Project”
! In Foundation Project Manger, File > New Project
! Select HDL Flow

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 Creating the Design I CIC

! 1.Open the HDL Editor

! by clicking the HDL Editor icon in the Design Entry box on the
Project Manager's Flow tab.

! 2. Use Design Wizard to create HDL

! When the HDL Editor window appears, you
may select an existing HDL file or create a
new one. The following steps describe
creating a new HDL file with the Design Wizard.
! When the HDL Editor dialog box displays, select Use HDL Design
Wizard. Click OK.

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 Creating the Design II CIC

! Click Next in the Design Wizard window.

! From the Design Wizard - Language window,
select VHDL or Verilog. Click Next.
! Note:For top-level ABEL designs, you
must use the Schematic Flow.

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 Creating the Design III CIC

! In the Design Wizard - Name window, enter

the name of your design file. Click Next.
! Define your ports in the Design Wizard-Ports
window by clicking NEW, entering the port
name, and selecting its direction. Click Finish.
The Wizard creates the ports and gives you
a template (in VHDL or Verilog) in which you
can enter your design.

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 Creating the Design IV CIC

! 3. Create the design in the HDL Editor.

! The Language Assistant is available to help with this step.
! It provides a number of language templates for basic language
constructs and synthesis templates for
synthesis-oriented
implementation of basic
functional blocks, such as
multiplexers, counters,
flip-flops, etc.
! Access the Language
Assistant by selecting
Tools > Language Assistant.
! 4. Add the design to the
project
! Project > Add to Project.
! 5. Exit the HDL Editor.

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 Analyzing Design File Syntax CIC

! How to analyze syntax

! Syntax is checked automatically when the design is added to the
project.
! In the HDL Editor, by selecting Synthesis > Check Syntax.
! In Project Manager, by selecting
Project > Analyze All HDL Source Files.
! In Files tab, by selecting source file
and right clicking, and then
clicking “Analyze”
! How to handle error and warning
! Use the HDL Error and HDL Warnings tabs in the messages area at
the bottom of the Project Manager to view any syntax errors or
messages output during analysis.

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 CIC
Performing HDL Behavioral Simulation

! If you installed an HDL simulation tool such as

ACTIVE-VHDL or ModelSIM, you can perform a
behavioral simulation of your HDL code.
! Please refer to the documentation provided with
these tools for more information.

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 Synthesizing the Design I CIC

! Translate the design into gates and optimize it for a target

architecture.
! 1. Set the global synthesis options
! By selecting Synthesis > Options from the Project Manager.
! In the Synthesis Options dialog, you can set the following defaults:
! FSM Encoding (One Hot or Binary)
! FSM Synthesis Style
! Export schematic
! Default clock frequency
! Export timing constraints
to the place and
route software
! Input XNF bus style
! 2. Click OK to close the Synthesis
Options dialog

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 Synthesizing the Design II CIC

! 3. Click the Synthesis icon on the Synthesis button on the

Flow tab.

! 4. The Synthesis/Implementation
dialog box is displayed.
! 5. Select the name of the top-level
VHDL entity or Verilog module.
! Processing will start from the file
named here and proceed through
all its underlying HDL modules.
! 6. Enter a version name.

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 Synthesizing the Design III CIC

! 7. Select the target device.

! 8. Modify the synthesis processing settings as desired.
! Modify the target clock frequency
! Select to optimize the design for speed or area
! Select the effort level as high or low
! Select whether I/O pads should be inserted for the designated
top-level module
! Select Preserve Hierarchy to preserve the design hierarchy. This
will result in producing output hierarchical netlists.
! Select Edit Synthesis/Implementation Constraints.
! Selecting this options pauses synthesis processing after the
elaboration phase to allow you to specify constraints (controls) for the
design using a constraints editor GUI.
! This feature is also referred to as the "Express Constraints Editor."
! For more information refer to the "Express Constraints Editor" section.

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 Synthesizing the Design IV CIC

! Select View Estimated Performance after Optimization.

! Select this option to view the estimated performance results
after design optimization.
! This feature is also referred as the "Time Tracker."
! For more information refer to the "Express Time Tracker"
section.
! 9. Click Run to synthesize the designated top-level
HDL design and its underlying HDL modules.
! The synthesis compiler automatically includes top-level
input and output pads required for implementation (unless
instructed not to do so in the Synthesis Settings on the
Synthesis/Implementation dialog.)

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 Express Constraints Editor I CIC

! Express Constraints Editor allows you to set

performance constraints and attributes before
optimization of FPGA designs.
! 1. The Express Constraints Editor window automatically
displays during Synthesis processing if you checked the Edit
Synthesis/Implementation Constraints box on the
Synthesis/Implementation dialog.
! Alternatively, you can access the Express Constraints Editor via
the Versions tab by right-clicking on a project version in the
Hierarchy Browser and then selecting Edit Constraints.
! 2. Design-specific information is extracted from the design
and displayed in device-specific spreadsheets. Click the tabs
to access the various spreadsheets.
! If you un-checked Insert I/O pads on the
Synthesis/Implementation dialog, only the Modules and Xilinx
Options tabs are shown. The Clocks, Ports, and Paths tabs
apply only to top-level HDL designs.
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 Express Constraints Editor II CIC

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 Express Constraints Editor III CIC

! 3. Right-click on an item in any of the spreadsheets to edit the

value, access a dialog box to edit the value, or access a pulldown
menu to select a value.
! Use the online help in the dialog boxes to understand and enter
specific constraints and options.

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 Express Constraints Editor IV CIC

! 4. Import / Export Constraints

! Optionally, you can import a constraints file (.exc) to use now
(click Import Constraints) or you can export the entered
constraints to a constraints file (.exc) for reuse (click Export
Constraints).
! 5. After you finish editing the constraints, click OK to close
the Constraints window and continue the synthesis using
the specified constraints.

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 Clocks Constraint Entry I CIC

! Use the Clocks constraint table to specify the waveforms of

periodic signals in the design.
! Name
! This is the full name of the periodic signal in the design hierarchy (for
example, top/module1/clk).
! Clock
! This is the waveform (period, rise time, fall time) of each periodic
signal.
! To specify a waveform, click the Clock cell, click the expand arrow that
appears in the cell, and then select Define...

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 Clocks Constraint Entry II CIC

! This displays the Define Clock dialog box where you can
enter the period, rise time, and fall time of the signal.

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 Paths Constraint Entry I CIC

! Use the Paths constraint table to specify timing constraints

for timing groups.
! From
! all primary inputs of the design
! all edge-sensitive sequential elements clocked by a specified periodic
signal
! all level-sensitive sequential elements clocked by a specified periodic
signal
! To
! all primary outputs of the design
! all edge-sensitive sequential elements clocked by a specified periodic
signal
! all level-sensitive sequential elements clocked by a specified periodic
signal.

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 Paths Constraint Entry II CIC

All input ports

All output ports

Flip-flops clocked by rising edge

Flip-flops clocked by falling edge

Latches with active high enable

Latches with active low enable

Subpath start point or end point

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 Paths Constraint Entry III CIC

! Required Delay
! This is the maximum delay of the path, computed from the
waveforms of the periodic signals.
! This value is the difference between the active edge of the
end group of the path and the active edge of the starting
group of the path.
! To enter a new value for a path group, click the Required
Delay column to highlight the default value and type in the
new value.
! Default Delay Values
! FPGA Express computes default timing values using the default
waveforms of the periodic signals.

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 Sub Path I CIC

! Subpath
! A subset of the actual paths within a primary timing path need a
tighter constraint to
ensure correct behavior.
! Note that you cannot specify a false or multicycle path by making
the subpath delay
longer than that of the primary path.
! Create / Edit Timing Subpath
! Create a new subpath by clicking the right mouse button on either
the appropriate primary path or any subpath of the primary path,
and selecting New Sub path.
! To edit an existing subpath, click the right mouse button on it and
select Edit Sub path

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 Sub Path II CIC

! In the Create/Edit Timing Sub Path dialog box, enter the desired
delay, and then double-click all of cells making up the subpath. The
controls below each list give an alternate way of adding named
cells to the list using global-style regular expressions (similar to
filename wildcards).

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 Ports Constraint Entry I CIC

! Enter port-specific constraints in the Ports constraint table.

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 Ports Constraint Entry II CIC

! Input Delay
! To define an input delay other than the default, click the Input Delay
cell for a port and select Define.

! Output Delay
! To define an output delay other than the default, click the Output
Delay cell for a port and select Define.

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 Ports Constraint Entry III CIC

! Global Buffer
! To specify insertion of a global buffer for a port or to select
automatic global buffer insertion, click the Global Buffer cell
for a port and make the appropriate selection.
! AUTOMATIC (default), DONT USE.
! You cannot define global buffers for a design that has the Do
Not Insert I/O Pads option selected.
! Pad Direction
! Use the pull-down list in this cell to specify this port as three-
state (bidirectional).
! Resistance
! Resistance options for a port or pad are specific to the
implementation's target device.
! NONE (default), PULLUP, PULLDOWN

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 Ports Constraint Entry IV CIC

! Input Register Delay

! Control whether optimization uses an input delay inside an
input register. The use of an input delay reduces the hold time
requirement for an input transition.
! DELAY (default), NODELAY
! Use I/O Register
! You can specify that I/O register pads be used on a port
where applicable.
! TRUE (default), FALSE
! Slew Rate
! You can select a fast or slow slew rate for an output or
bidirectional port.
! SLOW (default), FAST

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 Ports Constraint Entry V CIC

! Pad Location
! To specify the location of pads for a port, enter it in this cell.
! Pad locations are vendor-specific.
! You cannot specify pad locations for a design that has the Do
Not Insert I/O Pads option selected.

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 Modules Constraint Entry I CIC

! Use the Modules constraint table to control optimizing the

design hierarchy.
! Hierarchy
! Use this setting to control the preservation or elimination of the
module’s boundary during optimization.
! Set to Preserve, FPGA Express retains the boundary of this module
during optimization.
! The logic of this module is optimized independently of the rest of the
design’s logic, and the module remains a module in the optimized
implementation.

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 Modules Constraint Entry II CIC

! An Eliminate setting allows elimination of the boundary

between the module and its container during optimization.
! FPGA Express optimizes the logic of this module with the logic of
the rest of the module’s container.
! Default : Eliminate
! Primitives
! Use this setting to control the preservation or optimization of
the primitives instantiated in the module.
! When set to Preserve, FPGA Express retains the boundaries of
all the primitives instantiated in the module and uses the
implementation of the primitives provided by the architecture
vendor.
! An Optimize setting eliminates the boundaries of all the
primitives instantiated in the module and FPGA Express
optimizes the primitive logic with the logic of the module.
! default : Preserve.

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 Modules Constraint Entry III CIC

! Operator Sharing
! Use this setting to control sharing the operators in the module.
! Off : FPGA Express implements each operator using a separate
hardware resource and selects the best implementation of
each of these resources.
! On : FPGA Express determines which operators can be
implemented sharing the same hardware resource in order to
improve the area and speed of your design. It also selects the
best implementation of every hardware resource it uses.
! default : On
! Optimize for Speed or Area
! Use this setting to control whether you want to optimize for
faster speed or smaller area.
! default : speed

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 Modules Constraint Entry IV CIC

! Effort
! Use this setting to control whether the mapping effort for this
design is high or low.
! This option affects timing optimization most with little
influence on area.
! Low effort takes the least time to compile. Use low if you are
running a test to check the logic. Low is not recommended if
the design must meet area or timing goals.
! High effort takes longer to compile but should produce better
designs. The mapping process proceeds until it has tried all
strategies.
! default : High
! Duplicate Register Merge
! Removes duplicate cells. Values include Enable, Disable.

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 Xilinx Options CIC

! Ignore unlinked cells during GSR mapping

! A check in this check box enables GSR mapping for black boxes.
! Optimized for place and route
! Select a place and route tool from the drop-down list.

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 Express Time Tracker CIC

! The Express Time Tracker allows you view estimated

performance results after optimization of your designs.
! 1. The Optimized (Constraints) window automatically displays
after Synthesis processing if you checked the View Estimated
Performance after Optimization box in the
Synthesis/Implementation dialog window.
! Alternatively, you can access the Optimized (Constraints) window
via the Versions tab by right-clicking on an optimized structure in
the Hierarchy Browser and then selecting View Synthesis Results.
! 2. Click the tabs to access the performance results in the
various spreadsheets.
! If you un-checked Insert I/O pads on the
Synthesis/Implementation dialog, only the Models and Xilinx
Options tabs are shown. The Clocks, Ports, and Paths tabs apply
only to top-level HDL designs.

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 Analyzing Timing - Clocks CIC

! Check the Clocks constraint table to see the maximum

clock frequencies FPGA Express calculated for each of the
clocks in the design. Clock frequency violations appear in
red.

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 Analyzing Timing - Paths CIC

! Check the Paths constraint table for more detail on timing

violations.
! Select a path group to see a list of paths in that group.
! Select a path from the list to see the details of path composition,
cumulative delays, and fanout.

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 Analyzing Timing - Ports CIC

! Check the Ports constraint table for information about

input and output delays.

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 Analyzing Resources - Modules CIC

! Check the Modules constraint table for information about

the device resources used.
! Double-click the rows in the Area column for details about cell
count.

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 CIC
Performing Functional Simulation I

! Functional Simulation may be performed to verify that the

logic you created is correct.
! 1. Open the Logic Simulator
! By clicking the Functional Simulation icon in the Simulation box on
the Project Manager's Flow tab.

! 2. The design is automatically

loaded into the simulator.

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 CIC
Performing Functional Simulation II
! 3. Add signals
! By selecting Signal > Add Signals.
! From the Signals Selection portion of the Components Selection for
Waveform Viewer window, select the signals that you want to see in the
simulator.
! Use CTRL-click to select multiple signals. Make sure you add output signals
as well as input signals.
! Click Add and then Close. The signals are added to the Waveform Viewer
in the Logic Simulator screen.
! 4. Attach Stimulus
! Invoke Stimulator Selection window
! Select Signal > Add Stimulators from
the Logic Simulator menu.
! Create the waveform stimulus by
attaching stimulus to the inputs.
! For more details on how to use the
Stimulus Selection window, click Help.

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 CIC
Performing Functional Simulation III

! 5. Run Simulation
! After the stimulus has been applied to all inputs, click the Simulator
Step icon on the Logic Simulator toolbar to perform a simulation
step.
! The length of the step can be changed in the Simulation Step Value
box to the right of the Simulation Step box. (If the Simulator
window is not open, select View > Main Toolbar.)

! 6. Verify that the output waveform is correct.

! Click the step button repeatedly to continue simulating.
! 7. Save theflow-47
stimulus for future viewing or reuse
Y.T.Chang/2001.02/XLNX_HDL
select File > Save Waveform Enter a file name with a tve
 Implementing the Design I CIC

! Design Implementation is the process of translating, mapping, placing,

routing, and generating a Bit file for your design.
! Optionally, it can also generate post-implementation timing data.
! 1. Click the Implementation icon on the Implementation phase button
on the Project Manager's Flow tab.

! 2.The Synthesis/Implementation dialog box appears if the design

version has been synthesized but no revisions exist.
! A revision represents an implementation on the version selected for the
Synthesis phase.
! Modify the name in the Revision Name box, if desired. The other settings
are the same ones set for the synthesis phase.

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 Implementing the Design II CIC

! 3. Click the Options button under the

Physical Implementation Settings
area. The Options dialog box displays.
! 4. Choose any desired implementation
option.
! If you are planning on conducting a timing
simulation, select the Produce Timing Simulation
Data option.
! 5. Click OK to return to the
Synthesis/Implementation dialog box.
! 6. Click Run to implement your design.
The Flow Engine displays the progress of the
implementation.
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 Implementing the Design III CIC

! The Project Manager displays a status message when

Implementation is complete.
! View the Console tab on the Project Manager window for the
results of all stages of the implementation.
! The Versions tab also indicates the status of the implemented
revision.
! 7. Review Reports
! Click the Versions tab in the Hierarchy Browser area of the Project
Manager.
! Select the current revision.
! Then select the Reports tab on the Project Manager window to
review the reports and logs for that revision of the design.
! Click on the Implementation Report Files icon to view the
implementation reports.
! Click on the Implementation Log File icon to view the Flow
Engine's processing log.
! For more information on the Flow Engine, select Help >
Foundation Help Contents > Flow Engine.
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 Verifying the Design I CIC

! The Timing Analyzer or the Timing Simulator can be used

to perform a timing analysis on your design.
! The Timing Analyzer performs a static timing analysis that does
not include insertion of stimulus vectors.
! The Timing Simulator uses input stimulus to run the simulation.
! Performing a Static Timing Analysis
! 1. Click the Timing Analyzer icon in the Verification box on the
Project Manager's Flow tab.

! 2. Perform a static timing analysis on mapped or place and routed

designs.
! For FPGAs, you can perform a post-MAP or post-place timing analysis
to obtain rough timing information before routing delays are added.

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 Verifying the Design II CIC

! For CPLDs, you can perform a post-implementation timing analysis after a

design has been implemented.
! For details on how to use the Timing Analyzer, select Help > Foundation Help
Contents > Timing Analyzer.
! Performing a Timing Simulation
! 1. Open the Timing Simulator by clicking the Timing Simulation icon in the
Verification box on the Project Manager's Flow tab. The implementation
timing netlist will be loaded into the simulator.

! 2. Refer to the "Performing Functional Simulation (Optional)" section

earlier in this chapter for instructions on simulating the design. (The
operation of the simulator is the same for functional and timing simulation.)
! 3. If you have already saved test vectors (for instance, in the functional
simulation), you may load these vectors into the timing simulator by
selecting File > Load Waveform.

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 Programming the Device CIC

! 1. Invoke Program Box

! Click the Device Programming icon in the Programming box on the Project
Manager's Flow tab.

! 2. From the Select Program box, choose the Hardware Debugger, the
PROM File Formatter, or the JTAG Programmer.
! For CPLD designs, use the JTAG Programmer.
! For instructions, select Help > Foundation Help Contents > Advanced
Tools > JTAG Programmer.
! For FPGA designs, use the JTAG Programmer, Hardware Debugger, or
PROM File Formatter.
! For instructions, select Help > Foundation Help Contents > Advanced
Tools and then select the desired tool.

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