International Journal of Engineering and Technical Research (IJETR)

ISSN: 2321-0869, Volume-2, Issue-10, October 2014

Application of Digital System with Clock Speed in

Phase Locked Loop Clock Multipliers
Ekwe, A.O, Nwaogu, C. C, Abunike E.C
(phase frequency detector) circuits. In this work, we study the
Abstract As the bandwidth demand of computer and digital application of digital systems with clock speed in the
communications components continues to grow, high-speed giga-hertz range relying on ON-CHIPphase locked loop clock
serial I/O links are replacing traditional parallel buses. multipliers. In particular we focus on scaling the supply
High-performance digital systems use clocks to sequence
voltage, scaling down the area, operation over a frequency
operations and synchronize between functional units and
between ICs. Clock frequencies and data rates have been
range of 1GHZ, and achieving ultra low noise and jitter
increasing with each generation of processing technology and performance.
processor architecture. Phase locked-loops (PLLs) are widely An ultra low voltage (ULV) of 1-GHz PLL including a GFSK
used to generate well-timed on-chip clocks in high-performance modulator and implemented in a standard digital 90-nm
digital systems. This paper focuses on the application of Digital CMOS technology is first introduced. The design addresses
System with Clock Speed in the 1-Ghz range relying on the Chip robustness concerns and speed issues due to the aggressive
of a Phase Locked Loop Clock Multipliers supply voltage scaling (down to 0.5V). Next, a 2.5-GHz
ultra-compact analog PLL implemented in a 45-nm CMOS
technology is described to demonstrate that area scaling can
Index Terms Phase Locked Loop, Sequence, Clock, Chips
indeed be achieved in PLLs. The 0.042 square mm fully
integrated PLL includes an on-chip LC-VCO and an on-chip
passive R-C loop filter. A rigorous methodology for
I. INTRODUCTION
area-scaling LC oscillators by taking advantage of increased
As the bandwidth demand of computer and digital transistor speed is described as well as a novel stacked
communications components continues to grow, high-speed capacitor-inductor device is introduced to further reduce area.
serial I/O links are replacing traditional parallel buses. In the past thirty years, CMOS has become dominant in
Operating at speeds of giga hertz range, such high-speed I/O commercial, or more specifically, digital IC products. From
circuits are already found in packet switches, circuit switches, the fastest microprocessors to the simplest CD4000 by RCA
and processor-memory interconnects. Hundreds of these includes two 3-input NOR gates and one inverter. The
high-speed I/Os have been successfully integrated on a single CD4000 series is for general purpose and currently called
chip enabling monolithic switches with aggregate I/O 4000 series, which includes both the original CD4000 and
bandwidths as high as 1 Tb/s. By increasing the bandwidth per HEF4000 series. digital cooking timers, over 99% of todays
package pin and connector pin, high-speed I/Os reduce the commercial ICs are fabricated in CMOS, and this dominance
system size and cost per unit bandwidth and meet the demand is not expected to be changed in the foreseeable future.
for higher bandwidth computer and communication Because the market of CMOS logic has become so
systems[1]. Highly scaled CMOS devices can only operate diversified, semiconductor industries developed transistors
from lower voltages and their analog transistor characteristics with different characteristics targeting various applications.
can be degraded compared to longer channel length devices. High performance (HP) transistors are used in chips where
This raises many design concerns particularly for high-speed computation is needed, such as the central
conventional analog circuits. On the other hand, CMOS processing units (CPUs) in desktop personal computers (PCs)
technology scaling still results in significant speed and and servers. They have the shortest gate length for highest
functional density increases. This opens up many new speed, and the resulting power consumption is also the
opportunities for mitigating analog and mixed-mode design highest. Low power transistors are used by portable or mobile
challenges using appropriate circuit and design solutions. systems, and they can further be divided into two categories:
Almost all electronic communication and computation low operating power (LOP) and low standby power (LSTP).
devices rely on phase-locked loop (PLL) synthesizers to LOP transistors are typically used in relatively high
generate frequency references and clocks. Designing and performance mobile systems where larger batteries are
application of a PLL is a true mixed-signal design challenge available (e.g. laptop computers). This type of transistors
covering from high-speed analog and RF blocks (VCO), to emphasizes on lower operating (dynamic) power, and
high-speed digital blocks (dividers), to low-speed, low-noise therefore the corresponding supply voltage is the lowest. The
analog (charge pump and loop filter) and low-speed digital gate length is about one year behind HP transistors for the
development. LSTP transistors are used in consumer
electronics with lower performance and a very limited battery
Manuscript received October 14, 2014.
Ekwe, A.O, Department of Electrical/Electronics Engineering, capacity (e.g. cellular phones). Such transistors have the
MOUAU, Abia, Nigeria highest threshold voltage and supply voltage to minimize the
Nwaogu, C. C, Department of Electrical/Electronics Engineering, leakage to achieve a long battery life. The gate length of LSTP
MOUAU, Abia, Nigeria logic is about two years behind that of HP logic to develop
Abunike E.C, Department of Electrical/Electronics Engineering,
MOUAU, Abia, Nigeria
ultra-low leakage process. The above three types of
transistors are thin oxide devices. Most foundries allow only

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 Application of Digital System with Clock Speed in Phase Locked Loop Clock Multipliers

one type of thin oxide transistors on the same wafer. On the generation and in digital systems, microprocessor,
other hand, analog integrated circuits have evolved from networking, parallel and serial data communication, and
simple amplifiers made of a few transistors to very large frequency synthesizers. Because of the increase in the speed
mixed-mode systems, which are capable of interfacing the of the circuit operation, there is a need for a PLL circuit with
real world for complicated computation systems, handling faster locking ability. Many present communication systems
continuous or discrete time signals, detecting signals as small operate in the GHz frequency range and we are going to
as nano-volts or pico-amperes, or operating at frequencies examine the application of 1GHz clock bit range relying on
beyond 100 GHz. The diversity of analog functions have ON-Chip PLL which must operate in the GHz range with less
enabled countless new applications [4-5]. lock time. The PLL performance and stability of the whole
New emerging applications such as software-defined radios PLL system depends on the order of the loop filter. The
or highly integrated test instrumentation require a frequency voltage controlled oscillator (VCO) is the heart of the
synthesizer with ultra wide frequency coverage and ultra low PLL[10].
phase noise. Two approaches are presented to achieve these
challenging design and application objectives by exploiting 3.1 Clock Recovery System
the capabilities of nanometer transistors. A wideband Some data streams, especially high-speed serial data streams
synthesizer covering from 125 MHz to 32 GHz with a (such as the raw stream of data from the magnetic head of a
constant jitter performance across the entire frequency range disk drive), are sent without an accompanying clock. The
is described; the scaling and design methodologies to achieve receiver generates a clock bit from an approximate frequency
constant jitter performance across the ultra-wide frequency reference(1Ghz) and then phase-aligns to the transitions in the
range are discussed. Finally, an ultra low noise, two-step data stream with a PLL. This process is referred to as clock
synthesizer is presented to show how ultra-low phase-noise recovery. In order for this scheme to work, the data stream
fractional-N frequency synthesis can be achieved by taking must have a transition frequently enough to correct any drift in
the full advantage of nano-scale CMOS transistors [2][3]. the PLL's oscillator.

II. COMPONENTS USED IN THE DESIGN AND

APPLICATION
The components of used in this design include:
A digital system
Phase locked loop (PLL)
Analog system
LDO

Figure2: Block diagram showing clock distribution using PLL

3.2 Clock Distribution

Typically, the reference clock enters the on chip at a clock bit
that drives a phase locked loop (PLL), for the purpose of this
paper, we are looking at a digital on chip PLL in the 1GHz
range. This then drives the system's clock distribution. The
clock distribution is usually balanced so that the clock arrives
at every endpoint simultaneously. One of those endpoints is
the PLL's feedback input. The function of the PLL is to
compare the distributed clock to the incoming reference
clock, and vary the phase and frequency of its output until the
reference and feedback clocks are phase and frequency
matched. PLLs are ubiquitousthey tune clocks in systems
several feet across, as well as clocks in small portions of
individual chips. Sometimes the reference clock may not
actually be a pure clock at all, but rather a data stream with
enough transitions that the PLL is able to recover a regular
clock from that stream. Sometimes the reference clock is the
same frequency as the clock driven through the clock
Figure1: A block diagram of a digital system application
distribution, other times the distributed clock may be some
using a phase locked loop
rational multiple of the reference.

III. APPLICATION OF DIGITAL SYSTEMS WITH

3.3 Clock generation
CLOCK BIT PHASE LOCKED LOOP MULTIPLIERS.
Many electronic systems include processors of various sorts
The most versatile application of the phase locked loops that operate at hundreds of megahertz. Typically, the clocks
(PLL) is for clock recovery, clock distribution, clock supplied to these processors come from clock generator PLLs,

132 www.erpublication.org
 International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869, Volume-2, Issue-10, October 2014

which multiply a lower-frequency reference clock (usually 50 Oscillators and Phase-Locked Loops with White and 1/f Noise, IEEE Tran.
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charge pump PLL. The simulated settling time is less than AUTHORS
4s. The RMS value of period jitter of the PLLs output is 2.1
ps. The PLL core occupies an area of 0.12 mm2, one fourth of Engr. Ogbonna A. Ekwe is a highly motivated Electronic Engineer
which is occupied by the MiM loop capacitors. The total with a bias in Communications. He is currently lecturing in the department
of Electrical/Electronic Engineering, Michael Okpara University of
current consumption of the chip is 16.5 mA. The chip has Agriculture, Umudike, Abia State, Nigeria and also pursuing his Phd in the
been sent for fabrication in 0.13 m complementary metal same department. His research interest are in the areas of Interference
oxide semiconductor (CMOS) technology [11][12]. management for cellular network, Channel fading mitigation for fixed and
mobile wireless communication systems, etc.
IV. CONCLUSIONS Nwaogu, C. C is an undergraduate student in the department of
Phase-locked loops are widely used for synchronization electrical/electronic engineering, MOUAU, Abia, State Nigeria
purposes; in space communications for coherent carrier Abunike E.C holds a Bachelor degree in Electrical/Electronic
tracking and threshold extension, bi synchronization, and Engineering from University of Nigeria Nsukka, and currently pursuing a
symbol synchronization. Phase-locked loops can also be used master degree program in the department of Electrical and Electronic
to demodulate frequency-modulated signals. In radio Engineering, Micheal Okpara university of Agriculture, Umudike. He is
presently lecturing in the department of Electrical/Electronic Engineering,
transmitters, a PLL is used to synthesize new frequencies Michael Okpara University of Agriculture, Umudike, Abia State, Nigeria.
which are a multiple of a reference frequency, with the same His research interest are in the areas of Electrical and power Systems
stability as the reference frequency. Engineering.

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