Verilog Codes
Verilog Codes
Verilog Codes
// File Name
: rom_using_case.v
// Function
: ROM using case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module rom_using_case (
address , // Address input
data, // Data output
read_en, // Read Enable
ce
// Chip Enable
);
input [3:0] address;
output [7:0] data;
input read_en;
input ce;
reg [7:0] data ;
always @ (ce or read_en or address)
begin
case (address)
0 : data = 10;
1 : data = 55;
2 : data = 244;
3 : data = 0;
4 : data = 1;
5 : data = 8'hff;
6 : data = 8'h11;
7 : data = 8'h1;
8 : data = 8'h10;
9 : data = 8'h0;
10 : data = 8'h10;
11 : data = 8'h15;
12 : data = 8'h60;
13 : data = 8'h90;
14 : data = 8'h70;
15 : data = 8'h90;
endcase
end
endmodule
reg [7:0]
mem [0:255] ;
integer file_pointer;
assign data = (ce && read_en) ? mem[address] : 8'b0;
integer i;
initial begin
$readmemb("memory.list",mem);
end
endmodule
module rom_tb;
reg [7:0] address;
reg read_en, ce;
wire [7:0] data;
integer i;
initial begin
address = 0;
read_en = 0;
ce
= 0;
#10 $monitor ("address = %h, data = %h, read_en = %b, ce = %b", address,
data, read_en, ce);
for (i = 0; i <256; i = i +1 )begin
#5 address = i;
read_en = 1;
ce = 1;
#5 read_en = 0;
ce = 0;
address = 0;
end
end
rom U(
address , // Address input
data
, // Data output
read_en , // Read Enable
ce
// Chip Enable
);
endmodule
counter
timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
20:18:33 03/25/2015
// Design Name:
// Module Name:
counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counter(clk,rst,count);
input clk,rst;
output[3:0] count;
reg[3:0] count;
always@(posedge clk or posedge rst)
begin
if(rst)
count<=4'b0000;
else
count<=count+1;
end
endmodule
mux 2*1
//----------------------------------------------------// Design Name : mux_using_if
// File Name
: mux_using_if.v
// Function
: 2:1 Mux using If
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_if(
din_0
, // Mux first input
din_1
, // Mux Second input
sel
, // Select input
mux_out
// Mux output
);
//-----------Input Ports--------------input din_0, din_1, sel ;
//-----------Output Ports--------------output mux_out;
//------------Internal Variables-------reg mux_out;
//-------------Code Starts Here--------always @ (sel or din_0 or din_1)
begin : MUX
if (sel == 1'b0) begin
mux_out = din_0;
end else begin
mux_out = din_1 ;
end
end
endmodule //End Of Module mux
mux
-------------------------------------------------------- Design Name : mux_using_if
-- File Name
: mux_using_if.vhd
-- Function
: 2:1 Mux using If
-- Coder
: Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity mux_using_if is
port (
din_0
din_1
sel
mux_out
:in
:in
:in
:out
std_logic;
std_logic;
std_logic;
std_logic
-----
);
end entity;
architecture behavior of mux_using_if is
begin
MUX:
process (sel, din_0, din_1) begin
if (sel = '0') then
mux_out <= din_0;
else
mux_out <= din_1;
end if;
end process;
end architecture;
RefDes
Description
Xilinx Components
ds100.pdf
U1
ds202.pdf
U1
ds080.pdf
U2
ds056.pdf
U3
XC95144XL CPLD
ds123.pdf
U4-U5
In-Box
SiliconSystems 128MB
CompactFlash
TM162VCA6_SPEC.pdf
In-Box
HTF4C16_32_64x64HG.pdf
In Box
Board Components
Texas Instruments Components
TI Power Management Solutions for Xilinx FPGAs & CPLDs
TI Virtex-5 Power Management Solutions
TPS73633
U18, U21
TPS73118
U20
TPS74401
U30-U31, U33,
U40-U41
TPS51100
U42-U43
PTH08T240W
U35, U38
PTH08T220W
U37
U7, U45
CD4069UB
U39
U6/U6B
5067.pdf
U15
6485.pdf
U25
61NLP_NVP25636A_51218A.p
U26
df
30666604.pdf
U27
5V9885_datasheet.pdf
U8
ics843001-21.pdf
U10
ics8543.pdf
U11
ics85401.pdf
U12
ics844021-01i.pdf
U29
ics844071i.pdf
U44
M88E1111.pdf
U16
369857613ADR01_2_3_6_i.pd
U9
f
580393681ADM3202_22_138
U13
5_c.pdf
1024567057ADT7476_0.pdf
U14
464471350AD9980_0.pdf
U19
87560554AD1981B_c.pdf
U22
7301ds.pdf
U17
CY7C67300-100AI.pdf
U23
mic2025.pdf
U24
J1
PC4 Connector
32K10E-400b.pdf
015244742_sd.pdf
J15
022112032_sd.pdf
J31
Fan Connector
678008005_sd.pdf
J40, J41
N7E50_7516PG_20.pdf
P1
SJ100129_MM50_200B___E.pd
P2
f
K31-E9P-NJ.pdf
P3
KMDR-6S-BS.pdf
P4-P5
Mini-DIN Connectors
fastjack-gigabit.pdf
P6
KVI-DA29S-N-x.pdf
P7
DVI Connector
K66X-E15S-N.pdf
P8
VGA Connector
STX-3150-3N.pdf
P10-P13
p69.pdf
P14
KUSB-SMT-BS1N-xxx.pdf
P17
KUSB-SL-AS1N-x.pdf
P18
C_6367034_1.pdf
P19
C_6367035_1.pdf
P19
ENG_CD_1367073_C.pdf
P19
SFP Connector
ENG_CD_5767004_C.pdf
P22
PJ-002AHa.pdf
P20
Power Jack
APT1608PGW.pdf (Green)
APT1608EC.pdf (Red)
MS-100663.pdf
Power Switch
atc0000ce6.pdf
SW2
SDM.pdf
SeriesTL3301Tact.pdf
SW4-SW5, SW7,
Tact (PB) Switches
SW10-SW14
1107741_1108800.pdf
X1, X5
abls-2-3.pdf
X2-X4, X6-X7
Crystal, SMD
ZTB_ZTBF.pdf
X8
acol-achl.pdf
Install in X5
AT-1220-TT-2-R.pdf
SP1
ML616S_ML621S.pdf
ML_Series_Tab_Configurations B1
.pdf
Q1-Q5, Q8-Q9,
Q11-Q18, Q20Q21, Q40-Q42
NDT3055L.pdf
Q10
3352.pdf
R86
NDS331N.pdf
Note: This is collection of the device datasheets, which were available at the time
the ML506 was designed. To obtain the latest datasheets, visit the vendor's website.