Document Number Revision Author Project Manager

ENG-46158 Revision 1.7 Yi-Chin Chu JR Rivers

Serial-GMII Specication
The Serial Gigabit Media Independent Interface (SGMII) is designed to satisfy the following requirements: Convey network data and port speed between a 10/100/1000 PHY and a MAC with signicantly less signal pins than required for GMII. Operate in both half and full duplex and at all port speeds.

Change History
Revision 1.7 1.6 1.5 1.4 1.3 Date July 20, 20001 Jan 4, 20001 Aug 4, 2000 June 30, 2000 April 17, 2000 Description Clarify data sampling and also the possible loss of the rst byte of preamble. Added specications for Cisco Systems Intellectual Property. Specied the data pattern for the beginning of the frame (preamble, SFD) for the frames sent from the PHY to make the PCS layer work properly. Took out Jabber info, changed tx_Cong_Reg[0] from 0 to 1 to make AutoNegotiation work Increased allowable input and output common mode range. The output high and low voltages were also increased appropriately. Added specication for output over/undershoot. Added note about AC coupling and clock recovery. Added timing budget analysis and reduced LVDS input threshold to +/- 50 mV. Incoporated Auto-Negotiation Process for update of link status Initial Release

1.2 1.1 1.0

Feb 8, 2000 Nov 10, 1999 Oct. 14, 1999

Denitions
MII Media Independent Interface: A digital interface that provides a 4-bit wide datapath between a 10/100 Mbit/s PHY and a MAC sublayer. Since MII is a subset of GMII, in this document, we will use the term GMII to cover all of the specication regarding the MII interface. GMII Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide datapath between a 1000 Mbit/s PHY and a MAC sublayer. It also supports the 4-bit wide MII
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interface as dened in the IEEE 802.3z specication. In this document, the term GMII covers all 10/100/1000 Mbit/s interface operations.

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Overview
SGMII uses two data signals and two clock signals to convey frame data and link rate information between a 10/100/1000 PHY and an Ethernet MAC. The data signals operate at 1.25 Gbaud and the clocks operate at 625 MHz (a DDR interface). Due to the speed of operation, each of these signals is realized as a differential pair thus providing signal integrity while minimizing system noise. Figure 1 illustrates the simple connections in a system utilizing SGMII.

MAC CRS RX_DV RX_ER RXD[7:0] RX_CLK COL TX_EN TX_ER TXD[7:0] TX_CLK GTX_CLK
8 8

PHY CRS

802.3z Receive PCS

RX 802.3z Synch RXCLK

802.3z Transmit PCS

RX_DV RX_ER
8

RXD[7:0] RX_CK COL TX_EN

802.3z Auto-Negotiation TX 802.3z Transmit PCS TXCLK

802.3z Auto-Negotiation 802.3z Receive PCS

802.3z Synch

TX_ER
8

TXD[7:0] TX_CLK GTX_CLK

Figure 1

SGMII Connectivity

The transmit and receive data paths leverage the 1000BASE-SX PCS dened in the IEEE 802.3z specication (clause 36). The traditional GMII data signals (TXD/RXD), data valid signals (TX_EN/RX_DV), and error signals (TX_ER/RX_ER) are encoded, serialized and output with the appropriate DDR clocking. Thus it is a 1.25 Gbaud interface with a 625 MHz clock. Carrier Sense (CRS) is derived/inferred from RX_DV, and collision (COL) is logically derived in the MAC when RX_DV and TX_EN are simultaneously asserted. Control information, as specied in Table 1, is transferred from the PHY to the MAC to signal the change of the control information. This is achieved by using the Auto-Negotiation functionality dened in Clause 37 of the IEEE Specication 802.3z. Instead of the ability advertisement, the PHY sends the control information via its tx_cong_Reg[15:0] as specied in Table 1 whenever the control information changes. Upon receiving control information, the MAC acknowledges the update of the control information by asserting bit 14 of its tx_cong_reg{15:0] as specied in Table 1. SGMII details source synchronous clocking; however, specic implementations may desire to recover clock from the data rather than use the supplied clock. This operation is allowed; however, all sources of data must generate the appropriate clock regardless of how they clock receive data.

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Revision 1.7

The link_timer inside the Auto-Negotiation has been changed from 10 msec to 1.6 msec to ensure a prompt update of the link status.
Bit Number 15 14 13 12 11:10 tx_cong_Reg[15:0] sent from the PHY to the MAC Link: 1 = link up, 0 = link down Reserved for Auto-Negotiation acknowledge as specied in 802.3z 0: Reserved for future use Duplex mode: 1 = full duplex, 0 = half duplex Speed: Bit 11, 10: 1 1 = Reserved 1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X 0 1 = 100 Mbps: 100BASE-TX, 100BASE-FX 0 0 = 10 Mbps: 10BASET, 10BASE2, 10BASE5 0: Reserved for future use 1 tx_cong_Reg[15:0] sent from the MAC to the PHY 0: Reserved for future use 1 0: Reserved for future use 0: Reserved for future use 0: Reserved for future use

9:1 0

0: Reserved for future use 1

table 1

Denition of Control Information passed between links via tx_cong_Reg[15:0]

Clearly, SGMIIs 1.25 Gbaud transfer rate is excessive for interfaces operating at 10 or 100 Mbps. When these situations occur, the interface elongates the frame by replicating each frame byte 10 times for 100 Mbps and 100 types for 10 Mbps. This frame elongation takes place above the 802.3z PCS layer, thus the start frame delimiter only appears once per frame. The 802.3z PCS layer may remove the rst byte of the elongated frame.

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Implementation Specication
This section discusses how this SGMII interface shall be implemented by incorporating and modifying the PCS layer of the IEEE Specication 802.3z.

Signal Mapping at the PHY side

Figure 2 shows the PHY functional block diagram. It illustrates how the PCS layer shall be modied and incorporated at the PHY side in the SGMII interface.
MAC PHY
CRS PCS Layer from 802.3z Figure 36-2

RX RXCLK

RX

Serializer

ENC_RXD[0:9] 10

RXCLK PCS Transmit TX_EN State Machine TX_ER from 802.3z Figure 36-5, TXD[7:0] Figure 36-6 TX_CLK

RX_DV RX_ER RXD[7:0] RX_CLK @ 125 MHz

PHY Receive Rate Adaptation

GMII Signals from 10/100/1000PHY

RX_CLK @ 2.5/25/125 MHz

Auto-Negotiation Figure 37-6

TX TXCLK

Deserializer

ENC_TXD[0:9] 10 Synchronization Figure 36-9

RX_DV PCS Receive State Machine RX_ER from 802.3z Figure 36-7 RXD[7:0] RX_CLK

TX_EN TX_ER TXD[7:0] TX_CLK @ 125 MHz

PHY Transmit Rate Adaptation

GMII Signals to 10/100/1000PHY

TX_CLK @ 2.5/25/125 MHz

COL

Figure 2

PHY Functional Block

At the receive side, GMII signals come in at 10/100/1000 Mbps clocked at 2.5/25/125 MHz. The PHY passes these signals through the PHY Receive Rate Adaptation to output the 8-bit data RXD[7:0] in 125MHz clock domain. RXD is sent to the PCS Transmit State Machine to generate an encoded 10-bit segment ENC_RXD[0:9]. The PHY serializes ENC_RXD[0:9] to create RX and sends it to the MAC at 1.25 Gbit/s data rate along with the 625 MHz DDR RXCLK. At the transmit side, the PHY deserializes TX to recover encoded ENC_TXD[0:9]. The PHY passes ENC_TXD[0:9] through the PCS Receive State Machine to recover the GMII signals. In the mean time, Synchronization block checks ENC_TXD[0:9] to determine the synchronization status between links, and to realign if it detects the loss of synchronization.

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The decoded GMII signals have to pass the PHY Transmit Rate Adaptation block to output data segments according to the PHY port speed. To make the PCS layer from 802.3z work properly, the PHY must provide a frame started with at least two preamble symbols followed by a SFD symbol. To be more specic, at the beginning of a frame, RXD[7:0] in Figure 2 shall be {8h55, 8h55, (8h55.....), 8hD5} followed by valid frame data.

Signal Mapping at the MAC Side

Figure 3 shows the MAC functional block diagram. It illustrates how the PCS layer shall be modied and incorporated at the MAC side in the SGMII interface.
MAC
COL CRS
AND

PHY

PCS Layer from 802.3z Figure 36-2

GMII Signals from 10/100/1000PHY

MAC Receive Rate Adaptation

RX_DV RX_ER RXD[7:0] RX_CLK @ 125 MHz

Speed Information

PCS Receive State Machine RX_ER from 802.3z RXD[7:0] Figure 36-7 RX_CLK

RX_DV

ENC_RXD[0:9] 10 DeseriSynchronization alizer Figure 36-9

RX RXCLK

Auto-Negotiation Figure 37-6

GMII Signals to 10/100/1000PHY

MAC Transmit Rate Adaptation

TX_EN TX_ER TXD[7:0] TX_CLK @ 125 MHz

TX_EN TX_ER

Speed Information

PCS Transmit State Machine from 802.3z TXD[7:0] Figure 36-5 Figure 36-6 TX_CLK

TX ENC_TXD[0:9] Seri10

alizer

TXCLK

Figure 3

MAC Functional Block

At the receive side, the MAC deserializes RX to recover encoded ENC_RXD[0:9]. The MAC passes ENC_RXD[0:9] through the PCS Receive State Machine to recover the GMII signals. In the mean time, Synchronization block checks ENC_RXD[0:9] to determine the synchronization status between links, and to realign once it detects the loss of synchronization. The decoded GMII signals have to pass the MAC Receive Rate Adaptation block to output data segments according to the PHY port speed, passed from the PHY to MAC via AutoNegotiation process. At the transmit side, GMII signals come in at 10/100/1000 Mbps data clocked at 2.5/25/125 MHz. The MAC passes these signals through the MAC Transmit Rate Adaptation to output the
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8-bit data TXD[7:0] in 125MHz clock domain. TXD is sent to the PCS Transmit State Machine to generate an encoded 10-bit segment ENC_TXD[0:9]. The MAC serializes ENC_TXD[0:9] to create TX and sends it to the PHY at 1.25 Gbit/s data rate along with the 625 MHz DDR TXCLK.

Control Information Exchanged Between Links

As described in Overview, it is necessary for the PHY to pass control information to the MAC to notify the change of the link status. SGMII interface uses Auto-Negotiation block to pass the control information via tx_cong_Reg[15:0]. If the PHY detects the control information change, it starts its Auto-Negotiation process, switching its Transmit block from data to conguration state and sending out the updated control information via tx_cong_Reg[15:0]. The Receive block in the MAC receives and decodes control information, and starts the MACs Auto-Negotiation process. The Transmit block in the MAC acknowledges the update of link status via tx_cong_Reg[15:0] with bit 14 asserted, as specied in Table 1. Upon receiving the acknowledgement from the MAC, the PHY completes the auto-negotiation process and returns to the normal data process. As specied in Overview, inside the SGMII interface, the Auto-Negotiation link_timer has been changed from 10 msec to 1.6 msec, ensuring a prompt update of the link status. The expected latency for the update of link is 3.4 msec (two link_timer time + an acknowledgement process).

Data Information Transferred Between Links

Below we briey describe at receive side how GMII signals get transferred across from the PHY and recovered at the MAC by using the 8B/10B transmission code. The same method applies to the transmit side. According to the assertion and deassertion of RX_DV, the PHY encodes the Start_of_Packet delimiter (SPD /S/) and the End_Of_Packet delimiter (EPD) to signal the beginning and end of each packet. The MAC recovers RX_DV signal by detecting these two delimiters. The PHY encodes the Error_Propagation(/V/) ordered_set to indicate a data transmission error. The MAC asserts RX_ER signal whenever it detects this ordered_set. CRS is not directly encoded and passed to the MAC. To regenerate CRS, the MAC shall uses signal RX_DV before it is being passed to the MAC Receive Rate Adaptation block as shown in Figure 3. The MAC decodes ENC_RXD[0:9] to recover RXD[7:0]. Bellow Figure 4 illustrates how the MAC samples data in 100 Mbit/s mode. As signals shown in Figure 2, the GMII data in 100 Mbit/s mode get replicated ten times after passing through the PHY Receive Rate Adaptation to generate RXD[7:0]. The modied PCS Transmit State Machine encodes RXD[7:0] to create ENC_RXD[0:9]. As noted in the Overview, the SPD(/S/ ) only appears once per frame. SAMPLE_EN is a MAC internal signal to enable the MAC sampling of data starting at the rst data segment (/S/) once every ten data segments in 100 Mbit/s mode. A note to Figure 4: there is no xed boundary for the data sampling. Also the rst byte of preamble might be only repeated 9/99 instead of 10/100 times due to the algorithm of the 802.3z PCS Transmit State Machine.

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125 MHz Clock RX_DV Data in 100 Mbit/s Domain RXD[7:0] after Rate Adaptation ENC_RXD[0:9] SAMPLE_EN
D0 D0 D0 D0 Data0 Data1 Data2

D0

D0

D0

D0

D0

D0

D1

D1

D1

D1

D1

D1

D1

D1

D1

D1

D2

D2

D2

D2

D2

D2

D2

D2

D2

/S/

d0

d0

d0

d0

d0

d0

d0

d0

d0

d1

d1

d1

d1

d1

d1

d1

d1

d1

d1

d2

d2

d2

d2

d2

d2

d2

d2

d2

Figure 4

Data Sampling in 100 Mbit/s mode

LVDS AC/DC Specication

The basis of the LVDS and termination scheme can be found in IEEE1596.3-1996. Some parameters have been modied to accommodate the 1.25Gb/s requirements. SGMII consists of the most lenient DC parameters between the general purpose and reduced range LVDS. Both the data and clock signals are DC balanced; therefore, implementations that meet the AC parameters but fail to meet the DC parameters may be AC coupled. Figure 5 shows the DDR circuit at the source of the LVDS. The circuit passes data and clock with a 90 degree phase difference. The receiver samples data on both edges of the clock.

Data

Q QN

RX

Q QN

RXCLK 625 MHz DDR Clock

1.25 GHz Clock

Figure 5

Reference data and clock circuit

RXCLK (single ended) RXCLK (differential)

RX (single ended) RX (differential) tclock2q (min) tclock2q (max)

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Driver Clock and Data Alignment July 19, 2001

Symbola Voh Vol Vring |Vod| Vos Ro Ro |Vod| Vos Isa, Isb Isab Ixa, Ixb

Parameterb Output voltage high, Output voltage low Output ringing Output Differential Voltage Output Offset Voltage Output impedance (single ended) Mismatch in a pair Change in Vod between 0 and 1 Change in Vos between 0 and 1 Output current on Short to GND Output current when a, b are shorted Power off leakage current

Min

Max 1525

Units mV mV

875 10 150 1075 40 400 1325 140 10 25 25 40 12 10

% mV mV ohms % mV mV mA mA mA

table 2

Driver DC specication

a. For a detailed description of the symbols please refer to the IEEE1596.3-1996 standard b. All parameters measured at Rload = 100ohms +-1% load
Symbol Vi Vidth Vhyst Rin Parameter Input Voltage range a or b Input differential threshold Input differential hysteresis Receiver differential input impedance Min 675 -50 25 80 120 Max 1725 +50 Units mV mV mv ohms

table 3

Receiver DC specication
Symbola clock tfall trise tskew1b Parameter Clock signal duty cycle @ 625MHz Vod fall time (20%-80%) Vod rise time (20%-80%) Skew between two members of a differential pair - |tpHLAtpLHB| or |tpLHA - tpHLB| Clock to Data relationship: from either edges of the clock to valid data 250 Min 48 100 100 Max 52 200 200 20 Units % pSec pSec pSec

tclock2qc

550

pSec

table 4

Driver AC specication

a. For a detailed description of the symbols please refer to the IEEE1596.3-1996 standard b. Skew measured at 50% of the transition c. Skew measured at 0v differential

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Symbol tsetupa thold

Parameter setup time hold time

Min 100 100

Max

Units pSec pSec

table 5

Receiver AC specication

a. Measured at 50% of the transition

Representative Timing Budget

A transmit and receive path timing budget provided in the table below. The exact allocation of the budget is implementation specic; however, verication of overall requirements are tested against the specications in the tables external to the packaged integrated circuit.
Element Effective clock period Cycle to cycle clock jitter Imperfect duty cycle Data dependent jitter Static package skew Remaining window Value 800 100 30 70 100 500 (250 ps clock2q) Units ps ps peak-peak ps peak-peak ps peak-peak ps peak-peak ps peak-peak

table 6

Timing budget for driver requirements

Element Driver window Static package skew Receiver setup time Remaining window

Value 500 100 100 300

Units ps peak-peak ps peak-peak ps peak-peak ps peak-peak

table 7

Timing budget for receiver requirements

This budget shows the driver generating a data signal with a 500 ps eye centered around the sampling clock edge (see Figure 6 Driver Clock and Data Alignment on page 8). The receiver will add additional skew, leaving 300 ps of margin.

Cisco Systems Intellectual Property

Cisco Systems has released its proprietary rights to information contained in this document for the express purpose of implementation of this specication to encourage others to adopt this interface as an industry standard. Any company wishing to use this specication may do so if they will in turn relinquish their proprietary rights to information contained or referenced herein. Any questions concerning this release should be directed to the Robert Barr, World Wide Patent Counsel, Cisco Systems, 300 East Tasman Drive, San Jose, CA.

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