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    System Memory ARM

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    Nguyên Phong
    The document discusses ARM memory mapping and bit-band operations. It describes the different memory regions for an ARM Cortex M3 including code memory, SRAM, peripherals, external devices, and system regions. It explains how bit-band operations allow accessing individual bits via a separate memory region alias. It also covers using semaphores for shared resources, which requires atomic access via exclusive load and store instructions like LDREX and STREX.

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    © All Rights Reserved
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    System Memory ARM

    Uploaded by

    Nguyên Phong
    89 views15 pages
    The document discusses ARM memory mapping and bit-band operations. It describes the different memory regions for an ARM Cortex M3 including code memory, SRAM, peripherals, external devices, and system regions. It explains how bit-band operations allow accessing individual bits via a separate memory region alias. It also covers using semaphores for shared resources, which requires atomic access via exclusive load and store instructions like LDREX and STREX.

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    System Memory ARM

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    The document discusses ARM memory mapping and bit-band operations. It describes the different memory regions for an ARM Cortex M3 including code memory, SRAM, peripherals, external devices, and system regions. It explains how bit-band operations allow accessing individual bits via a separate memory region alias. It also covers using semaphores for shared resources, which requires atomic access via exclusive load and store instructions like LDREX and STREX.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    89 views15 pages

    System Memory ARM

    Uploaded by

    Nguyên Phong
    The document discusses ARM memory mapping and bit-band operations. It describes the different memory regions for an ARM Cortex M3 including code memory, SRAM, peripherals, external devices, and system regions. It explains how bit-band operations allow accessing individual bits via a separate memory region alias. It also covers using semaphores for shared resources, which requires atomic access via exclusive load and store instructions like LDREX and STREX.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 15

    ARM PROGRAMMING

    Bi Quc Bo

    Memory map

    Cortex M3 have fixed memory map

    BI QUC BO
    1

    System control space

    Can be accessed in privileged mode only

    Code memory region


    Address: 0x000000000x1FFFFFFF
     Executable
    

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    2

    SRAM memory region


    Address: 0x200000000x3FFFFFFF
     Intended for on-chip RAM
     Executable
     Program code can be copied here
    executed.
    

    Peripheral region
    Address: 0x400000000x5FFFFFFF
     Intended for peripherals
     Cannot execute instruction code in this
    region
    

    BI QUC BO
    3

    External RAM region


    Address: 0x600000000x7FFFFFFF
     Intended for either on-chip or off-chip
    memory.
     Program code can be copied here
    executed.
    

    External devices
    Address: 0xA00000000xDFFFFFFF
     intended for external devices and/or
    shared memory that needs ordering /
    nonbuffered accesses
     Cannot execute instruction code in this
    region
    

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    4

    System region
    Address: 0xE00000000xFFFFFFFF
     for private peripherals and vendorspecic devices
     Nonexecutable
    

    Default memory Access Permission

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    5

    Default memory Access Permission

    Bit-band Operation
    Bit-band operation support allows a
    single load/store operation to access
    (read/write) to a single data bit.
     Supported in two predened memory
    regions called bit-band regions
    

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    6

    Bit-band regions
    Can be accessed like normal memory
     Each individual bit can be accessed
    separately via a separate memory region
    called the bit-band alias
    

    Bit-band regions
    

    The rst 1 MB of the SRAM region:


    

    Address: 0x200000000x200FFFFF

    The rst 1 MB of the peripheral region:


    

    0x400000000x400FFFFF

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    7

    Bit-band alias

    Write to bit-band alias

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    8

    Write to bit-band alias


    LDR R0,=0x20000000 ; Setup address
    LDR R1, [R0]
    ; Read
    ORR.W R1, #0x4
    ; Modify bit
    STR R1, [R0] ; Write back result

    LDR R0,=0x22000008 ; Setup address


    MOV R1, #1
    ; Setup data
    STR R1, [R0]
    ; Write

    Read from bit-band alias

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    9

    Read from bit-band alias


    LDR R0,=0x20000000 ; Setup address
    LDR R1, [R0]
    ; Read
    UBFX.W R1,R1, #2, #1 ; Extract bit[2]

    LDR R0,=0x22000008
    LDR R1, [R0]

    ; Setup address
    ; Read

    Remapping of SRAM bit-band


    region

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    10

    Remapping of Bit-Band
    Addresses in Peripheral Memory Region

    Bit-band operation in C
    #define DEVICE_REG0 ((volatile unsigned long *) (0x40000000))
    #define DEVICE_REG0_BIT0 ((volatile unsigned long *) (0x42000000))
    #define DEVICE_REG0_BIT1 ((volatile unsigned long *) (0x42000004))
    ...
    *DEVICE_REG0 = 0xAB; // Accessing the hardware register by normal
    // address
    ...
    *DEVICE_REG0 = *DEVICE_REG0 | 0x2; // Setting bit 1 without using
    // bitband feature
    *DEVICE_REG0_BIT1 = 0x1;
    // Setting bit 1 using bitband feature
    // via the bit band alias address

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    11

    // Convert bit band address and bit number into bit


    band //alias address
    #define BITBAND(addr,bitnum) ((addr &
    0xF0000000) + 0x2000000+((addr & 0xFFFFF) <<5) +
    (bitnum <<2))
    // Convert the address as a pointer
    #define MEM_ADDR(addr) *((volatile unsigned long *)
    (addr))
    #define DEVICE_REG0 0x40000000

    // Accessing the hardware register by normal address


    MEM_ADDR(DEVICE_REG0) = 0xAB;
    // Setting bit 1 without using bitband feature
    MEM_ADDR(DEVICE_REG0) =
    MEM_ADDR(DEVICE_REG0) | 0x2;

    // Setting bit 1 with using bitband feature


    MEM_ADDR(BITBAND(DEVICE_REG0,1)) = 0x1;

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    12

    Semaphore
    

    To use shared resource, semaphore are


    used to manage access.

    Atomic access
    In order to implement a reliable
    semaphore, we must guarantee atomic
    access.
     Reading the semaphore value, checking
    it and writing the modified value back
    must occur in an uninterruptible
    sequence
    

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    13

    Exclusive Load and Store


    

    LDREX
    

    loads data from memory and tag the


    memory location

    STREX
    store data to memory if the memory location
    is tagged, return 0. Otherwise, return 1.
     Every access to this memory location will
    clear the tag
    

    Syntax
     LDREX{cond}
     STREX{cond}
     LDREXB{cond}
     STREXB{cond}
     LDREXH{cond}
     STREXH{cond}
     LDREXD{cond}
     TREXD{cond}

    Rt, [Rn {, #offset}]


    Rd, Rt, [Rn {, #offset}]
    Rt, [Rn]
    Rd, Rt, [Rn]
    Rt, [Rn]
    Rd, Rt, [Rn]
    Rt, Rt2, [Rn]
    Rd, Rt, Rt2, [Rn]

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    14

    cond
    

    Rd

    Rt

    is an optional condition code.


    is the destination register for the returned status.
    is the register to load or store.

    Rt2

    Rn

    offset

    is the second register for doubleword loads or stores.


    is the register on which the memory address is based.
    is an optional offset applied to the value in Rn

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    15

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