1.

BASIC IDEAL & PRACTICAL OP-AMP :

1.1 D 1.2 –4 1.3 C, D 1.4 D 1.5 B
1.6 0.02 1.7 D 1.8 C 1.9 C 1.10 D
1.11 A 1.12 D 1.13 D 1.14 A 1.15 B
1.16 D 1.17 D 1.18 C, D 1.19 D 1.20 D
1.21 D 1.22 A 1.23 B 1.24 C 1.25 A
1.26 B 1.27 B 1.28 B 1.29 D 1.30 B
1.31 D 1.32 A 1.33 C 1.34 D 1.35 B
1.36 C 1.37 C 1.38 B 1.39 A 1.40 B
1.41 A 1.42 A 1.43 B 1.44 B 1.45 B
1.46 C 1.47 A 1.48 B 1.49 B 1.50 C
1.51 B 1.52 A 1.53 B 1.54 C 1.55 B
1.56 A 1.57 D 1.58 B 1.59 A 1.60 A
1.61 B 1.62 A 1.63 C 1.64 C 1.65 B
1.66 C 1.67 D 1.68 B 1.69 0.6 1.70 12
1.71 250 1.72 1 1.73 1.39 1.74 B 1.75 B
1.76 –1 1.77 100 1.78 100 1.79 D 1.80 D
1.81 C 1.82 B 1.83 C 1.84 B 1.85 B

1.6 For the ideal Op-Amp circuit of figure. Determine the output voltage V0
[GATE EC 1993, IIT-Bombay]

99 W
100 W

100 W
V0
4V 100 W

Ans. 0.02 V
Sol. Circuit will reduce as follows
100 W 99 W

V
100 W V V0

4V
100 W
Analog Electronics [EC/EE/EEE/IN] 1-2 GATE ACADEMY ®

Due to virtual ground condition

V  V  V
Apply KCL at non-inverting terminals
V 4 V
 0
100 100
2V 4
  V  2 Volts
100 100
Apply KCL at inverting terminal
V  4 V  V0
 0
100 99
Put V = 2 Volts.
2  4 2  V0
 0
100 99
2  V0 2

99 100
200  100V0  198
100V0  2
V0  0.02 Volt
Rf
1.8 Correction Option (C) 1 
R
1.55 For the Op-Amp circuit shown below, V0 is approximately equal to
[GATE IN 2008, IIT-Bangalore]
10 V

1 MW
105 W 95 W
100 kW

V0

100 kW
95 W 105 W 1 MW

(A) –10 V (B) – 5 V (C) + 5 V (D) + 10 V

Ans. (B)
Sol.
10 V 10 V

1 MW 1 MW
105 W 95 W 105 W 95 W
100 kW 100 kW
I VX
V0 105 W V0
VY
100 kW 100 kW
I2
95 W 105 W 1 MW 95 W 1 MW
I1
GATE ACADEMY ® 1-3 Operational Amplifier

 105 
VX  10    5.25 V
 200 
I  I1  I 2
I1  I 2 [Due to small resistance 95  ]
 95  and 105  will be in series
 95 
VY  10    4.75 V [By VDR]
 200 

1 MW
100 kW
VX
a
b
VY
100 kW Vd » 0
1 MW Vb = Va

Apply KCL at ‘b’

VY  Vb V
 b  10VY  11Vb
100 1000
 10 
Vb    VY  4.31817 Volts
 11 
Apply KCL at ‘a’
VX  Va Va  V0

100 1000
10VX  11Va  V0
V0  11Va  10VX
V0  10(4.31187)  10(5.25)  47.5  52.5
V0   5 V
1.58 The nature of feedback in the Op-Amp circuit shown is [GATE EE 2009, IIT-Roorkee]
+ 6V
1kW 2 kW
-
Vout
+
- 6V
Vin ~

(A) Current - Current feedback (B) Voltage - Voltage feedback

(C) Current - Voltage feedback (D) Voltage - Current feedback
Ans. (B)
Sol. (i) Voltage (sampling) + Series (mixing) feedback
(ii) Series (mixing) + Shunt (sampling) feedback
(iii)Voltage (sampling) + Voltage (mixing) feedback
Analog Electronics [EC/EE/EEE/IN] 1-4 GATE ACADEMY ®

1.71 In the circuit shown, assume that the Op-Amp is ideal. The bridge output voltage V 0 (in mV) for
  0.05 is______________. [GATE EC 2015 (Set-01), IIT-Kanpur]
100W
+ 1V
-
250(1 + d)Ω 250(1 - d)Ω

- +
V0

250(1 - d)Ω 250(1+d)Ω

100W 50W

Ans. (250)
Sol.
100W
+ 1V
-
250(1 + d)Ω 250(1 - d)Ω

1 - + 1
A V0 A
100 100
250(1 - d)Ω 250(1+d)Ω
100W
1V
1
1 50W A
A 50
50

Due to virtual ground concept

V  V  1V
Current in 100  and 50  resistor will be same
1
I50   I100   A
50
So, output voltage is given by,
1 1
V0   250(1  )  250(1  )   500
100 100
V0  5   0.05  0.25 V
V0  250 mV
1.73 In the figure shown, RT represents a resistance temperature device (RTD), whose characteristic is given
by RT  R0 (1  T ) , where R0  100 ,   0.00390 C 1 and T denotes the temperature in 0 C . Assuming
the op-amp to be ideal, the value of V0 in volts when T  1000 C , is __________V.
[GATE IN 2015, IIT-Kanpur]
+1 V

RT V0

100 W

Ans. (1.39 V)
GATE ACADEMY ® 1-5 Operational Amplifier

Sol.
+1 V

RT V0

1V by VGC
I
100 W

Given :   0.00390 C 1 , R0  100, T  1000 C

RT  R0 (1  T )  100(1  0.0039 100)
RT  139 
1
I A
100
1
V0  I  RT  139 
100
V0  1.39 V
1.76 In the circuit given below, the OP-AMP is ideal. The output voltage V0 in volt is ________.
[GATE IN 2016, IISc Bangalore]
20 kW

20 kW
10 kW
2V
V1 V0
20 kW
10 kW

V1  2 V1 V1
Sol.   0
20 20 10
V1  0.5 V
20
V0   0.5  1V
10
1.77 In the circuit given below, the OP-AMP is ideal. The input vx is a sinusoid. To ensure v y  v x , the value
of C N in picofarad is _________ [GATE IN 2016, IISc Bangalore]
10 kW

1kW

vy
vx
1kW
1nF
CN

Sol. Appling KCL at inverting terminal,

Vy  0 Vy  V0
 0
1k 10 k
Vy Vy V0
 
1 10 10
V0  11 V y … (i)
Analog Electronics [EC/EE/EEE/IN] 1-6 GATE ACADEMY ®

Applying KCL at non-inverting terminal,

Vy  Vx Vy Vy  V0
  0
1 k 1 1
sC sCN
V y .sC  (V y  11 V y ).sC N  0
V y .sC  10V y .sC N  0
V y .sC  10 V y .sC N
C
CN   0.1 nF  100 pF
10
1.78 In the circuit given below, the OP-AMP is ideal. The value of current I L in microampere is ______
[GATE IN 2016, IISc Bangalore]
100 kW

100 kW

1V
10 kW
10 kW
IL
RL

Sol. Applying KCL at inverting terminal,

V  0 V  V0 100 kW
 0
100 K 100 K
100 kW V
2V V0

100 K 100 K
1V
V0  2V 10 kW V

Applying KCL at non inverting, IL 10 kW

V 1 V  V0 RL
 IL  0
10 K 10 K
V 1 V
  IL  0
10 K 10 K 10 K
I L  0.1mA  100 A
1.81 In an Op-Amp, if the feedback voltage is reduced by connecting a voltage divider at the output, which
of the following will happen? [IES EC 2016]
1. Input impedance increases
2. Output impedance reduces
3. Overall gain increases
Which of the above statements is/are correct?
(A) 1 only (B) 2 only (C) 3 only (D) 1, 2 and 3
Ans. (C)
Sol.
1
Vf ¯ b¯ Af » ­
b
GATE ACADEMY ® 1-7 Operational Amplifier

2. OP-AMP APPLICATION (ADDER / SUBTRACTOR) :

2.1 C 2.2 1 2.3 D 2.4 A 2.5 C
2.6 B 2.7 B 2.8 A 2.9 D 2.10 C
2.11 C 2.12 A 2.13 B 2.14 B 2.15 C
2.16 A 2.17 B 2.18 C 2.19 D 2.20 C
2.21 B 2.22 B 2.23 C 2.24 B 2.25 C
2.26 C 2.27 B 2.28 1.5 2.29 15

2.5 The differential input resistance of the circuit shown in figure is [GATE IN 1996, IISc-Bangalore]
Rf
V1 R1

Vi V0

V2 R1
Rf

(A) R1 (B) R1 /2 (C) 2R1 (D) R f

Ans. (C)
Sol.
Rf
Rf I V1 R1
Voltage at node ‘b’, Vb   V2 a
R1  R f Vd V0
b
For ideal Op-Amp, V  V I V2 R1
Rf Rf
 Va  Vb   V2
R1  R f
Va  V1
Current supplied by source, I 
R1
Vd
Differential input resistance, Rd 
I
Rf
 V2  V1
R1  R f
I
R1
V V
For differential input, V1  d , V2  d
2 2
1 Rf 1
    V1
 2 R1  R f 2 
I
R1
Vd 2 R1 ( R1  R f )
  2 R1
I R1  2 R f
2.25 Correction option (C)  4 cos t V
2.29 An ideal op-amp has voltage sources V1 , V3 , V5 ,......, VN 1 connected to the non-inverting input and
V2 , V4 , V6 ,......, VN connected to the inverting input as shown in the figure below (  VCC = 15 volt,
 VCC = −15 volt). The voltages V1 , V2 , V3 , V4 , V5 , V6 ,...... are 1, − 1/2, 1/3, −1/4, 1/5, −1/6, .… volt,
respectively. As N approaches infinity, the output voltage (in volt) is ___________.
[GATE EC 2016 (Set - 01), IISc Bangalore]
Analog Electronics [EC/EE/EEE/IN] 1-8 GATE ACADEMY ®

10 kW
V2
10 kW 10 kW
V4

10 kW + VCC
VN
V0

1kW - VCC
V1
1kW 1kW
V3

1kW
VN -1

Ans. 15
Sol.
10 kW
V2
10 kW 10 kW
V4

10 kW + VCC
VN
VB V0
1kW
V1
1kW - VCC
V3 VA

1kW 1kW
VN -1

Apply nodal analysis at node A,

VA  V1 VA  V3 V  VN 1 V
  .....  A  A 0
1 k 1 k 1 k 1 k
N 
VA   1  V1  V3  .....VN 1
2 
 VB  VA [ Virtual ground concept]
Apply nodal analysis at node B,
VA  V2 VA  V4 V  VN VA  V0
  ..... A   0 [We used VB  VA ]
10 k 10 k 10 k 10 k
N 
V0  VA   1  (V2  V4  V6  .....VN )
2 
 N  (V  V  .....VN 1 )
V0    1 1 3  (V2  V4  V6  .....VN )
2  N 
  1
2 
1 1 1
V0  V1  V2  V3  V4  .....  1     .....
2 3 4
1
V0    
N
Output of op-amp goes to saturation
V0  Vsat  VCC  15 Volt
Hence, the correct answer is 15.
GATE ACADEMY ® 1-9 Operational Amplifier

3. OP-AMP APPLICATION (COMPARATOR / SCHMITT TRIGGER) :

3.1 D 3.2 D 3.3 D 3.4 A 3.5 A
3.6 D 3.7 A 3.8 B 3.9 B 3.10 A
3.11 B 3.12 A 3.13 B 3.14 A 3.15 D
3.16 B 3.17 C 3.18 D 3.19 A 3.20 C
3.21 C 3.22 B 3.23 C 3.24 D 3.25 D
3.26 D 3.27 D 3.28 C 3.29 D 3.30 8.10
3.31 1 3.32 A 3.33 B 3.34 0.67 3.35 D

3.9 Correction Diagram :

+10 V

10 kW

47 kW
–10 V
Vin
1k W Vout

Vg = 0.7 V

Ans. (B)
Sol. For increasing input voltage if Vout  10 V then triggering voltage using superposition
1 47
  10   0.7  0.893 V
48 48
3.15 Shows a Schmitt trigger circuit and the corresponding hysteresis characteristics. The values of VTL and
VTH are [GATE IN 2004, IIT-Delhi]
+ 10 V + 10 V
_
V0
+
-10 V
5 kW
-10 V
Vi + 10 kW
–
VTL VTH

(A) VTL  3.75 V, VTH  3.75 V (B) VTL  1 V, VTH  5 V

(C) VTL  5 V, VTH  1 V (D) VTL  5 V, VTH  5 V
Ans. (D)
Sol. Given circuit is shown below.
+ 10 V
_
V0
+
-10 V
5 kW

Vi + 10 kW
–
Analog Electronics [EC/EE/EEE/IN] 1 - 10 GATE ACADEMY ®

NON-INVERTING SCHMITT TRIGGER CIRCUIT

R2

R1
v+ Vout
Vin +-

Op-amp with positive feedback act as a comparator and input is given to non-inverting terminal. So
this is a non-inverting Schmitt trigger circuit.
Voltage v is given by,
V R V R
v   in 2  out 1
R1  R2 R1  R2
When Vout   VCC ,
Vin R2 V R
Then v   V1   CC 1
R1  R2 R1  R2
Again Vout  VCC if v   0
Vin R2 V R
i.e.  CC 1  0
R1  R2 R1  R2
R
Vin  VCC 1 …… (i)
R2
When Vout   VCC
V R V R
Then v   V2  in 2  CC 1
R1  R2 R1  R2
Again Vout   VCC if v   0
Vin R2 V R
 CC 1  0
R1  R2 R1  R2
V R
Vin  CC 1 …… (ii)
R2
Transfer characteristics is shown below. Vout

Vin
V R V R VTL VTH
Where VTH  CC 1 and VTL  CC 1 VH
R2 R2
Hysteresis is given by,
V R  V R 
VH  VTH  VTL  CC 1   CC 1 
R2  R2 
R1
VH  2VCC
R2
VCC R1 10  5
VTH   5 V
R2 10
 VCC R1 10  5
VTL    5 V
R2 10
GATE ACADEMY ® 1 - 11 Operational Amplifier

3.17 In the given figure, if the input is a sinusoidal signal, the output will appear as shown in
[GATE EE 2005, IIT-Bombay]

(A) (B)

(C) (D)

Ans. (C)
Sol.
+V
R _

+
+
Protecting diodes RL Vout
R –V
_

Protecting diodes are used to protect the Op-Amp form the damage due to application of high
voltage.
This is an open loop system so Op-Amp behaves as a comparator.
For positive half cycle, I  NI
 V0   Vsat
For negative half cycle, NI  I
 V0   Vsat
3.22 The input signal shown in the figure below is fed to a Schmitt trigger. The signal has a square wave
amplifier of amplitude of 6 V p-p. It is corrupted by an additive high frequency noise of amplitude 8
V p-p. [GATE IN 2007, IIT-Kanpur]
Vi
7V
Noise
Square Wave

8V
3V

1V
6V
t
-1 V

-3 V

-7 V
Analog Electronics [EC/EE/EEE/IN] 1 - 12 GATE ACADEMY ®

Which one of the following is an appropriate choice for the upper and lower trip points of the Schmitt
trigger to recover a square wave of the same frequency from the corrupted input signal Vi ?
(A)  8.0 V (B)  2.0 V (C)  0.5 V (D) 0 V
Ans. (B)
Sol.
Vi
7V
Noise
Square Wave to
be recovered
8V
3V

1V
6V
t
-1 V

-3 V
T

-7 V

The above corrupted signal is given as an input to Schmitt trigger circuit.

+ Vsat
Vi
V0

- Vsat
VT
R1
R2

Operation of Schmitt trigger :

For Vi  VUTP  V0 switches from Vsat to  Vsat
For Vi  VLTP  V0 switches from Vsat to  Vsat
Calculation of Trip point voltage :
V R
VT  0 2 [By VDR]
R1  R2
When V0   Vsat
VT  VUTP  upper trip point
V  R2
 VUTP  sat …… (i)
R1  R2
When V0   Vsat
VT  VLTP  lower trip point
 V  R2
 VLTP  sat …… (ii)
R1  R2
From equation (i) and (ii), we can conclude that both VUTP and VLTP are lesser in magnitude than Vsat
for proper operation.
Since the signal to be recovered is square wave of peak amplitude of +3 V. we should adjust the  Vsat
in such a way that it is equal to  3V . (As output of Schmitt trigger is  Vsat ) therefore the VUTP and
VLTP will have magnitude less than 3 V.
GATE ACADEMY ® 1 - 13 Operational Amplifier

So, option (A)  8 V is straight forwardly rejected. So now we are left with option (B), (C) and (D).
Consider option (C)  0.5 V
Vi
7V

8V
3V
VUTP = + 0.5 V
0.5 V 6V
t (s)
- 0.5 V
VLTP = - 0.5 V
-3 V
T

-7 V
V0
+Vsat

t (s)

-Vsat

Key Point : Multiple triggering occurs if we select VUTP or VLTP  1 V . So we can’t recover square
wave with same frequency because due to noise frequency will change.
Consider option (B)  2 V
Vi
7V
At VUTP
+Vsat to –Vsat

8V
3V
2V VUTP = + 2 V
1V
6V
t (s)
-1 V
-2 V VLTP = - 2 V
-3 V
T At VLTP
–Vsat to +Vsat

-7 V
V0
+Vsat = + 3 V

t (s)

-Vsat = - 3 V
T
Key Point : For VUTP or VLTP  1 V we get square wave same as input square wave.
So, VUTP  2 V and VLTP  2 V satisfies all the required conditions for recovery of square wave
with same frequency.
Hence, the correct option is (B).
Analog Electronics [EC/EE/EEE/IN] 1 - 14 GATE ACADEMY ®

3.31 In the bistable circuit shown, the ideal Op-Amp has saturation levels of  5 V . The value of R1
(in k ) that gives a hysteresis width of 500 mV is _____. [GATE EC 2015 (Set-02), IIT-Kanpur]
R2 = 20 kΩ

R1

Vout
Vin +-

Ans. 1
Sol. Given circuit is shown below.
R2 = 20 kΩ

R1
v+ Vout
Vin +-

Op-amp with positive feedback at as a comparator.

V R V R
Voltage v  is given by, v   in 2  out 1
R1  R2 R1  R2
When Vout   VCC ,
Vin R2 V R
Then v   V1   CC 1
R1  R2 R1  R2
Again Vout  VCC if v   0
Vin R2 V R
i.e.  CC 1  0
R1  R2 R1  R2
R
Vin  VCC 1 …… (i)
R2
When Vout   VCC
Vin R2 V R
Then v   V2   CC 1
R1  R2 R1  R2
Again Vout   VCC if v   0
Vin R2 V R
 CC 1  0
R1  R2 R1  R2
V R
Vin  CC 1 …… (ii)
R2
Transfer characteristics is shown below.
Vout

Vin
V2 V1
VH
GATE ACADEMY ® 1 - 15 Operational Amplifier

VCC R1 V R
Where V1  and V2  CC 1
R2 R2
Hysteresis is given by,
VCC R1  VCC R1 
VH  V1  V2   
R2  R2 
R1
VH  2VCC
R2
Given : VH  0.5 V
R1
2 5  0.5
20
R1  1 k
4. OP-AMP APPLICATION (INTEGRATOR / DIFFERENTIATOR / ACTIVE FILTER /
FREQUENCY RESPONSE) :
4.1 A 4.2 D 4.3 C 4.4 C 4.5 A
4.6 A 4.7 D 4.8 B 4.9 * 4.10 C
4.11 D 4.12 C 4.13 D 4.14 A 4.15 C
4.16 C 4.17 A 4.18 A 4.19 D 4.20 B
4.21 A 4.22 D 4.23 A 4.24 A 4.25 A
4.26 A 4.27 D 4.28 A 4.29 C 4.30 C
4.31 B 4.32 C 4.33 D 4.34 D 4.35 A
4.36 D 4.37 D 4.38 D 4.39 C 4.40 B
4.41 A 4.42 A 4.43 D 4.44 B 4.45 A
4.46 3.1-3.26 4.47 A 4.48 15-16 4.49 159.15 4.50 D
4.51 A 4.52 1.245 4.53 B 4.54 C 4.55 D
4.56 –1 4.57 A 4.58 44.37 4.59 2.95
4.9 (A - R, B - S, C - P)
d 2V dV
4.2 In the following circuit, the output ‘V’, follows an equation of the form 2
 a  bV  f (t ) . The
dt dt
value of a, b and f (t ) are respectively [GATE EE 1992, IIT-Delhi]
C
C
R
R

V
R
R

R
et
Analog Electronics [EC/EE/EEE/IN] 1 - 16 GATE ACADEMY ®

1 1
, b  2 2 , f (t )  2 2  1 
1 1  t
(A) a  e
2RC 2R C 2R C  RC 
1 1
, b  2 2 , f (t )  2 2  1 
1 1  t
(B) a  e
2RC 2R C R C  RC 
1 1
, b  2 2 , f (t )  2 2  1 
1 1  t
(C) a  e
RC 2R C 2 R C  RC 
1 1
, b  2 2 , f (t )  2 2  1 
1 1  t
(D) a  e
2RC 2R C 2 R C  RC 
Ans. (D)
Sol. Solve the circuit in parts
C

R
V1
V2

Above circuit is an integrator.

1
RC 
Output V2  V1dt

dV
Or V1   RC 2 …… (i)
dt
C

R
V2
V

1
RC 
Output V V2 dt

dV
Or V2   RC …… (ii)
dt
C

V3 V1
V2
R
R

et
(V2  et )
V3 
2
d
And RC (V1  V3 )  V3
dt
GATE ACADEMY ® 1 - 17 Operational Amplifier

Or RC (V1  V3 )   V3 dt

1 
RC (V1  V3 )  et   V2 dt 
2 
 d  dV   V2  e   1  t
t
Or RC   RC   RC 
      e   V2 dt 
 dt  dt   2  2

 d 2V 1 1 dV   1 t
RC  R 2C 2 2  et    RC    e  RCV 
 dt 2 2 dt   2 

 2 2 d 2V 1 dV  1 t 1 t 1
R C 2
 RC  e  e  V
 dt 2 dt  2 2 RC 2

d 2V 1 dV 1 et  1 
Or 2
RC 2
2
 RC  V  1  
dt 2 dt 2 2  RC 
Compare with
d 2V dV
2
 a  bV  f (t )
dt dt
1 1
, b  2 2 , f (t )  2 2  1 
1 1  t
a e
2RC 2R C 2 R C  RC 
4.27 For the circuit shown in the following figure, the capacitor C is initially uncharged. At t = 0 the switch
S is closed. The voltage VC across the capacitor at t  1msec is [GATE EC 2006, IIT - Kharagpur]

In the figures shown the OP-AMP is supplied with  15 V .

(A) 0 V (B) 6.3 V (C) 9.45 V (D) 10 V
Ans. (D)
Sol.
S C = 1μF
_V
ic c+
1kW _

+
10 V

Above figure represents the linear charging of capacitor. Here transient equation is not valid.
After closing the switch apply KCL at non-inverting terminals.
Analog Electronics [EC/EE/EEE/IN] 1 - 18 GATE ACADEMY ®

Due to virtual ground

V  V  10 V
10
ic 
1k
dV 10
c c 
dt 1k
106  Vc 10

1 103 103
Vc  10 Volt
4.28 and 4.29 Common data Correction diagram
R

R _
Vi V0
+
R
C

4.39 The ideal Op-Amp based circuit shown below acts as a [GATE IN 2011, IIT-Madras]
1MW 1MW 0.5 mF 0.5 mF

500 kW
Vi 1mF –
+
V0

(A) low-pass filter (B) high-pass filter

(C) band-pass filter (D) band-reject filter
Ans. (C)
Sol. . Method 1 :
C /2 C /2
R Va R Vb Vc
a b c
R /2
Vi C –
+
V0

R = 1 MW
C = 0.5 mF
The type of filter can be determined from the transfer function of circuit in s-domain. So transfer`
function of circuit will be obtained first. From which conclusion will be draw about type of filter.
KCL at node (a),
Va  Vi Va  Vb Va  0
 
R R 1 / sC
As node ‘b’ is at virtual ground, so Vb  0
2  V
Va   sC   i
R  R
Vi
Va  …… (i)
2  sCR
GATE ACADEMY ® 1 - 19 Operational Amplifier

KCL at node (b),

0  Va 0  Vc
 0
R 2 / sC
sCR
Va   Vc ……. (ii)
2
From equation (i) and (ii), we have
sCR 1
 Vc  Vi
2 2  sCR
2
Vc    Vi …… (iii)
sCR(2  sCR)
KCL at node (c),
Vc  0 V V V
 c  c 0 0
2 / sC R / 2 2 / sC
 2  sCV0
Vc  sC   
 R 2
sCR
Vc  V0 …… (iv)
2(2  sCR)
From equation (iii) and (iv), we have
sCR 2
V0    Vi
2(2  sCR) sCR(2  sCR)
V0 4

Vi ( sCR)2
In frequency domain, s  j
V0 4
  2
Vi  CR
Gain of circuit reduces as  increases so given filter like low pass filter.
. Method 2 :
At low frequency f  0, X C  , C  O.C.
1MW 1MW

Vi –
+
V0

This is an open loop system. So, Op-Amp behaves as a comparator.

 if Vi  0  V0   Vsat
If Vi  0  V0   Vsat
In this case V0  Vsat  finite gain
At high frequency f  , X C  0, C  S.C.
1MW 1MW

500 kW

Vi –
+
V0

Here V0  0 (Due to virtual ground)

So, this circuit act as a low pass filter.
Analog Electronics [EC/EE/EEE/IN] 1 - 20 GATE ACADEMY ®

4.42 The following circuit has R  10 k , C  10 F The input voltage is a sinusoidal at 50Hz with an rms
value of 10 V. under ideal conditions, the current is from the source is
[GATE EE 2009, IIT-Roorkee]
R
10 kW
iS
+
OPAMP Vo
~ -
10 kW
C R
10 mF

(A) 10 mA leading by 900 (B) 20 mA leading by 900

(C) 10 mA leading by 900 (D) 10 mA lagging by900
Ans. (A)
 Xc 
Sol. Vs    V0
 R  X c  10 kW
j
Where Xc  iS
C
+
 R  Xc  OPAMP Vo
Vs    Vs ~ Vs -
V V  Xc 
and is  s 0  10 kW
R R
 RVs C = 10 mF
is    Vs jC
RX c
is   j (2   50  10  10 6 )
is   j10 mA
So, 10 mA lagging by 900 .
4.53 The filters F1 and F2 having characteristics as shown in figure (a) and (b) are connected as shown in
figure (c). [GATE EE 2015 (Set-02), IIT-Kanpur]
F1 F2
V0 V0
Vi Vi
Vi V0 Vi V0

f f
f1 f2

(a) (b)
R
2
+Vsat
R
F1 –
Vi +
V0
F2 -Vsat
R
(c)
GATE ACADEMY ® 1 - 21 Operational Amplifier

The cut-off frequencies of F1 and F2 are f1 and f 2 respectively. If f1  f2 , the resultant circuit exhibits
the characteristic of a
(A) Band-pass filter (B) Band-stop filter (C) All pass filter (D) High-Q filter
Ans. (B)
Sol. The given circuit represents F1 as LPF & F2 as HPF in parallel followed by a buffer.
LPF will pass all the frequencies less than f1 and HPF pass all the frequencies above f 2 .
R
2
+Vsat
R
F1 –
Vi +
V0
F2 VA -Vsat
R

Since f1  f 2 ; frequencies lying between f1 and f 2 will be stopped.

Since f1  f 2 , so VA / Vi will be
VA /Vi

From figure V0  Va (voltage follower circuit)

V0 Va
So 
Vi Vi
V0 / Vi will be
V0 /Vi

Hence the circuit behaves like a band stop filter.

