Training F4 V1.3 PDF

STM32 F4 Seminar and Hands-On
Exercises
Hands On
Ensure you picked-up
DVD with STM32 F4 Discovery Kit Contents
USB Cable
STM32F4-Discovery Kit will be provided after software is loaded
Welcome
Overview of the STM32 Portfolio
Introducing the STM32 F4 Series
Installation
The STM32 F4 Part 1: Cortex-M4
Bruno Montanari
Cicero Pompeu
The STM32 F4 Part 2: System and Peripherals
Hands-on Training
STM32 Firmware and Development Tools
Questions and Answers
Agenda
Speaker Presentation
2
CONTENTS
Objectives
STM32 F-4 Series
Series highlights at glance
Block Diagram / Boot modes
System Architecture
System Architecture and Performance
STM32F4xx vs STM32F10x/STM32F2xx
STM32F4xx Peripherals / Tool Installation
Main features
OBJECTIVES
Get you familiar with the STM32F4 product series through
The STM32F4 product presentation and show you the embedded
high performance features.
Cortex-M4 Hands On training
Q/As
At the end of the training you will be able to
Understand all the STM32F4 new product features
Install dev tools and run demos and peripheral examples
4
CONTENTS
Objectives
STM32F4 Series
System Architecture
Main features
Presentation highlights
The STM32 F4 series brings to the market the worlds
highest performance Cortex-M microcontrollers
168 MHz F
CPU
/210 DMIPS
363 Coremark score
The STM32 F4 series extends the STM32 portfolio
350+ compatible devices already in production, including
the F0, F1, F2 series and ultra-low-power L1 series
The STM32 F4 series reinforces STs current leadership in
Cortex-M microcontrollers, with 45% world market share
by units in (2010 or cumulated 2007 to Q1/11) according to
ARM reporting
STM32 F4 portfolio
2
STM32 product series
4 product series
STM32 leading Cortex-M portfolio
10
STM32 F4 Series highlights 1/4
ST is introducing STM32 products based on Cortex M4
core. Over 30 new part numbers pin-to-pin and
software compatible with existing STM32 F2 Series.
The new DSP and FPU instructions combined to
168Mhz performance open the door to a new level of
Digital Signal Controller applications and faster
development time.
STM32 Releasing your creativity
11
Advanced technology and process from ST:
Memory accelerator: ART Accelerator
Multi AHB Bus Matrix
90nm process
Outstanding results:
210DMIPS at 168Mhz.
Execution from Flash equivalent to 0-wait state
performance up to 168Mhz thanks to START
Accelerator
12
More Memory
Up to 1MB Flash,
192kB SRAM: 128kB on bus matrix + 64kB (Core Coupled
Memory) on data bus dedicated to the CPU usage
Advanced peripherals shared with STM32 F2
Series
USB OTG High speed 480Mbit/s
Ethernet MAC 10/100 with IEEE1588
PWM High speed timers: Now 168Mhz max frequency!
Crypo/hash processor, 32-bit random number generator (RNG)
32-bit RTC with calendar: Now with sub 1 second accuracy, and
<1uA typ!
13
Further improvements
Low voltage: 1.8V to 3.6V VDD , down to 1.7*V on most
packages
Full duplex I2S peripherals
12-bit ADC: 0.41s conversion/2.4Msps (7.2Msps in
interleaved mode)
High speed USART up to 10.5Mbits/s
High speed SPI up to 37.5Mbits/s
Camera interface up to 54MBytes/s
*external reset circuitry required to support 1.7V
STM32 F4 block diagram
Feature highlight
168 MHz Cortex-M4 CPU
Floating point unit (FPU)
ART Accelerator
TM
Multi-level AHB bus
matrix
1-Mbyte Flash,
192-Kbyte SRAM
1.7 to 3.6 V supply
RTC: <1 A typ, sub second
accuracy
2x full duplex IS
3x 12-bit ADC
0.41 s/2.4 MSPS
168 MHz timers
Cortex-M processors binary compatible
Cortex-M feature set comparison
16
Cortex-M0 Cortex-M3 Cortex-M4
Architecture Version V6M v7M v7ME
Instruction set architecture Thumb, Thumb-2
System Instructions
Thumb + Thumb-2 Thumb + Thumb-2,
DSP, SIMD, FP
DMIPS/MHz 0.9 1.25 1.25
Bus interfaces 1 3 3
Integrated NVIC Yes Yes Yes
Number interrupts 1-32 + NMI 1-240 + NMI 1-240 + NMI
Interrupt priorities 4 8-256 8-256
Breakpoints, Watchpoints 4/2/0, 2/1/0 8/4/0, 2/1/0 8/4/0, 2/1/0
Memory Protection Unit (MPU) No Yes (Option) Yes (Option)
Integrated trace option (ETM) No Yes (Option) Yes (Option)
Fault Robust Interface No Yes (Option) No
Single Cycle Multiply Yes (Option) Yes Yes
Hardware Divide No Yes Yes
WIC Support Yes Yes Yes
Bit banding support No Yes Yes
Single cycle DSP/SIMD No No Yes
Floating point hardware No No Yes
Bus protocol AHB Lite AHB Lite, APB AHB Lite, APB
CMSIS Support Yes Yes Yes
51/82/114/140 I/Os
USB 2.0 OTG
FS/HS
Encryption**
Camera Interface
3x 12-bit ADC
24 channels / 2Msps
3x I
2
C
Up to 16 Ext. ITs
Temp Sensor
2x6x 16-bit PWM
Synchronized AC Timer
2x Watchdog
(independent & window)
5x 16-bit Timer
XTAL oscillators
32KHz + 8~25MHz
Power Supply
Reg 1.2V
POR/PDR/PVD
2x DAC + 2 Timers
2 x USART/LIN
1 x SPI
1 x Systic Timer
PLL
Clock Control
RTC / AWU
4KB backup RAM
Ethernet MAC
10/100, IEEE1588
USB 2.0 OTG FS
4x USART/LIN
1x SDIO
Int. RC oscillators
32KHz + 16MHz
3 x 16bit Timer
2x 32-bit Timer
2x CAN 2.0B
2 x SPI / I2S
HS requires an external PHY connected to ULPI interface,
** Encryption is only available on STM32F415 and STM32F417
17
STM32F4xx Block Diagram
Cortex-M4 w/ FPU, MPU and ETM
Memory
Up to 1MB Flash memory
192KB RAM including 64KB CCM
data RAM
FSMC up to 60MHz
New application specific peripherals
USB OTG HS w/ ULPI interface
Camera interface
HW Encryption**: DES, 3DES, AES
256-bit, SHA-1 hash, RNG.
Enhanced peripherals
USB OTG Full speed
ADC: 0.416s conversion/2.4Msps,
up to 7.2Msps in interleaved triple
mode
ADC/DAC working down to 1.8V
Dedicated PLL for I2S precision
Ethernet w/ HW IEEE1588 v2.0
32-bit RTC with calendar
4KB backup SRAM in VBAT domain
Pure 1% RC
2 x 32bit and 8 x 16bit Timers
high speed USART up to 10.5Mb/s
high speed SPI up to 37.5Mb/s
RDP (JTAG fuse)
More I/Os in UFBGA 176 package
A
R
M

3
2
-
b
i
t

m
u
l
t
i
-
A
H
B

b
u
s

m
a
t
r
i
x

A
r
b
i
t
e
r

(
m
a
x

1
5
0
M
H
z
)
F
l
a
s
h

I
/
F
CORTEX-M4
CPU + FPU +
MPU
168 MHz
128KB SRAM
JTAG/SW Debug
DMA
16 Channels
Nested vect IT Ctrl
Bridge
Bridge APB1 (max 42MHz)
ETM
512kB- 1MB
Flash Memory
External Memory External Memory
Interface
AHB1
(max 168MHz)
AHB2 (max 168MHz)
A
P
B
2

(
m
a
x

8
4
M
H
z
)
64KB CCM data RAM
D-bus
I-bus
S-bus
Innovative system Architecture
SRAM1
112KB
SRAM1
112KB
SRAM2
16KB
SRAM2
16KB
FSMC FSMC
AHB2 AHB2
Multi-AHB Bus Matrix
A
R
T
A
c
c
e
l
e
r
a
t
o
r
A
R
T
A
c
c
e
l
e
r
a
t
o
r
CORTEX-M4
168MHz
w/ FPU & MPU
Master 1
CORTEX-M4
168MHz
w/ FPU & MPU
Master 1
D
-
B
u
s
S
-
B
u
s
I-Code
D-Code
Dual Port
DMA2
Master 3
Dual Port
DMA2
Master 3
FIFO/8 Streams FIFO/8 Streams
AHB1 AHB1
Dual Port
AHB1-APB1
Dual Port
AHB1-APB1
Dual Port
AHB1-APB2
Dual Port
AHB1-APB2
FLASH
1Mbytes
FLASH
1Mbytes
Dual Port
DMA1
Master 2
Dual Port
DMA1
Master 2
FIFO/8 Streams FIFO/8 Streams
CCM
data RAM
64KB
CCM
data RAM
64KB
18
High Speed
USB2.0
Master 4
High Speed
USB2.0
Master 4
FIFO/DMA FIFO/DMA
Ethernet
10/100
Master 5
Ethernet
10/100
Master 5
FIFO/DMA FIFO/DMA
I
-
B
u
s
System Architecture DMA transfers
DMA1 transfers
DMA1 periph bus is not connected to the bus matrix
DMA1 can not address AHB1/AHB2 peripheral
DMA1 can only do APB1 from/to Memory transfers
DMA2 transfers
DMA2 can do all possible transfers
Both DMA2_periph and DMA2_mem buses are connected to the bus
Matrix.
System b/w divided when the read and write data path are shared
DMA can only access to 128KB main SRAM memory
(64KB CCM RAM is only accessed by the CPU).
Use DMA transfers as much as possible to offload the
CPU.
19
System Architecture Flash performance
F
E
T
C
H
-M4
with FPU & MPU
Up to
168MHz
I-32-bit
At 3WS -120MHz, it takes
4 cycles to fetch 128-bit
instruction from flash.
But at the 5
th
sequential
instruction requested, the
CPU has to wait for 4
more cycles before it can
fetch the next 4
instructions from flash.
FLASH
I1- 32-bit
I2- 32-bit
I3- 32-bit
I4- 32-bit
I5- 32-bit
128-bit
20
21
STs ART Accelerator
The adaptive real-time memory accelerator unleashes the Cortex-M4 cores
maximum processing performance equivalent to 0-wait state execution
Flash up to 168 MHz
System Architecture Role of the ART accelerator
1/2
I-32-bit
PFQ collects in advance the next
128-bit instructions from flash
while I-bus fetches data from the
current buffer line
PFQ clk
No more CPU stall in the execution
of sequential code
4x32-bit / 8x16-bit
buffer
PFQ
128-bit
FLASH
I1- 32-bit
I2- 32-bit
I3- 32-bit
I4- 32-bit
CPU clk
23
F
E
T
C
H
-M4
with FPU & MPU
Up to
168MHz
24
System Architecture Role of the ART accelerator
2/2
FLASH
I1- 32-bit
I2- 32-bit
I3- 32-bit
I4- 32-bit
I-32-bit
128-bit
Branch Cache stores the 64 LRU
branches and feeds the CPU
without latency in case of a Hit.
4x32-bit buffer
8x16-bit buffer
PFQ
What if a branch occurs?
8 rows of
128-bit -D
BC
Branch Cache stores 8 rows of
128-bit data (literals)
D
-
3
2
-
b
i
t
64 rows of
128-bit-I
BC
25
F
E
T
C
H
-M4
with FPU & MPU
Up to
168MHz
STM32F4 versus competitors (Coremark)
Fcpu
(MHz)
STM32 F4
Max system
frequency
Coremar
k
100
200
300
250
150
50
40 20 80 140 60 100 120 160
350
Competitor R
Max flash frequency
Max system frequency
Competitor F
Max flash
frequency
STM32 F4
Max flash
frequency Competitor A
0
Competitor N
Max system
frequency
Good Acceleration but
limited 100MHz speed
For this CM4
Good CPU, fast flash but
No acceleration, limited speed
All the results are with the best compiler for each MCU
150MHz but less
Acceleration
For this CM4
400 Best acceleration and highest speed
STM32F4
180
26
STM32F4 versus competitors (Dhrystone 2.1)
Fcpu
(MHz)
STM32 F4
Max system
frequency
DMIP
S
50
100
150
125
75
25
40 20 80 140 60 100 120 160
175
200
Competitor R
Max flash frequency
Competitor F
Max flash
frequency
STM32 F4
Max flash
frequency
0
Good CPU, fast flash but
No acceleration, limited system speed
Inefficient flash
acceleration for this
CM4
All the results are with the best compiler for each MCU
180
225
Best mix acceleration and speed : STM32F4
27
CONTENTS
Objectives
STM32 F-4 Series
System Architecture
Main features
Full compatibility throughout the family
STM32F4 family is fully pin-to-pin , software and feature compatible
with the STM32F2xx devices.
The STM32F4xx devices maintain a close compatibility with the whole
STM32F10x family.
Functional pins are pin-to-pin compatible.
There are some slight differences concerning the power scheme
Transition from the STM32F10x to the STM32F4xx family remains
simple as only a few pins are impacted.
29
STM32F4xx , STM32F2xx, STM32F10x &
STM32L1xx IPs overview (1/4)
Peripheral STM32F10x
family
STM32L1xx
medium
density
STM32F2xx STM32F4xx
FLASH memory
up to 1 MB up to 128 KB up to 1 MB up to 1 MB
SRAM
up to 96 KB up to 16 KB up to 128 KB up to 192 KB
FSMC
Yes No Yes (+ enhance) Yes (+enhance)
Max CPU frequency
72 MHz 32 MHz 120 MHz 168 MHz
FPU
No No No Yes
MPU
Yes Yes Yes Yes
DMA
Yes Yes Yes Yes
Operating voltage
2.0 to 3.6 V 1.65 to 3.6 V 1.8 to 3.6 V 1.8 to 3.6 V
30
family
STM32L1xx
medium
density
STM32F2xx STM32F4xx
Timers
Advanced 2 No 2 2
General purpose 2 3 4 4
Basics 2 2 2 2
2 Channels 2 1 2 2
1 Channel 4 2 4 4
RTC Basic HW calendar HW calendar
HW calendar
+ sub
seconds
precision
IWDG/WWDG Yes Yes Yes Yes
STM32F4xx, STM32F2xx, STM32F10x &
31
family
STM32L1xx
medium
density
STM32F2xx STM32F4xx
COMs
SPI(I2S) 3(2) 2(+ bug fix) 3(2) (+bug fix) 3(2) (+ bug fix)
Max Operating freq Up to 18Mbits/s Up to 16Mbits/s Up to 15 or 30
Mbits/s
Up to 18.75 or
37.5Mbits/s
Audio sampling freq 8 kHz up to 96 kHz No 8 kHz up to 192 kHz 8 kHz up to 192 kHz
I2C 2 2(+bug fix) 3(+bug fix) 3(same as F2)
Max Operating freq 400 KHz 400 KHz 400 KHz 400 KHz
USART 3 3 4 4
UART 2 No 2 2
Max Operating freq 2.25 or 4.5 Mbit/s up to 4.5 Mbit/s 3.75 or 7.5 Mbit/s 5.25 or 10.5 Mbit/s
USB
OTG FS or Device
FS
Device FS OTG FS and
OTG HS
OTG FS and
OTG HS
CAN 2 No 2 2
SDIO 1 No 1(+bug fix) 1(same as F2)
Ethernet Yes No Yes Yes
32
STM32L1xx Pripherals overview (4/4)
family
STM32L1xx
medium
density
STM32F2xx STM32F4xx
GPIOs 51/80/112 37/51/83 51/82/114/140 51/82/114/140
12 bit ADC 3 1 3 3
Max sampling freq 1 MS/s 1 MS/s 2 MS/s 2.4 MS/s
Number of channels 16 channels 16/20/24 channels 16/24 channels 16/24 channels
12 bit DAC 2 2 2 2
Max sampling freq 1 MS/s 1 MS/s 1 MS/s 1 MS/s
Number of channels 2 2 2 2
DCMI No No Yes Yes
RNG No No Yes Yes
HW Encryption
No No
DES, 3DES, AES
256-bit, SHA-1 &
MD5 hash
DES, 3DES, AES
256-bit, SHA-1 &
MD5 hash
33
34
STM32F4 / F2 Differences in Core and System Architecture
STM32F2xx STM32F4xx
Core ARM Cortex M3 (r2p0) ARM Cortex M4 (r0p1)
Floating point calculation s/w Single precision h/w
Performance / with ART ON 120MHz 0ws like (1.65V-3.6V) 150MHz 0ws like (2.4V3.6V)
144MHz 0ws like (2.1V3.6V)
128MHz 0ws like (1.65V3.6V)
SRAM internal capacity 128KB of system memory 192KB (128KB system memory +
64KB CCM dedicated to CPU
data)
35
STM32F4 / F2 Differences in Core and
System Architecture
STM32F2xx STM32F4xx
Internal Regulator Bypass Available only on WLCSP64
(IRR_OFF pin) and BGA176
(BYPASS_REG pin) packages
On WLCSP64 this functionality can
not be dissociated from BOR OFF
Available only on WLCSP64 and
BGA176 (BYPASS_REG pin)
packages
BOR OFF and Internal regulator
bypass are non exclusive on the
above packages
VDD min extension from 1.8V down
to 1.65V (requires BOR OFF)
Available only on WLCSP64
package (IRR_OFF pin)
This functionality can not be
dissociated from Regulator bypass
Available on all packages
(PDR_ON pin) except on LQFP64
pin package
This functionality can be
dissociated from Regulator bypass
Voltage Scaling (Internal regulator
output)
None Performance Optimization (150
MHz max)
Power Optimization (120MHz max)
36
F4/F2 Differences in Peripheral System
Architecture
STM32F2xx STM32F4xx
FSMC (improvements) Remap capability on
bank1-NE1/NE2, but no
capability to access other
banks while remapped
Remap capability on
bank1-NE1/NE2, with
access to other FSMC
banks while remapped.
I2S 2x I2S Half duplex 2x I2S Full duplex.
37
New RTC implementation in F4 vs F2
STM32F2xx STM32F4xx
Calendar Sub seconds
access
NO YES (resolution down
to RTC clock)
Calendar resolution From RTCCLK/2 to
RTCCLK/2^20
From RTCCLK/1 to
RTCCLK/2^22
Calendar read and
synchronization on the fly
NO YES
Alarm on calendar 2 alarms
Sec, Min, Hour, Date/day
2 alarms
Sec, Min, Hour,
Date/day, Sub seconds
38
New RTC implementation in F4 vs F2
STM32F2xx STM32F4xx
Calendar
Calibration
Calib window : 64min
Calibration step:
Negative:-2ppm
Positive: +4ppm
Range [-63ppm+126ppm]
Calib window :
8s/16s/32s
Calibration step:
Negative or Positive:
3.81ppm/1.91ppm/0.95
ppm
Range [-480ppm
+480ppm]
Timestamp YES
Sec, Min, Hour, Date
YES
Sec, Min, Hour, Date,
Sub seconds
Tamper YES (2 pins /1 event)
Edge Detection only
YES (2 pins/ 2 events)
Level Detection with
Configurable filtering
CONTENTS
Objectives
STM32 F-4 Series
Block Diagram
Boot modes
System Architecture
Main features
Tool Installation
Systems Check
Everyone should have
A Windows Laptop (XP, Vista or Windows 7)
USB Cable
CD/DVD
STM32F0DISCOVERY kit, will be provided after software
installation
Ready to begin?
Note: Please do not attempt to plug in the STM32 F4 Discovery Kit into your laptop until
instructed to do so.
41
Step #1 - File Installation
Insert the CD into your Laptop
Copy the folder D:\STM32F4-DISCOVERY_Kit
on the CD to your root c:\ folder
C:\STM32F4-DISCOVERY_Kit\
Enter this directory. You will find the following:
In the \EWARM directory: EWARM Installation file
Documentation folder containing all relevant documentation for this
training
Firmware Library folder
42
Step #2 - Install IAR EWARM
For this workshop, we will be using the evaluation version
of the Workbench from IAR. Some restrictions apply:
Program and debug up to 32 Kbytes of code
Double-click on the file EWARM-EV-CD-6308.exe to
begin installation. Please click-through the default options
and accept the license agreement
Ask for assistance if you have an issue
43
STM32F4-DISCOVERY
LEDs/Push-Buttons/Extension
Connector
45
Embedded ST-Link
ST-Link programming and
debugging tool integrated on-
board the kit (STM32F103C8T6)
Can be used two different ways
Program and debug the MCU on the
board
Program an MCU on another
application board
Features
USB Connector
ST-LINK MCU
5 to 3V Voltage regulator
CN2 MCU Program Jumper
CN3 Application SWD connector
46
Step #3 - Install ST-Link Driver
The STM32F4DISCOVERY board includes an ST-LINK/V2
embedded programming and debug tool
The driver for ST-Link is contained in the EWARM toolchain and
located in this directory:
C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\drivers\ST-Link
Double-click on the file: ST-Link_V2_USBDriver.exe to install
Click through the installation menu until the driver installation is
complete
47
Step #4: Connect the DiscoveryKit/
Enable ST-Link
Using the USB cable, connect the mini-B male connector into the
STM32F4DISCOVERY USB port and connect the A male connector into your
Laptop
48
Wait for Windows to recognize the
ST-Link device and follow any step
required to install the driver
Upon successful driver recognition,
the ST-Link device should be fully
enumerated in Windows Device
Manager as show:
Step #4
ST-Link Driver Trouble Shooting
1. Open Device Manager
2. Right-click on the STM32 ST-Link Driver icon
3. Select Update Driver Software
49
Step #4
5. Select Let me pick from a list of
device drivers of my computer
6. Click Next
50
4. Select Browse my computer for
driver software
Step #4
The STMicroelectronics ST-Link dongle should be listed
7. Click Next
51
Step #4
A warning message may appear
8. Select Install this driver software anyway
52
Step #4
You should receive a message:
Windows has successfully updated
your driver software
53
Re-check device manager to ensure
STMicroelectronics ST-Link dongle
is functioning normally
Compile, Debug and Run
Step #5
Open FW demo project with EWARM
Using explorer, go to the directory:
C:\STM32F4-Discovery_FW_V1.1.0\Project\Demonstration\EWARM
Double-click on the STM32F4-Discovery_Demo.eww file
55
Step #5 - Inside EWARM
56
Step #6 - Compile
Click on the Build button or Menu::Project::Rebuild All
57
The project should compile without errors
Make
Button
Step #7 - Debug
Click on the Download and Debug button or Menu:
Start/Stop Debug Session
58
Step #7
The EWARM IDE Debugger
59
Files Window
Disassembly Window
Memory Windows
Program counter position
Step #8 - Run
Click on the Go button to start the program
60
Run Button
Your STM32F4DISCOVERY board LD3, LD4, LD5 and LD6 should
begin flashing sequentially
Note: LD2 (ST-Link Status) Should be flashing
Step #8 - Run
Mission Accomplished
Please click on the Break
button.
You code will stop
anywhere within the
program flow
Click on the Stop button to
exit from the debugger
61
Stop Button
Debug
Button
Standard Peripherals Library
62
Library
Global view of the Library
Inclusions relationship
Description of the files
66
Description of the files - CMSIS
67
How to use the Standard
Peripherals Library
68
How to set up the IAR in 7 Steps to work
with the Standard Peripheral Library
1) Create a project and setup all your toolchain's start-up files (or use
the template project provided within the Library, under
Project\STM32F4xx_StdPeriph_Templates) and Select the
corresponding startup file:
i. EWARM: startup_stm32f4xx.s, under
Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\iar
ii. The Library entry point is stm32f4xx.h (under
Libraries\CMSIS\Device\ST\STM32F4xx\Include), user has to include it in the
application main and configure it:
iii. Select the target product family to be used, comment/uncomment the right
define:
iv. /* Uncomment the line below according to the target STM32 device used in your
application */
#if !defined (STM32F4XX)
#define STM32F4XX
#endif
v. Uncomment #define USE_PERIPH_LIBRARY (default)
vi. In stm32f4xx_conf.h file, select the peripherals to include their header file
vii. Add the system_stm32f4xx.c (under
Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates)
How to use the Library in 4 Steps
1) In the main application file, declare a PPP_InitTypeDef structure,
for example: PPP_InitTypeDef PPP_InitStructure;
i. The PPP_InitStructure is a working variable located in data memory area. It
allows initializing one or more PPP instances.
2) Fill the PPP_InitStructure variable with the allowed values of the
structure member. There are two ways of doing this:
i. Configuring the whole structure by following the procedure described below:
ii. PPP_InitStructure.member1 = val1;
PPP_InitStructure.member2 = val2;
PPP_InitStructure.memberN = valN; /* where N is the number of the structure
members */
3) Initialize the PPP peripheral by calling the PPP_Init(..) function.
i. PPP_Init(PPP, &PPP_InitStructure);
4) At this stage the PPP peripheral is initialized and can be enabled
by making a call to PPP_Cmd(..) function.
i. PPP_Cmd(PPP, ENABLE);
Tips for the Library Usage
All peripherals need to receive the clock in order to be activated, in
order to do that, one of the following functions should be used:
RCC_AHBxPeriphClockCmd (where x can be 1..3)
RCC_APBxPeriphClockCmd (where x can be 1..3)
To configurate an interrupt the following steps should be made:
Configure the PPP_ITConfig function
Set the interrupt line in the NVIC_Init function
Remember to clear the interrupt pending bit with PPP_ClearITPendingBit function
Get the name of the Interrupt Handler function from the startup_stm32f4xx.s file
Use the Interrupt Handler name to create the function in the stm32f4xx_it.c file
71
Help and its usage
72
10/08/2012 Presentation Title
Library functions for each peripheral
GPIO Example - Functions
GPIO Example Init Function
GPIO_InitStruct elements
The first parameter is the PORT to be configured, it can one of these:
GPIOAup to GPIOI;
The second parameter is a struct, which contain the following
elements:
Click on the element to configure and check the available options
GPIO_InitStruct elements GPIO_Pin
Choosing the GPIO_Pin we receive the description:
Clicking on the link we receive the options to configure:
Embedded FLASH
Flash Features Overview
79
Up to 1 Mbytes
128 bits wide data read
Byte, half-word, word and double word write
512 Bytes One Time Programmable (OTP)
Sector and mass erase
32-bit Word Program time: 12s(Typ)
Sector Erase time:
16KB: 400ms(Typ)
64KB: 700ms(Typ)
128KB: 1s(Typ)
1MB: around 2s(Typ)
10K Cycles by sector / 20 years retention
Protections
2 RDP levels/sector Write protection
Block Name Block base address Size
Main Memory
Sector 0 0x0800 0000 - 0x0800 3FFF 16 Kbyte
.
.
.
.
.
.
.
.
.
Sector 3 0x0800 C000 - 0x0800 FFFF 16 Kbyte
Sector 4 0x0801 0000 - 0x0801 FFFF 64 Kbyte
Sector 5 0x0802 0000 - 0x0803 FFFF 128 Kbyte
.
.
.
.
.
.
.
.
.
Sector 11 0x080E 0000 - 0x080F FFFF 128 Kbyte
System memory
0x1FFF 0000 - 0x1FFF 77FF
30 Kbyte
OTP
0x1FFF 7800 - 0x1FFF 7A0F
528 Bytes
Option bytes 0x1FFF C000 - 0x1FFF C00F 16 bytes
Flash Interface features Overview
Flash interface Features
Read Interface
Instruction prefetch
Instruction cache: 64 cache lines of 128 bits
Data cache: 8 cache lines of 128 bits
Flash program/Erase operations
Program: Byte, Half word, word and double word
Sector erase and Mass erase
Types of Protection
Read Protection
Level0
Level1
Level2 (JTAG fuse)
Write Protection
Option Bytes
80
Power control (PWR)
Power Supply
V
SS
V
BAT
V
DDA
V
SSA
V
REF-
V
REF+
A/D converter
D/A converter
Temp. sensor
Reset block
PLLs
V
DDA
domain
Core
Memories
Digital
peripherals
V
Core
(1.2V)
domain
V
DD
domain
STANDBY circuitry
(Wake-up logic,
IWDG)
V
DD
Power Supply Schemes
V
DD
= 1.8 V to 3.6 V. External Power Supply for
I/Os and the internal regulator. The supply
voltage can drop to 1.7 when the PDR_ON is
connected to VSS and the device operates in the 0
to 70C.
V
DDA
= 1.8 V to 3.6 V : External Analog Power
supplies for ADC, DAC, Reset blocks, RCs and
PLLs.
V
CAP
= Voltage regulator external capacitors
(also 1.2V supply in Regulator bypass mode)
V
BAT
= 1.65 to 3.6 V: power supply for Backup
domain when V
DD
is not present.
Power pins connection:
V
DD
and V
DDA
must be connected to the same
power source
V
SS
, V
SSA
must be tight to ground
2.4V V
REF+
V
DDA
when V
DDA
2.4
V
REF+
= V
DDA
when V
DDA
< 2.4
RTC and BKP reg
LSE crystal 32K osc
RCC BDCR
BKP SRAM
I/O Rings
FLASH Memory
Backup domain
V
CAP
Low voltage detector
Reset Controller PDR_ON
Voltage Regulator
82
Backup Domain (1/2)
Backup Domain
RTC unit and 4KB Backup RAM
LVR for the backup RAM
Switch off option
VBAT independent voltage supply
Automatic switch-over to V
BAT
when
V
DD
goes below PDR level
No current sunk on V
BAT
when
V
DD
present
Prevent from power line down
1 Wakeup pin and 2 RTC Alternate
functions pins (RTC_AF1 and RTC_AF2)
Backup domain
LP Voltage
Regulator
RTC
80 byte
data
V
BAT
V
DD
BKP SRAM
power switch
RCC BDCR
reg
32KHz OSC
(LSE)
83
RTC Alternate functions (RTC_AF1/RTC_AF2)
Time stamp/Tamper detection
resets all RTC user backup registers
The calendar is saved in the time-stamp registers
RTC Alarm Output: Alarm A, Alarm B (RTC_AF1)
RTC Clock calibration Output: RTCCLK/64, 512Hz when using
32.768Hz crystal. (RTC_AF1)
RTC Clock input reference 50/60 Hz (RTC_AF1)
Wakeup pin
Backup SRAM
4 Kbytes of backup SRAM accessible only from the CPU
Can store sensitive data (crypto keys)
Backup SRAM is powered by a dedicated low power
regulator in V
BAT
mode. Its content is retained even in
Standby and V
BAT
mode when the low power backup
regulator is enabled.
The backup SRAM is not mass erased by an tamper
event.
Backup Domain
32KHz OSC
(LSE)
RTC + 80 Bytes Data RTC_AF1
RCC BDCR
reg
Wakeup
Logic
IWDG Wakeup Pin 1
RTC_AF2
Backup SRAM (4Kbytes)
Backup Domain (2/2)
84
STM32F4xx Low power modes features
The STM32F4xx features 3 low power modes as in STM32F2xx family
SLEEP
STOP
STANDBY
VBAT mode.
The STM32F4xx features options to decrease the consumption during low
power modes
Peripherals clock stopped automatically during sleep mode (S/W)
Flash Power Down mode
LVR and Backup RAM disable option
The STM32F4xx features many sources to wakeup the system from
low power modes
Wakeup pin (PA0) / NRST pin
RTC Alarm (Alarm A and Alarm B)
RTC Wakeup Timer interrupt
RTC Tamper events
RTC Time Stamp Event
IWDG Reset event
85
Reset and clock control (RCC)
RESET Sources
System RESET
Resets all registers except some RCC
registers and Backup domain
Sources
Low level on the NRST pin
(External Reset)
WWDG end of count condition
IWDG end of count condition
A software reset (through NVIC)
Low power management Reset
Power RESET
Resets all registers except the
Backup domain
Sources
Power On/Power down Reset
(POR/PDR)
BOR
Exit from STANDBY
Backup domain RESET
Resets in the Backup domain: RTC
registers + Backup Registers + RCC
BDCR register
Sources
BDRST bit in RCC BDCR register
POWER Reset
87
Filter
V
DD
/V
DDA
R
PU
PULSE
GENERATOR
(min 20s)
SYSTEM RESET
NRST
WWDG
RESET
IWDG RESET
Software RESET
Power RESET
Low power
management RESET
Externa
l RESET
BOR
RESET
POR/PDR
RESET
Clock Features
HSE:(High Speed External Osc) 4MHz to 26MHz
Can be bypassed by and external Oscillator (ie:50MHz)
HSI (High Speed Internal RC): factory trimmed internal RC oscillator 16MHz +/- 1
LSI (Low Speed Internal RC): 32KHz internal RC
IWDG and optionally for the RTC
used for Auto Wake-Up (AWU) from STOP/STANDBY mode
LSE (Low Speed External oscillator): 32.768kHz osc
precise time base with very low power consumption (max 1A).
Optionally drives the RTC for Auto Wake-Up (AWU) from STOP/STANDBY
mode.
Can be Bypassed by an external Osc
88
Clock Features
Two PLLs
Main PLL (PLL) clocked by HSI or HSE used to generate the System clock
(up to 168MHz), and 48 MHz clock for USB OTG FS, SDIO and RNG. PLL
input clock in the range 1-2 MHz, 2MHz is the preferred PLL input frequency
for Jitter purpose.
A dedicated PLL (PLLI2S) used to generate an accurate clock to achieve
high-quality audio performance on the I2S interface.
System Clock (SYSCLK) sources: HSI, HSE and PLL
RTC Clock sources: LSE, LSI and HSE clock divided by 2 to 31
Clock-out capability on the MCO1 (PA8) and MCO2 pins (PC9)
Clock Security System (CSS) to backup clock in case of HSE clock failure (HSI
feeds the system clock)
Spread Spectrum Clock Generation (SSCG, enabled by SW) to reduce the
spectral density of the electromagnetic interference (EMI) generated by the
device
89
Clock Scheme
90
HSI
HSE
PLLCLK
MCO1 /1..5
LSE
SYSCLK
HSE
PLLCLK
MCO2 /1..5
PLLI2S
LSI RC
32.768KHz
/2, to 31
LSE OSc
OSC32_IN
OSC32_OUT
~32KHz
IWDGCLK
RTCCLK
TIM5 IC4
HSE
/
2
,

2
0
MACTXCLK
MACRXCLK
MACRMIICLK
USB HS
ULPI clock
/ P
/ Q
/ R
x N
PLLI2S
I2SCLK
Ext. Clock
I2S_CKIN
PLLI2SCLK
VCO
PCLK1
up to 42MHz
If (APB2 pres =1)
x1 Else
x2
If (APB1 pres
=1) x1
Else x2
PCLK2
up to 84MHz
TIMxCLK
TIM2..7,12..14
APB1
Prescaler
/1,2,4,8,16
TIMxCLK
TIM1,8..11
APB2
Prescaler
/1,2,4,8,16
HCLK up
to 168MHz
AHB Prescaler
/1,2512
/8 SysTick
PLL48CLK (USB FS, SDIO & RNG)
CSS
HSE Osc
OSC_OUT
OSC_IN
4 -26 MHz
PLLCLK
HSI RC
16MHz
/ M
HSE
HSI
SYSCLK
168 MHz
max
/ P
/ Q
/ R
VCO
x N
PLL
Ethernet
PHY
USB2.0
PHY
Tips and Tricks:
Using the STM32F4 System clock
configuration file
STM32F4xx_Clock_Configuration.xls
This tool supports the following functionalities for the STM32F4xx:
Configuration of the system clock, HCLK source and output frequency
Configuration of the Flash latency (number of wait states depending on the HCLK
frequency)
Setting of the PCLK1, PCLK2, TIMCLK (timer clocks) and I2SCLK frequencies
Generation of a ready-to-use system_stm32f0xx.c file with all the above settings
(STM32F4xx CMSIS Cortex-M4 Device Peripheral Access Layer System Source
File)
92
Enable Macros for Excel1997-2003 version
1. Click Tools in the menu bar.
2. Click Macro.
3. Click Security.
4. Click Low (not recommended).
Excel 2007 version
1. Click the Microsoft Office button and then click Excel options.
2. Click Trust Center, click Trust center settings, and then click Macro settings.
3. Click Enable all macros (not recommended, potentially dangerous code can run).
4. Click Trust Center, click Trust center settings, and then click ActiveX settings.
5. Click Enable all controls without restrictions and without prompting (not
recommended; potentiality dangerous controls can run).
6. Click OK
93
94
The wizard guides you through the following steps:
1. Set the HSE frequency (if is used in your application) between a minimum
of 4 MHz, and a maximum of 26 MHz if a crystal oscillator is used for the
STM32F4xx. If the frequency entered is out of range, an error message is
displayed, and a valid frequency must be entered.
The definition of HSE_VALUE in the stm32f4xx.h file must be modified each time
the user changes the HSE oscillator value.
2. Configure the Prefetch buffer (select ON or OFF from the list box).
3. Specify if the I2S clock is needed. If needed, enable it and follow steps 7, 8 and
9. Otherwise, go to step 4.
4. Set the desired HCLK frequency. If the value entered is higher than the
maximum HCLK frequency, an error message is displayed.
5. Select the PCLK1 and PCLK2 prescaler settings from the list box to obtain the
desired PCLK1 and PCLK2 frequencies. The TIMCLK frequencies are configured
automatically depending on the PCLK1 and PCLK2 prescaler settings.
95
6. If the I2S clock is needed, select the frame width (16 or 32 bits).
7. Specify if the master clock is enabled or disabled (Select ON/OFF from the list
box).
8. Select the Frequency from the list box. The Fs value can be 192 kHz, 96 kHz, 48
kHz, 44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz, or 8 kHz.
9. Click the RUN button.
If more than one clock source is possible, a message box displays the
clock sources that can be selected (see Figure below). Choose HSE,
HSI or PLL (which are sourced by the HSI or HSE).
96
10. Click the Generate button to automatically generate system_stm32f4xx.c
file. The system_stm32f4xx.c file is generated in the same location as the clock
tool. Display the file to verify the value of the system clock, SystemCoreClock, and
the values of HCLK, PCLK1, PCLK2, Flash access mode, and other parameters
which are defined in the SetSysClock function.
If the file is not generated, an error message is displayed as shown
11. The system_stm32f4xx.c file must be added to the working project to be built.
97
General-purpose I/Os (GPIO)
GPIO features
Up to 140 multifunction bi-directional I/O ports available on biggest
package 176 pin.
Almost standard I/Os are 5V tolerant*
All Standard I/Os are shared in 9 ports (GPIOA..GPIOI)
Atomic Bit Set and Bit Reset using BSRR register
GPIO connected to AHB bus: max toggling frequency 84 MHz
Configurable Output Speed up to 100 MHz
Locking mechanism (GPIOx_LCKR) provided to freeze the I/O
configuration
Up to 140 GPIOs can be set-up as external interrupt (up to 16 lines
at time) able to wake-up the MCU from low power modes
99
GPIO Configuration Modes
(1) VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.
To On-chip Peripherals
Analog
From On-chip Peripherals
Push-Pull
Open Drain Output
Driver
I
/
O

p
i
n
VS
S
On/Off
P
u
l
l

-
U
p
P
u
l
l

-
D
o
w
n
VDD
On/Off
B
i
t

S
e
t
/
R
e
s
e
t

R
e
g
i
s
t
e
r
I
n
p
u
t

D
a
t
a

R
e
g
i
s
t
e
r
O
u
t
p
u
t

D
a
t
a

R
e
g
i
s
t
e
r
Read / Write
Alternate Function Input
Alternate Function Output
Schmitt
Trigger
VDD
VSS
0
Input
Driver
Read
Write
OnOff
VDD or VDD_FT
(1)
VS
S
OUTPUT
CONTROL
Analog
MODER(i)
[1:0]
OTYPER(i)
[1:0]
I/O configuration
PUPDR(i)
[1:0]
11 x Analog mode x
01
0
0 0 Output Open Drain
0 1 Output Open Drain with Pull-up
1 0 Output Open Drain with Pull-down
1
0 0 Output Push Pull
0 1 Output Push Pull with Pull-up
1 0 Output Push Pull with Pull-down
10
0
1
0 0 Alternate Function Open Drain
0 1 Alternate Function OD Pull-up
1 0 Alternate Function OD Pull-down
0 0 Alternate Function Push Pull
0 1 Alternate Function PP Pull-up
1 0 Alternate Function PP Pull-down
00 x
0 0 Input floating
0 1 Input with Pull-up
1 0 Input with Pull-down
* In output mode, the I/O speed is configurable through OSPEEDR
register: 2MHz, 25MHz, 50MHz or 100 MHz
100
Alternate Functions features
Most of the peripherals shares the same pin (like USARTx_Tx, TIMx_CH2,
I2Cx_SCL, SPIx_MISO, EVENTOUT)
Alternate functions multiplexers prevent to have several peripherals function
pin to be connected to a specific I/O at a time.
Some Alternate function pins are remapped to give the possibility to optimize
the number of peripherals used in parallel.
AF0 (system)
AF1 (TIM1/2)
AF2 (TIM3..5)
AF15 (EVENTOUT)
Pin x (015)
101
HANDS-ON!!!
102
Open IO_Toggle Project
Go to the directory:
C:\STM32F4-Discovery_FW_V1.1.0\Project\Exercises\IO_Toggle\EWARM
Double-click on IO_Toggle.eww to open the project
103
Hands on GPIO
Proposition: Fill the missing functions and parameters
Configure the PD12/13/14/15 as output pushpull mode and provide
the functions to toggle the LEDs in this sequency:
Set PD12 delay
Set PD13 delay
Set PD14 delay
Set PD15 delay
Reset all Leds delay
Main functions:
GPIO_Init
GPIO_SetBits
GPIO_ResetBits
RCC_AHB1PeriphClockCmd
104
General purpose timers (TIM)
STM32F4xx Timer features overview (1/2)
Counter
resolution
Counter type
Prescaler
factor
DMA
Capture
Compare
Channels
Complementary
output
Synchronization
Master
Config
Slave
Config
Advanced
TIM1 and TIM8
16 bit
up, down and
up/down
1..65536 YES 4 3 YES YES
General purpose (1)
TIM2 and TIM5
32 bit
up, down and
up/down
1..65536 YES 4 0 YES YES
General purpose
TIM3 and TIM4
16 bit
up, down and
up/down
1..65536 YES 4 0 YES YES
Basics
TIM6 and TIM7
16 bit up 1..65536 YES 0 0 YES NO
1 Channel (2)
TIM10..11 and
TIM13..14 (2)
16 bit up 1..65536 NO 1 0
YES(OC
signal)
NO
2 Channel(2)
TIM9 and TIM12
16 bit up 1..65536 NO 2 0 NO YES
(1) Same as STM32F2xx 32-Bit Timers
(2) These Timers are identical to STM32F2xx and XXL Timers
106
Counter clock source
Output
Compare
PWM
Input
Capture
PWMI OPM
Encoder
interface
Hall sensor
interface
XOR
Input
Advanced
TIM1 and TIM8
-Internal clock APB2
-External clock:
ETR/TI1/TI2/TI3/TI4 pins
-Internal Trigger:
ITR1/ITR2/ITR3/ITR4
-Slave mode
7 channels 7 channels 4 channels 2 channels 2 channels Yes Yes Yes
General Purpose
TIM2 and TIM5
-External clock:
-Internal Trigger:
ITR1/ITR2/ITR3/ITR4
-Slave mode
4 channels 4 channels 4 channels 2 channels 2 channels Yes No Yes
General Purpose
TIM3 and TIM4
-External clock:
-Internal Trigger:
ITR1/ITR2/ITR3/ITR4
-Slave mode
4 channels 4 channels 4 channels 2 channels 2 channels Yes No Yes
Basics
TIM6 and TIM7
-Internal clock APB1 No No No No No No No No
1 Channel
TIM10/11 and 13/14
-Internal clock APB1/APB2 1 Channel 1 Channel 1 Channel No No No No No
2 Channel
TIM9 and TIM12
-Internal clock APB1/APB2
-External clock:
TI1/TI2/TI3/TI4 pins
-Internal Trigger:
ITR1/ITR2/ITR3/ITR4
-Slave mode
2 channels 2 channels 2 channels 2 channels 2 channels No No No
STM32F4xx Timer features overview 2/2
107
Features overview
General Purpose Feature
16/32-bit Counter
Auto Reload / Up, down and centered modes
4x 16 High resolution Capture Compare channels
Programmable direction of the channel: input/output
Output Compare: Toggle, PWM
Input Capture
PWM Input Capture
Synchronization
Up to 8 IT/DMA Requests
Motor Control Specific Feature
OC Signal Management
6 Complementary outputs
Dead-time management
Repetition Unit
Encoder Interface
Hall sensor Interface
Embedded Safety features
CH1
CH1N
CH2
CH2N
CH3
CH3N
CH4
16-Bit Prescaler
ITR 1 Trigger/Clock
Controller
Trigger
Output
Clock
Auto Reload REG
+/- 16/32-Bit Counter
Capture Compare
ITR 2
ITR 3
ITR 4
BKIN
Capture Compare
Capture Compare
Capture Compare
CH1
CH2
CH3
CH4
ETR
108
Counter Modes
There are three counter modes:
Up counting mode
Down counting mode
Center-aligned mode
When using the Repetion Counter (case of TIM1 and TIM8 only)
Center Aligned Up counting Down counting
RCR = 0
RCR = 2
UEV
UEV
109
Update Event
The content of the preload register is transferred in the shadow register (depending on the auto-reload
preload is enable or not):
Immediately
At each update event UEV
The Update Event is generated:
when the counter reaches overflow/undeflow
when the Repetition counter equals to 0 (only for TIM1)
By software by setting the UG (Update Generation) bit
The Update event UEV requests can be selected as follow:
The requests are sent only when the counter reachs the overflow/underflow.
The request are sent when (counter overflow/underflow or set of UG bit or update generation through
the slave mode controller
110
HANDS-ON!!!
111
Open TIM_TimeBase Project
C:\STM32F4-Discovery_FW_V1.1.0\Project\Exercises\TIM_TimeBase\EWARM
Double-click on TIM_TimeBase.eww to open the project
112
Hands on TIM example
Configure All LEDS (PD12/13/14/15) as output pushpull mode,
configure the time based from TIM3 and its interrupt as overflow
(update)
Main functions:
GPIO_Init
RCC_APB1PeriphClockCmd
TIM_TimeBaseInit
TIM_ITConfig
TIM_ClearITPendingBit
NVIC_Init
113
Output Compare Mode
114
Timer Clock
CCR1
Interrupt
New CCR1
OC1
Interrupt
The Output Compare is used to control an output waveform or indicate when a period of
time has elapsed.
When a match is found between the
capture/compare register and the counter:
The corresponding output pin is assigned to the
programmable Mode, it can be:
Set
Reset
Toggle
Remain unchanged
Set a flag in the interrupt status register
Generates an interrupt if the corresponding
interrupt mask is set
Send a DMA request if the corresponding
enable bit is set
The CCRx registers can be programmed with or
without preload registers
PWM Mode
The PWMmode allows to generate:
7 independent signals for TIM1 and TIM8
4 independent signals for TIM2, 3, 4 and 5
2 independent signals for TIM9 and 12
1 signals for TIM10, 11, 13 and 14
The frequency and a duty cycle determined as follow:
One auto-reload register to defined the PWMperiod.
Each PWMchannel has a Capture Compare register to define the duty cycle.
Example: to generate a 40 KHz PWMsignal w/ duty cycle of 50% on TIM1 clock at 72MHz:
Load Prescaler register with 0 (counter clocked by TIM1CLK/(0+1)), Auto Reload register with 1799 and CCRx
register with 899
There are two configurable PWMmodes:
115
Capture
Compare
Timer
Clock
AutoReload
Update
Event
Capture
Compare
Edge-aligned Mode
Center-aligned Mode
Timer
Clock
AutoReload
Update
Event
OCx
OCx
Advanced Control timer TIM1 and TIM8
Complementary PWM outputs for motor control
This mode allows the TIM1 and TIM8 to:
Output two complementary signals for each three channels.
Output two independent signals for each three channels.
Manage the dead-time between the switching-off and the switching-on instants of the outputs.
One reference waveform OCx
REF
to generate 2 outputs OCx and OCxN for the three channels.
Full modulation capability (0 and 100% duty cycle), edge or center-aligned patterns
Dedicated interrupt and DMA requests for TIM1 period and duty cycles updating.
Three programmable write protection levels
Level1: Dead Time and Emergency enable are locked.
Level2: Level1 + Polarities and Off-state selection for run and Idle state are locked.
Level3: Level2 + Output Compare Control and Preload are locked.
116
117
Examples of OCx waveform in Complementary PWM mode
OCx
REF
OCx
OCxN
t
OCx
REF
OCx
OCxN
t
delay
Dead-time disabled Dead-time enabled
Exercise:
How to configure the PWM to generate three complementary Pulse Width
Modulation waveforms with dead time insertion?
Complementary PWM configuration steps:
1. Select the PWM mode.
2. Activate the three complementary signals:
i. Enable: Main Output, OCx and OCxN
ii. Select the different off-state for Run
and Idle state.
3. Set the corresponding polarity for each output.
4. Define the dead-time, the frequency and duty
cycles.
5. Set the locking level and enable the input
Break if necessary.
6. Enable the counter.
7. Set The Main Output Enable bit and/or the
Automatic Output Enable bit.
118
OC1
OC1N
OC2
OC2N
OC3
OC3N
t
HANDS-ON!!!
119
Open TIM_PWM_OutputProject
C:\STM32F4-
Discovery_FW_V1.1.0\Project\Exercises\TIM_PWM_Output\EWARM
Double-click on TIM_PWM_Output.eww to open the project
120
Hands on TIM example
Configure All LEDS (PD12/13/14/15) as output Alternate Function
mode, configure the time based from TIM4 and its Output Compare
Channels 1 to 4
Main functions:
GPIO_Init
TIM_TimeBaseInit
TIM_OC4PreloadConfig
TIM_OCxInit (where x goes from 1 to 4)
GPIO_PinAFConfig
121
ANALOG TO-DIGITAL CONVERTER
(ADC)
123
ADC Features (1/3)
3 ADCs : ADC1 (master), ADC2 and ADC3 (slaves).
Maximum frequency of the ADC analog clock is 36MHz.
12-bits, 10-bits, 8-bits or 6-bits configurable resolution.
ADC conversion rate with 12 bit resolution is up to:
2.4 M.sample/s in single ADC mode,
4.5 M.sapmle/s in dual interleaved ADC mode,
7.2 M.sample/s in Triple interleaved ADC mode.
Conversion range: 0 to 3.6 V.
ADC supply requirement: VDDA = 2.4V to 3.6V at full speed and down to 1.65V
at lower speed.
Up to 24 external channels.
3 ADC1 internal channels connected to:
Temperature sensor,
Internal voltage reference : VREFINT (1.2V typ),
VBAT for internal battery monitoring.
124
External trigger option for both regular and injected conversion.
Single and continuous conversion modes.
Scan mode for automatic conversion of channel 0 to channel n.
Left or right data alignment with in-built data coherency.
Channel by channel programmable sampling time.
Discontinuous mode.
Dual/Triple mode (with ADC1 and ADC2 or all 3 ADCs) with various
possibilities :
Injected simultaneous mode,
Regular simultaneous mode,
Interleaved mode,
Alternate trigger mode,
Injected simultaneous mode + Regular simultaneous mode,
Regular simultaneous mode + Alternate trigger mode.
ADC Features (2/3)
125
DMA capability
DMA request generation during regular channel conversion in single mode,
ADC-DMA mode 1 used in regular simultaneous Dual/Triple ADC mode,
ADC-DMA mode 2 used in interleaved Dual/Triple ADC mode as well as in regular simultaneous
Dual ADC mode,
ADC-DMA mode 3 used in interleaved Dual/Triple ADC mode with 6-bits and 8-bits resolution.
Analog Watchdog on high and low thresholds.
Interrupt generation on:
End of Conversion
End of Injected conversion
Analog watchdog
Overrun
ADC Features (3/3)
126
ADC speed performances
AHBCLK APB2CLK ADC_CLK
ADC speed
(15 cycles)
168MHz
(a)
84MHz
(2)
21MHz
0.714s
1.4 Msample/s
144MHz
(a)
72MHz
(1)
36MHz
0.416s
2.4 Msample/s
120MHz
(a)
60MHz
(1)
30MHz
0.5s
2 Msample/s
96MHz
(a)
48MHz
(1)
24MHz
0.625s
1.6 Msample/s
72MHz
(b)
72MHz
(1)
36MHz
0.416s
2.4 Msample/s
(1). ADC_PRESC = /2
(a) APB_PRESC = /2
(b) APB_PRESC = /1
SYSCLK
(168MHz max)
AHB_PRESC
/1,2,..512
APB2_PRESC
/1, 2, 4, 8,16
ADC_PRESC
/2,4, 6, 8
ADC_CLK
(36MHz max)
AHBCLK
(168MHz max)
APB2CLK
(84MHz max)
(2). ADC_PRESC = /4
127
ADCCLK, up to 36MHz, taken from PCLK through a prescaler (Div2,
Div4, Div6 and Div8).
Three bits programmable sample time for each channel:
3 cycles
15 cycles
28 cycles
58 cycles
84 cycles
112 cycles
144 cycles
480 cycles
ADC Sampling Time (T
Sampling
)
ADCx
ADCCLK ADCCLK
Prescaler
/2, /4, /6 or /8
PCLK
112 cycles
15 cycles
144 cycles
84 cycles
28 cycles
58 cycles
3 cycles
480 cycles
S
a
m
p
l
e

T
i
m
e
S
a
m
p
l
e

T
i
m
e
S
e
l
e
c
t
i
o
n
S
e
l
e
c
t
i
o
n
SMPx[2:0]
128
Total Conversion Time
Total conversion Time = T
Sampling
+ T
Conversion
With Sample time= 3 cycles @ ADC_CLK = 36MHz total conversion time is equal to :
Resolution
T
Conversion
12 bits 12 Cycles
10 bits 10 Cycles
8 bits 8 Cycles
6 bits 6 Cycles
resolution Total conversion Time
12 bits
12 + 3 = 15cycles
0.416 us 2.4 Msps
10 bits
10 + 3 = 13 cycles
0.361 us 2.71 Msps
8 bits
8 + 3 = 11 cycles
0.305 us 3.27 Msps
6 bits
6 + 3 = 9 cycles
0.25 us 4 Msps
33
ADC_CLK ADC_CLK
66 99 12 12 15 15 18 18
21 21
24 24 27 27 30 30
00
--22
+2 +2
ADC conversion in single mode (12 bit resolution)
3
Sampling Sampling
Conversion Conversion
12 3 12
1st sample 1st sample 2nd sample 2nd sample
This channel is sampled This channel is sampled
each 15 ADC CLK each 15 ADC CLK
cycles. cycles.
The sampling speed in The sampling speed in
this case is equal to: this case is equal to:
36MHz/15 = 36MHz/15 = 2.4Msps 2.4Msps
With 36MHz is the With 36MHz is the
maximum ADC CLK in maximum ADC CLK in
STM32F4xx product. STM32F4xx product.
3td sample 3td sample
ADC1 ADC1
129
130
ADC Regular / Injected channels group
Programmable number of regular channels: Up to 16 conversions.
Programmable sample time and conversion sequence.
Conversion started by:
Software: through start bit,
External trigger generated by:
EXTI IT11,
15 triggers from 6 TIMERS,
Programmable number of injected channels: Up to 4 conversions.
Programmable sample time and conversion sequence.
Conversion started by:
JAUTO: automatic injected conversion after regular channels conversion,
Software: through start bit,
External trigger generated by:
EXTI IT15,
15 triggers from 6 TIMERS.
131
ADC Sequencer
Up to 16 regular and 4 injected conversions with programmable order, programmable
sampling time and over-sampling possibility.
Example: - Conversion of channels: 0, 2, 8, 4, 7, 3, 3 ,3 and 11
- Different sampling time.
- Over-sampling of channel 3.
Ch.0 Ch.2 Ch.8 Ch.4 Ch.7 Ch.3 Ch.3 Ch.3 Ch.11
15 cycles
3 cycles
28 cycles
3 cycles
28 cycles
28 x 3
cycles
58 cycles
132
ADC conversion modes
Five conversion modes are available:
CHx
Start
Stop
Single channel Single channel
single conversion mode single conversion mode
CHx
Start
Stop
.
.
.
CHn
Multi Multi--channels (Scan) channels (Scan)
single conversion mode single conversion mode
CHx
Start
.
.
.
CHn
Multi Multi- -channels channels (Scan) (Scan)
continuous conversion mode continuous conversion mode
CHx
Start
Single channel Single channel
Continuous conversion mode Continuous conversion mode
.. .. CHa
Discontinuons conversion Discontinuons conversion
mode mode
CHb CHc CHx CHy CHz
133
ADC discontinuous conversion mode
Split channels conversion sequence into sub-sequences
Available for both regular and injected groups:
Up to 8 conversions for regular group
Up to 3 conversions for injected group
Example:
- Conversion of regular channels: 0, 1, 2, 4, 5, 8, 9, 11, 12, 13, 14 and 15
- Discontinuous mode Number of conversions: 3
Ch.0 Ch.1 Ch.2 Ch.4 Ch.5 Ch.8 Ch.9 Ch.11 Ch.12
Ch.13 Ch.14 Ch.15
1
st
trigger 2
nd
trigger 3
rd
trigger
4
th
trigger
End of
Conversion
Ch.0 Ch.1 Ch.2
5
th
trigger
Note: Note: Do not use discontinuous mode for both

regular and injected together. It can be
used only for one group channel
134
ADC Analog Watchdog
12-bit programmable analog watchdog low and high thresholds
Enabled on one or all converted channels: one regular or/and injected
channel, all injected or/and regular channels.
Interrupt generation on low or high thresholds detection
Status Register
Analog Watchdog
Low Threshold Low Threshold
Temp Sensor
VREFINT
ADC_IN0
ADC_IN1
ADC_IN15
.
.
.
AWD
High Threshold High Threshold
.
.
.
135
Temperature sensor and V
BAT
monitoring
The Temperature Sensor is internally connected to the ADC1_IN16
input channel.
The temperature sensor can be used to measure the junction
temperature (TJ) of the device.
Accuracy: +/- 1.5C.
V
BAT
input voltage can be converted on ADC1_IN18 input for Battery
monitoring.
As V
BAT
voltage could be higher than VDDA, to assure the correct
operating condition of the ADC, the Input voltage is in fact V
BAT
followed by a bridge divider by 2.
136
ADC dual modes
ADCs: ADC1 master and ADC2 slave, ADC3 is independently.
The start of conversion is triggered alternately or simultaneously by the
ADC1 master to the ADC2 slave depending on the mode selected.
6 ADC dual modes
A
D
C
_
I
N
0
A
D
C
_
I
N
1
5
GPIO
Ports
T
e
m
p

S
e
n
s
o
r
V
R
E
F
I
N
T
Up to 4 injected
channels
Up to 16 regular channels
ANALOG MUX
A
D
C
_
I
N
1
ADC1
Analog
ADC2
Analog
Digital Master Digital Slave
External event
synchronization
External event (Regular group)
External event (Injected group) Data
register
EOC/JEOC
C
o
m
m
o
n

p
a
r
t
D
u
a
l
/
T
r
i
p
l
e

m
o
d
e

c
o
n
t
r
o
l
EOC/JEOC
External event
synchronization
Data
register
137
GPIO
Ports
T
e
m
p

S
e
n
s
o
r
V
R
E
F
I
N
T
Up to 4 injected
channels
Up to 16 regular channels
A
D
C
_
I
N
0
ANALOG MUX
A
D
C
_
I
N
1
A
D
C
_
I
N
1
5
ADC1
Analog
ADC2
Analog
Digital Master Digital Slave
External event
synchronization
External event (Regular group)
External event (Injected group)
Data
register
EOC/JEOC
C
o
m
m
o
n

p
a
r
t
D
u
a
l
/
T
r
i
p
l
e

m
o
d
e

c
o
n
t
r
o
l
EOC/JEOC
External event
synchronization
Data register
ADC3
Analog
Digital Slave
ADCs: ADC1 master, ADC2 and ADC3 slaves.
The start of conversion is triggered alternately or simultaneously by the
ADC1 master to the ADC2 and ADC3 slaves depending on the mode
selected.
6 ADC Triple modes.
ADC Triple modes(1/7)
ADC Triple modes(2/7) Injected simultaneous mode
Converts an injected channel group.
The external trigger source, which start the conversion, comes from ADC1
(simultaneous trigger provided to ADC2 and ADC3 slaves).
An end of injected conversion is generated at the end of all channels
conversion.
Results stored on injected data registers of each ADC.
Injected simultaneous mode on 4 injected channels:
CH0 CH1 CH2 CH3
CH15 CH14 CH13 CH12
ADC1 ADC1
ADC2 ADC2
Sampling Sampling
CH6 CH7 CH8 CH9
ADC3 ADC3
Trigger for
injected
channels
End of Injected Conversion on ADC1,
ADC2 and ADC3.
Note: Note: Do not convert the same channel on the three
ADCs.
138
ADC Triple modes(3/7) Regular simultaneous mode
Converts a regular channel group.
The external trigger source, which start the conversion, comes from ADC1
(simultaneous trigger provided to ADC2 and ADC3 slaves).
An end of regular conversion is generated at the end of all channels
conversion.
Results stored on the common data register ADC_CDR.
Regular simultaneous mode on 16 regular channels:
CH0 CH1 CH2 CH3
CH15 CH14 CH13 CH12
ADC1 ADC1
ADC2 ADC2
Sampling Sampling
CH10 CH12 CH8 CH5
ADC3 ADC3
Trigger for
regular
channels
End of regular Conversion on ADC1,
ADC2 and ADC3.
ADCs.
CH15
CH0
CH2
139
ADC Triple modes(4/7) Interleaved mode
Converts a regular channel group (usually one channel).
The external trigger source, which start the conversion, comes from ADC1:
ADC1 starts immediately,
ADC2 starts after a delay of 5 ADC clock cycles,
ADC3 starts after a delay of 5 ADC clock cycles referred to the ADC2 conversion.
In this mode the sampling criteria to respect is always "Tsampling + 2
ADC Cycles as minimum delay.
Results stored on the common data register ADC_CDR.
Interleaved mode on 1 regular channel in continuous conversion mode:
CH0 ADC1 ADC1
ADC2 ADC2
Sampling Sampling
Trigger for
regular
channels
5 ADCCLK
cycles
CH0
CH0
CH0
CH0
CH0 CH0 CH0
DMA request every 2 conversions
CH0
ADC3 ADC3
End of Conversion on
ADC2
ADC1
ADC3
140
33
ADC_CLK ADC_CLK
66 99 12 12 15 15 18 18
21 21
24 24 27 27 30 30
00
--22
+2 +2
ADC conversion in Triple Interleaved mode (12 bit resolution)
3
Sampling Sampling
12
3 12
1st sample 1st sample
2nd sample 2nd sample
cycles. cycles.
36MHz/5 = 36MHz/5 = 7.2Msps 7.2Msps
3d sample 3d sample
ADC1 ADC1
55
5 Cycle 5 Cycle
15 15
3 12
4th sample 4th sample
25 25
3 12
3 12
ADC2 ADC2
ADC3 ADC3
10 10
55 55
20 20
55 55
3 12
141
33
ADC_CLK ADC_CLK
66 99 12 12 15 15 18 18
21 21
24 24 27 27 30 30
00
--22
+2 +2
ADC conversion in Triple Interleaved mode (6 bit resolution)
3
Sampling Sampling
6
3
1st sample 1st sample
2nd sample 2nd sample
cycles. cycles.
36MHz/5 = 36MHz/5 = 7.2Msps 7.2Msps
3d sample 3d sample
ADC1 ADC1
55
5 Cycle 5 Cycle
15 15
3
25 25
3
3
ADC2 ADC2
ADC3 ADC3
10 10
55 55
20 20
55 55
3
6
6
6
6
6
66
66
66
142
143
ADC Triple modes (5/7) Alternate Trigger mode
Converts an injected channel group.
The external trigger source, which start the conversion, comes from ADC1:
On 1st trigger, the first injected group channel in ADC1 is converted
On 2nd trigger, the first injected group channel in ADC2 is converted
On 3rd trigger, the first injected group channel in ADC3 is converted
On 4th trigger, the second injected group channel in ADC1 is converted
An end of injected conversion is generated at the end of each conversion
Results stored on injected data registers of each ADC.
CH0 ADC1 ADC1
ADC2 ADC2
Alternate Trigger mode on 4 injected channels:
Sampling Sampling
CH11
CH1
CH12 CH13
CH2 CH3
1
st
Trigger
4
th
Trigger
7
th
Trigger
10
th
Trigger
CH10
JEOC on ADC1 JEOC JEOC
JEOC
JEOC
JEOC JEOC JEOC on ADC2
ADC3 ADC3
CH6 CH6 CH7 CH5
JEOC
JEOC JEOC
JEOC on ADC3
2
nd
Trigger
3
th
Trigger
5
th
Trigger
6
th
Trigger
8
th
Trigger
9
th
Trigger
11
th
Trigger
12
th
Trigger
ADC Triple modes (6/7)
Combined Regular + Injected simultaneous mode
Converts an injected and regular channel groups.
The external triggers sources, which start the conversions, comes from ADC1
(simultaneous trigger provided to ADC2 and ADC3): injected simultaneous
mode can interrupt all channels conversions.
Results of injected channels stored on injected data registers of each ADC,
and regular channels on the common data register ADC_CDR.
Combined Regular/Injected simultaneous mode on 4 regular channels and 2 injected channels:
CH0 CH1
CH1 CH2
CH3 CH2
CH2 CH1
ADC1 ADC1
ADC2 ADC2
Trigger for
regular
channels
End of Conversion on ADC1,
ADC2 and ADC3.
CH10 CH11
CH15 CH14
ADC1 ADC1
ADC2 ADC2
Trigger for injected
channels
End of Injected Conversion on ADC1,
ADC2 and ADC3.
regular simultaneous
mode interrupted by
injected simultaneous
one
CH3
CH0
CH1 CH3
CH3 CH0 CH2
ADC3 ADC3
CH8 CH9 ADC3 ADC3
ADCs.
Sampling Sampling
144
ADC Triple modes (7/7)
Combined Regular simultaneous + Alternate Trigger mode
Converts an injected and regular channel groups.
The external triggers sources, which start the conversions, comes from
ADC1 (simultaneous trigger provided to ADC2 and ADC3): alternate trigger
mode can interrupt all channels conversions.
Results of injected channels stored on injected data registers of each ADC,
and regular channels on the common data register ADC_CDR.
Combined Regular simultaneous + Alternate trigger mode:
CH0 CH1 CH1 CH2
CH3 CH0 CH0 CH1
ADC1 reg ADC1 reg
ADC2 reg ADC2 reg
Trigger for
regular
channels
ADC1, ADC2 and ADC3
ADC1 inj ADC1 inj
ADC2 inj ADC2 inj
End of Injected
Conversion on ADC2
Regular simultaneous mode interrupted by the Alternate trigger mode
CH10
2
nd
injected
Trigger
CH11
CH2
CH1
End of Injected
Conversion on ADC1
1
st
injected
Trigger
CH1 CH2 CH2 CH3 ADC3 reg ADC3 reg CH3
CH3
CH12
CH3
CH2 CH2
CH0 CH0
ADC3 inj ADC3 inj
End of Injected
Conversion on ADC3
3
th
injected
Trigger
145
146
ADC and DMA(1/4): Single mode
DMA request generated on each ADC end of regular channel conversion
(Not in injected channels).
Example:
- Conversion of regular channels: 0, 2, 3, 4, 2, 5, 9, 7
and 8
- Converted data stored in ConvertedValue_Tab[9]
- DMA transfer enabled (destination address auto incremented)
Channel0 Channel2 Channel3 Channel4 Channel2 Channel5 Channel9 Channel7 Channel8
DMA
Request
Channel8 conversion result
ADC_DR register ADC_DR register
.
.
.
.
.
.
DMA
Request
DMA
Request
DMA
Request
DMA
Request
DMA
Request
DMA
Request
DMA
Request
DMA
Request
ConvertedValue_Tab[9]
Note: Each time DMA accessed to ADC_DR register, EOC
flag is automatically cleared
ADC and DMA(2/4): ADC_DMA mode 1
Used in regular simultaneous Dual/Triple ADC mode.
DMA ensure the access to the converted regular channel values which are
stored into the common data register ADC_CDR.
On each DMA request, a half-word representing an ADC-converted data
item is transferred.
DMA bits in common control register ADC_CCR must be set at 0b01.
DMA transfer in Triple ADC Regular simultaneous mode:
CH0 CH1
CH15 CH14
ADC1 ADC1
ADC2 ADC2
CH10 CH12
ADC3 ADC3
Trigger for
regular
channels
1
st
DMA
request
2
nd
DMA
request
3
rd
DMA
request
6
th
DMA
request
5
th
DMA
request
4
th
DMA
request
ADC_CDR register ADC_CDR register
DMA 1st request
DMA 2st request
DMA 3st request
ADC_CDR[31:0] = ADC1_DR[15:0]
ADC_CDR[31:0] = ADC2_DR[15:0]
ADC_CDR[31:0] = ADC3_DR[15:0]
DMA request ++
147
Used in interleaved Dual/Triple ADC mode and in regular simultaneous
Dual ADC mode.
On each DMA request, two half-words representing two ADC-converted
data items are transferred as a word.
DMA transfer in Triple ADC interleaved mode:
CH0 ADC1 ADC1
ADC2 ADC2
Trigger for
regular
channels
5 ADCCLK
cycles
CH0
CH0
CH0 CH0
DMA request every 2 conversions
CH0
ADC3 ADC3
ADC2
ADC1
ADC3
DMA 1st request
DMA 2st request
DMA 3st request
DMA request ++
ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0]
148
Used in interleaved Dual/Triple ADC mode and in regular simultaneous
Dual ADC mode with 6-bits and 8-bits resolutions.
On each DMA request, two bytes representing two ADC-converted data
items are transferred as a half-word.
DMA 1st request
DMA 2st request
DMA 3st request
DMA request ++
149
150
ADC Flags and interrupts
OVRIE
EOCIE
JEOCIE
AWDIE
Interrupt enable
bits
ADCx
Global interrupt
(NVIC)
STRT
JSTRT
OVR
EOC
JEOC
AWD
Flags
OVR : Overrun detection when regular converted data are
lost
JEOC : Injected channel end of conversion to indicate at
the end of injected GROUP conversion
STRT: Regular channel start to indicate when regular
CHANNEL conversion starts.
JSTRT: Injected channel start to indicate hardware when
injected GROUP conversion starts.
EOC : Regular channel end of conversion to indicate
(depending on EOCS bit) the end of :
a regular CHANNEL conversion
sequence of regular GROUP conversions .
AWD : Analog watchdog to indicate if the converted
voltage crosses the programmed thresholds values.
Flag for ADC regular channels
Flag for ADC Injected channels
General Flag for the ADC
Direct Memory Access (DMA)
DMA Features
Dual AHB master bus architecture, one dedicated to memory accesses and
one dedicated to peripheral accesses.
8 streams for each DMA controller, up to 8 channels (requests) per stream (2
DMA controllers in STM32F4xx family). Channel selection for each stream is
software-configurable.
4x32-Bits FIFO memory for each Stream (FIFO mode can be enabled or
disabled).
Independent source and destination transfer width (byte, half-word, word):
when the source and destination data widths are different, the DMA
automatically packs/unpacks data to optimize the bandwidth. (this feature is
available only when FIFO mode is enabled)
Double buffer mode (double buffer mode can enabled or disabled).
Support software trigger for memory-to-memory transfers (available for the
DMA2 controller streams only)
152
DMA Features
The number of data to be transferred can be managed either by the DMA
controller or by the peripheral:
DMA flow controller: the number of data to be transferred is software programmable from 1 to 65535
Peripheral flow controller: the number of data items to be transferred is unknown and controlled by the
source or the destination peripheral that signals the end of the transfer by hardware.
Independent Incrementing or Non-Incrementing addressing for source and
destination. Possibility to set increment offset for peripheral address.
Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is
software-configurable, usually equal to half the FIFO size of the peripheral
Each stream supports circular buffer management.
5 event flags (DMA Half Transfer, DMA Transfer complete, DMA Transfer Error,
DMA FIFO Error, Direct Mode Error) logically ORed together in a single interrupt
request for each stream
Priorities between DMA stream requests are software-programmable (4 levels
consisting of very high, high, medium, low) or hardware in case of equality (request
0 has priority over request 1, etc.)
153
DMA1 Controller
DMA1
High Priority Request Low Priority Request
Stream 0
SPI3_RX
I2C1_RX
TIM4_CH1
I2S3_EXT_
RX
UART5_RX
--
TIM5_CH3
TIM5_UP
--
Stream 1
--
--
--
TIM2_UP
TIM2_CH3
USART3_R
X
--
TIM5_CH4
TIM5_TRIG
TIM6_UP
Stream 2
SPI3_RX
TIM7_UP
I2S2_EXT_
RX
I2C3_RX
UART4_RX
TIM3_CH4
TIM3_UP
TIM5_CH1
I2C2_RX
Stream 3
SPI2_RX
--
TIM4_CH2
I2S2_EXT_
RX
USART3_T
X
--
TIM5_CH4
TIM5_TRIG
I2C2_RX
Stream 4
SPI2_TX
TIM7_UP
I2S2_EXT_T
X
I2C3_TX
UART4_TX
TIM3_CH1
TIM3_TRIG
TIM5_CH2
USART3_T
X
Stream 5
SPI3_TX
I2C1_RX
I2S3_EXT_T
X
TIM2_CH1
USART2_R
X
TIM3_CH2
--
DAC1
Stream 6
--
I2C1_TX
TIM4_UP
TIM2_CH2
TIM2_CH4
USART2_T
X
--
TIM5_UP
DAC2
Stream 7
SPI3_TX
I2C1_TX
TIM4_CH3
TIM2_UP
TIM2_CH4
UART5_TX
TIM3_CH3
--
I2C2_TX
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
OR OR OR OR OR OR OR OR
154
DMA2 Controller
DMA2
High Priority Request Low Priority Request
Stream 0
ADC1
--
ADC3
SPI1_RX
--
--
TIM1_TRIG
--
Stream 1
--
DCMI
ADC3
--
--
USART6_R
X
TIM1_CH1
TIM8_UP
Stream 2
TIM8_CH1/2
/3
ADC2
--
SPI1_RX
USART1_R
X
USART6_R
X
TIM1_CH2
TIM8_CH1
Stream 3
--
ADC2
--
SPI1_TX
SDIO
--
TIM1_CH1
TIM8_CH2
Stream 4
ADC1
--
--
--
--
--
TIM1_CH4/_
TRIG/_COM
TIM8_CH3
Stream 5
--
--
CRYP_OUT
SPI1_TX
USART1_R
X
--
TIM1_UP
--
Stream 6
TIM1_CH1/2
/3
--
CRYP_IN
--
SDIO
USART6_T
X
TIM1_CH3
--
Stream 7
--
DCMI
HASH_IN
--
USART1_T
X
USART6_T
X
--
TIM8_CH4/_
TRIG/_COM
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
OR SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger OR SW_Trigger
155
Streams and Channels configuration
Each DMA Stream is connected to 8 channels (requests).
Software selection of which channel should be active for a given stream by setting CHSEL[2:0] bits in
DMA_SxCR register.
Only one Channel can be active for a given Stream.
A Channel may be not connected to any physical request on the product (ie. DMA1 Stream1 Channel
0).
A Channel may also be connected to more than one request from the same peripheral (ie. DMA1
Stream1 Channel 4 is connected to TIM2_UP and TIM2_CH3 requests).
Software requests are used for Memory-to-Memory transfers and are available only on DMA2
controller.
156
Transfer size and Flow controller
Either the DMA or the Peripheral determine the amount of data to transfer
DMA is the flow controller: (to most applied)
Number of data items to be transferred is determined by the DMA through the value in
register DMA_SxNDTR.
DMA_SxNDTR register: from 1 to 65535 bytes/half-words/words and decrements
Number of data items is relative only to Peripheral side
in Memory-to-Memory mode, the source memory is considered as
peripheral
Peripheral is the flow controller: SDIO only
The number of transfers is determined only by the peripheral.
Used when the transfer size is unknown to the DMA
When transfer is complete, the peripheral sends End of Transfer Signal to DMA
when number of transfers is reached.
DMA_SxNDTR register can be read when transfer is ongoing to know the
remaining number of transfers.
157
FIFO: Data Packing/Unpacking
When FIFO mode is enabled (direct mode disabled) the DMA manage the data format difference
between source and destination (data Packing and Unpacking).
Supported operations:
8-bit / 16-bit 32-bit / 16-bit (Packing)
32-bit / 16-bit 8-bit / 16-bit (Unpacking)
This feature allows to reduce software overhead and CPU load.
A1
B1
C1
D1
A1 B1 C1 D1
A2
B2
C2
A2 B2 C2 D2
A1 B1 C1 D1
T1
T2
T4
T3
T5
T6
T7
T1
T2 A2 B2 C2
D2
T8
DMA FIFO
D2
A1 B1 C1 D1
A2 B2 C2 D2
A1 B1
T1
T2
T4
T3
T1
T2
Source data width = 8-bit
Destination data width = 32-bit
8 transfers are performed from source to DMA FIFO.
2 transfers are performed from DMA FIFO to destination.
DMA FIFO
Data Packing Example (8-bit 32-bit) Data Unpacking Example (32-bit 16-bit)
A1 B1 C1 D1
A2 B2 C2 D2
C1 D1
A2 B2
C2 D2
Source data width = 32-bit
Destination data width = 16-bit
2 transfers are performed from source to DMA FIFO.
4 transfers are performed from DMA FIFO to destination.
158
FIFO: Threshold & Burst mode
Threshold:
Threshold level determines when the data in the FIFO should be transferred to/from Memory.
There are 4 threshold levels:
FIFO Full ,1/2 FIFO Full, FIFO Full, FIFO Full
When the FIFO threshold is reached, the FIFO is filled/flushed from/to the Memory location.
Burst/Single mode:
Burst mode is available only when FIFO mode is enabled (direct mode disabled)
Burst mode allows to configure the amount of data to be transferred without CPU/DMA
interruption.
Available Burst modes:
INC4: 1 burst = 4-beats (4 Words, 8 Half-Words or 16 Bytes)
INC8: 1 burst = 8-beats (8 Half-Words or 16 Bytes)
INC16: 1 burst = 16-beats (16 Bytes)
When setting Burst mode, the FIFO threshold should be compatible with Burst size:
Memory Data Size Burst Size Allowed Threshold levels
Byte
4-Beats (INC4) , , and Full
8-Beats (INC8) & Full
16-Beats (INC16) Full
Half-Word
4-Beats (INC4) & Full
8-Beats (INC8) Full
Word 4-Beats (INC4) Full
Notes:
For Half-Word Memory
size, INC16 is not possible.
For Word Memory size,
INC8 and INC16 are not
possible.
159
Circular & Double Buffer modes
Circular mode:
All FIFO features and DMA events (TC, HT, TE) are available in this mode.
The number of data items is automatically reloaded and transfer restarted
This mode is NOT available for Memory-to-Memory transfers .
Double Buffer mode: (circular mode only)
Two Memory address registers are available (DMA_SxM0AR & DMA_SxM1AR)
Allows switch between two Memory buffers to be managed by hardware.
Memory-to-Memory mode is not allowed
A flag & control bit (CT) is available to monitor which destination is being used for data
transfer.
TC flag is set when transfer to memory location 0 or 1 is complete.
Peripheral Data Register
DMA_SxM0AR
DMA_SxM1AR
CT TC HT
Memory location 0 Memory location 0 Memory location 1 Memory location 1
CT = 1
CT = 0
DMA_SxPAR
160
DMA Events and Interrupt Flags (1/2)
Each DMA Stream has its own events flags and interrupts.
DMA Enable (EN):
EN bit is a control AND status bit.
If the DMA is disabled while a transfer is ongoing, the current transfer is completed then the DMA
Enable bit is updated (cleared).
If the DMA is disabled while some data are still present in FIFO, these data are flushed to memory
then the DMAE flag is updated (cleared).
DMA allows suspending the current transfer by clearing EN bit then resume the transfer by setting
EN bit again.
EN bit is cleared by hardware when:
End of transfer is reached (not applicable in circular mode).
A transfer error occurs on AHB buses.
FIFO threshold is not compatible with the burst size.
Transfer Completion (TC):
TC flag is set when all the data configured in DMA_SxNDTR register has been actually
transferred to destination.
Half Transfer Complete (HT):
HT is set when half of data configured in DMA_SxNDTR register has been transfered.
161
DMA Events and Interrupt Flags (2/2)
Transfer Error (TE):
Can indicate a bus error occurs during a DMA read or a write access.
Can indicate a write access is requested by software on a memory address register in
Double buffer mode whereas the stream is enabled and the current target memory is the
one impacted by the write into the memory address register
Direct mode Error (DME):
Is available only in: Peripheral-to-Memory mode, in Direct mode, when Memory
Incrementation is disabled.
Indicates that a new data is being transferred to memory location whereas the previous
transfer is not complete yet.
FIFO Error (FE):
Indicates FIFO Underrun/overrun condition or Threshold-burst size incompatibility.
Each of TC, HT, TE, DME and FE events can independently generate an
interrupt when relative interrupt enable bits is set.
162
Transfer modes summary
DMA
transfer
mode
Flow
Controller
Circular
mode
Transfer
Type
Direct Mode
Double Buffer
mode
Peripheral-
to-Memory
DMA Possible
Single Possible
Possible
Burst Forbidden
Peripheral Forbidden
Single Possible
Forbidden
Burst Forbidden
Memory-to-
Peripheral
DMA Possible
Single Possible
Possible
Burst Forbidden
Peripheral Forbidden
Single Possible
Forbidden
Burst Forbidden
Memory-to-
Memory
DMA Forbidden
Single
Forbidden Forbidden
Burst
163
HANDS-ON!!!
164
Open ADC3_DMAProject
C:\STM32F4-Discovery_FW_V1.1.0\Project\Exercises\ADC3_DMA\EWARM
Double-click on ADC3_DMA.eww to open the project
165
Hands on ADC + DMA exercise
Proposition: Fill the missing lines
Configure the PC2 as Analog Input, with No Pull
Configure the ADC3_CH12 with 12b resolution, continuous mode with
no External Trigger and enable the DMA to work with ADC3
Configure the DMA channel 2 to work from Peripheral to memory
transfer
Main functions:
GPIO_Init
DMA_Init
ADC_Init
ADC_RegularChannelConfig
ADC_DMACmd
166
Digital-to-analog converter (DAC)
DAC Features
Two DAC converters: one output channel for each one
8-bit or 12-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave or Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
DMA underrun error detection
External triggers for conversion
DAC supply requirement: 1.8V to 3.6 V
Conversion range: 0 to 3.6 V
DAC outputs range: 0 DAC_OUTx VREF+ (VREF+ is available
only in 100, 144 and 176 pins package)
168
DAC Channelx Block Diagram
169
TIM2_TRGO
TIM4_TRGO
TIM6_TRGO
TIM7_TRGO
TIM9_TRGO
VREF+
VDDA
VSSA
Ext_IT_9
DMA Request x DMA Request x
DAC Control Register
Digital to Analog Converter x
Control Logic x
Trianglex LFSRx
DHRx
DORx
SWTRIGx
T
S
E
L
x
[
2
:
0
]
M
A
M
P
x
[
3
:
0
]
W
A
V
E
x
[
1
:
0
]
T
E
N
x
D
M
A
E
N
x
12 bits
12 bits
12 bits
DAC_OUTx
DAC Output Voltage
The analog output voltages on each DAC channel pin are determined
as:
DAC Output = V
REF+
x (DOR / 4095)
Each DAC Channel integrates an output buffer, enabled through
BOFFx bit, can be used to reduce the output impedance.
170
Single DAC Channel Data Format
One data holding register for each data alignment and for
each DAC Channel
171
12 bits Right 12 bits Right alignment alignment : Load DAC_DHR12Rx [11:0]
12 bits 12 bits Left Left alignment alignment : Load DAC_DHR12Lx [15:4]
8 bits Right 8 bits Right alignment alignment: Load DAC_DHR8Rx [7:0]
D7 D6 D5 D4 D3 D2 D1 D0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DAC_DHR8Rx
DAC_DHR12Rx
DAC_DHR12Lx
DAC Conversion triggers
Programmable DAC conversion triggers
Conversion started (Load of DORx register) by:
Automatically: After one APB1 clock cycle (external trigger disabled TENx
reset)
Triggered conversion: After three APB1 clock cycles (external trigger
enabled TENx set) and generated by :
Software trigger though SWTRIGx (Only one APB1 clock cycle is needed)
TIM2, 4, 5..8 TRGO
EXTI Line9
172
Noise Wave Generation
Generate a variable amplitude pseudo-noise based on a Linear Feedback
Shift Register (LFSR): used in ADC over sampling purposes for example
Initial Linear Feedback Shift Register value is 0xAAA.
The LFSR 12bits value can be masked partially or totally
Anti lock-up mechanism: if LFSR equal to 0 then a 1 is injected on it
Calculated noise value, updated through external trigger, is added to the
DAC_DHRx content without overflow
173
11 10 9 8 7 6 5 4 3 2 1 0
XOR
12
NOR
X
12
X
0
X
X
4
X
6
Triangle Wave Generation
Add a small-amplitude triangular waveform on a DC or slowly varying signal:
used as basic waveform generator for example
Calculated triangle value, updated through external trigger, is added to the
DAC_DHRx content without overflow to reach the configurable max amplitude
Up-Down triangle counter:
Incremented to reach defined max amplitude value
Decremented to return to the initial base value
Triangle max amplitude values are: (2
N
1) with N=[1..12]
174
DAC_DHRx: Base value
MAMPx[3:0]: Max amplitude
DMA
DMA available on both DAC Channels
A DAC DMA request is generated when an external trigger occurs: The value
of the DAC_DHRx register is then transferred to the DAC_DORx register.
DMA underrun error detection with interrupt capability
175
DAC DAC
DMA
CPU
RAM
(Pattern Table
1)
(Pattern Table
2)
Channel
1 Output
Channel
2 Output
DAC Triggers
Dual DAC Channel mode
Both DAC channels can be used together: generate differential or
stereo signals in simultaneous conversion mode
11 DAC dual modes:
Independent trigger, without or with, same or different wave generation
(LFSR or Triangle)
Simultaneous software start
Simultaneous trigger, without or with, same or different wave generation
(LFSR or Triangle)
176
Dual DAC Channel Data Format
One data holding register for each data alignment for both DAC
channels
D7 D6 D5 D4 D3 D2 D1 D0
8 bits Right 8 bits Right alignment alignment: Load DAC Channel1 data to DAC_DHR8RD [7:0] and DAC Channel2 data to DAC_DHR8RD [15:8]
D7 D6 D5 D4 D3 D2 D1 D0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DAC Channel1 Data DAC Channel2 Data
DAC_DHR8RD
DAC_DHR12RD
DAC_DHR12LD
177
DAC Buffered output
To drive external loads without using an external operational amplifier, DAC
channels have embedded output buffers which can be enabled and
disabled depending on the user application.
When the DAC output is not buffered, and there is a load in the user
application circuit, the voltage output will be lower than the desired voltage.
Enabling the buffer, the voltage output and the voltage desired are similar.
DAC DAC_Channel_1
DOR = 0xFFF 3.3V
VSS
R
LOAD
>= 1.5 M
DAC_OUT
Output buffer disabled Output buffer enabled
DAC DAC_Channel_1
DOR = 0xFFF 3.3V
VSS
R
LOAD
>= 5 K
Due to the R
LOAD
resistor the measured
voltage on output could be lower than the
required.
The measured output voltage is similar to
the required voltage despite of R
LOAD
: The
output buffer reduced the output impedance.
DAC_OUT
178
DAC Applications (1/2)
Audio applications such as: Security Alarms, Bluetooth headsets,
Talking toys, Answering machines, man-machine interfacing, and low-
cost music players
For analog purposes, such as analog waveform generation and control
engineering.
STM32 DAC Noise generation
ADC Oversampling for higher accuracy. More details about these methods are
explained in the STM32 Application note AN2668, Oversampling using white
noise section.
Electronic music production, frequency response testing of amplifiers and
electronic filters
STM32 DAC Triangular wave
Sound Synthesis
Modem circuit applications
179
DAC Applications (2/2)
Audio wave generation using the STM32 DAC sine wave
Typical Audio application
TIM6
DAC DAC
DMA
CPU
SPI
RAM
.WA
V
Application Note is available from www.st.com/mcu
AN3126: STM32 DAC for waveform and audio applications
180
DEMONSTRATION!!!
181
Open DAC_SignalsGeneration Project
C:\STM32F4-Discovery_FW_V1.1.0\Project\Exercises\ DAC_SignalsGeneration
\EWARM
Double-click on DAC_SignalsGeneration.eww to open the project
182
DEMONSTRATION!!!
183
Open Audio_playback_and_record Project
C:\STM32F4-
Discovery_FW_V1.1.0\Project\Audio_playback_and_record\EWARM
Double-click on Audio_playback_and_record.eww to open the project
184
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
USART Features (1/2)
6 USARTs: USART1 & USART6 on High speed APB2 and USART2,3,4,5 on
Low speed APB1
Fully-programmable serial interface characteristics:
Data can be 8 or 9 bits
Even, odd or no-parity bit generation and detection
0.5, 1, 1.5 or 2 stop bit generation
Programmable baud rate generator
Integer part (12 bits)
Fractional part (4 bits)
Baud rate for standard USART (SPI mode included)
Tx/Rx baud = fck/8x(2-OVR8)xUSARTDIV
Where:
Tx/Rx baud: desired baudrate
OVR8: oversampling by 8 (1 if enabled, 0 if disabled)
fck: APB frequency
USARTDIV: value to be programmed to the BRR register
Up to 10.5 Mbps
186
USART Features (2/2)
Support hardware flow control (CTS and RTS)
Dedicated transmission and reception flags (TxE and RxNE) with interrupt capability
Support for DMA
Receive DMA request and Transmit DMA request
10 interrupt sources to ease software implementation
LIN Master/Slave compatible
Synchronous Mode: Master mode only
IrDASIR Encoder Decoder
Smartcard Capability
Single wire Half Duplex Communication
Multi-Processor communication
USART can enter Mute mode
Mute mode: disable receive interrupts until next header detected
Wake up from mute mode (by idle line detection or address mark detection)
Support One Sample Bit method: allows to disable noise detection (for noise-free
applications) in order to increase the receivers tolerance to clock deviations.
187
Clock deviation
tolerance up to
4.375%
DMA Capability
Each USART has a DMA Tx and Rx requests
Each of the USARTs requests is mapped on a separate DMA stream:
possibility to use DMA for all USARTs transfer direction at the same
time
188
Synchronous Mode
USART supports Full duplex synchronous communication
mode
Full-duplex, three-wire synchronous transfer
USART Master mode only
Programmable clock polarity (CPOL) and phase (CPHA)
Programmable Last Bit Clock generation
Transmitter Clock output (SCLK)
Slave
SCK
MISO
MOSI
NSS
Master
SCLK
Rx
Tx
Full Duplex Full Duplex
USART SPI
189
IrDA SIR Encoder Decoder
USART supports the IrDA Specifications
Half-duplex, NRZ modulation,
Max bit rate 115200 bps
3/16 bit duration for normal mode
Low power mode: 1.42MHz<USART Prescaler<2.12MHz
Half Half Duplex Duplex
USART
Tx/ SW_Rx
SIR Transmit
Encoder
SIR Receive
Decoder
USART Tx
IrDA OUT
IrDA IN
190
Smart Card mode
USART supports Smart Card Emulation ISO 7816-3
Half-Duplex, Clock Output (SCLK)
9Bits data, 0.5 Stop Bit in receive, 1.5 Stop Bits in transmit
Parity Error Generation with NACK transmission
Programmable Guard Time
Programmable Clock Prescaler to guarantee a wide range clock
input
USART
Tx
SCLK
191
Single Wire Half Duplex mode
USART supports Half duplex synchronous communication mode
Only Tx pin is used (Rx is no longer used)
Used to follow a single wire Half duplex protocol.
USART2
Rx
USART1
Tx
V
DD
R

=

1
0

K
Half Half Duplex Duplex

192
DEMONSTRATION!!!
193
C:\STM32F4-Discovery_FW_V1.1.0\Project\USART\EWARM
Double-click on Project.eww to open the project
194
SERIAL PERIPHERAL INTERFACE
(SPI)
Same as STM32F-1
SPI Features (1/2)
Two SPIs: SPI1 on high speed APB2 and SPI2 on low speed APB1
Full duplex synchronous transfers on 3 lines
Simplex synchronous transfers on 2 lines with or without a bi-
directional data line
Programmable data frame size :8- or 16-bit transfer frame format
selection
Programmable data order with MSB-first or LSB-first shifting
Master or slave operation
Programmable bit rate: up to 37.5 MHz in Master/Slave mode
NSS management by hardware or software for both master and
slave: Dynamic change of Master/Slave operations
TI mode (master and slave operations).
196
Up to 37.5MHz
bit rate
SPI Features (2/2)
Programmable clock polarity and phase
Dedicated transmission and reception flags (Tx buffer
Empty and Rx buffer Not Empty) with interrupt capability
SPI bus busy status flag
Master mode fault and overrun flags with interrupt
capability
Hardware CRC feature for reliable communication
Support for DMA
197
DMA Capability
Each SPI has a DMA Tx and Rx requests
Each of the SPIs requests is mapped on a different DMA Stream:
possibility to use DMA for all SPIs transfer direction at the same
time
Calculated CRC value is automatically transmitted at the end of
data transfer
198
Data Frame Format (Motorolla mode)
Master
SCK
MISO
MOSI
NSS
Data frame format :
selection
Programmable data order with MSB-first or LSB-first shifting
88--bit long bit long
16 16--bit long bit long
MSB first MSB first
LSB first LSB first
MSB first MSB first
LSB first LSB first
V
DD
0xD7 0xD7
0xD7 0xD7
0xD739 0xD739
0xD739 0xD739
199
Data Frame Format (TI mode)
Master
SCK
MISO
MOSI
NSS
Data frame format :
selection.
Clock polarity and phase and NSS are managed by hardware to be
compliant to TI mode.
200
Slave
SCK
MISO
MOSI
NSS
NSS NSS
Dont care
MSB
..
LSB
floating
MSB
..
LSB
0/1
MSB
MSB
SCK SCK
MISO MISO
MOSI MOSI
Full Duplex Communication
Slave
SCK
MISO
MOSI
NSS
Master
SCK
MISO
MOSI
NSS
SPI supports Full duplex and Rx-Only communication mode :
Full-duplex, three-wire (four wire for TI mode) synchronous transfer
Full Duplex ( Full Duplex (Motorolla Motorolla mode) mode)
V
DD
201
Slave
SCK
MISO
MOSI
NSS
Master
SCK
MISO
MOSI
NSS
Full Duplex (TI mode) Full Duplex (TI mode)
Simplex Communication
Slave
SCK
MISO
MOSI
NSS
Master
SCK
MISO
MOSI
NSS
SPI supports simplex communication mode:
Bidirectional: 1 Clock and 1 bi-directional data wire (One bit direction
transfer control)
Rx-Only: 1 Clock and 1 unidirectional data wire
V
DD
Slave
SCK
MISO
MOSI
NSS
Master
SCK
MISO
MOSI
NSS
Rx Rx Only Only (Slave) (Slave)
V
DD
Bi Bi--directional directional
202
NSS Hardware & Software Management
Hardware NSS Hardware NSS
Slave
SCK MISOMOSINSS
Master
SCK MISOMOSINSS
V
DD
Software NSS Software NSS
Slave
SCKMISOMOSINSS
Master
SCK MISOMOSINSS
Both Master and Slave
NSS pins could be used
for other purpose
Provides the possibility of
dynamic change of
Master/Slave operations:
No hardware limitation to
switch from master to
slave or slave to master in
the same application
203
Note. These configurations are not applicable for TI mode. In TI
mode master and slave NSS lines should be connected.
Single Master: SS output Management
Slave
SCK MISOMOSINSS
Master
SCK MISOMOSINSS
Slave
SCKMISOMOSINSS
Slave
SCKMISOMOSINSS
Enable SS output
capability
Each device can be a unique
master by enabling its NSS as
output and driving it low: all
other devices became slaves.
No need for external GPIO
pin to drive slaves NSS pins
204
CRC Calculation (1/2)
Hardware CRC feature for reliable communication (only for Full Duplex mode) :
Separate CRC calculators implemented for transmitted and received data
CRC value can be transmitted as last byte in transmission mode
CRC error checking for last received byte and interrupt generation on error
Programmable CRC polynomial calculation
CRC calculation based on:
CRC8 for 8-bit data
CRC16-CCITT standard for 16-bit data
205
Basic SD/MMC support (SPI protocol):
Performance: speed up to 16MHz
Error checking: hardware CRC calculation
Master
SCK
MISO
CS
V
DD
R

=

4
.
7

K
MOSI
V
DD
9 1

2

3

4

5

6

7

8
206
MOSI MOSI
SCK SCK
Example of n data transfer between two SPIs followed by the CRC transmission of
each one in Full-duplex mode
MISO MISO
Taken Taken from from SPI1 TXCRC SPI1 TXCRC register register and sent to SPI2 and sent to SPI2
Taken Taken from from SPI2 TXCRC SPI2 TXCRC register register and sent to SPI1 and sent to SPI1
Data 2 Data n CRC[1..n] Data 1
Data 2 Data n CRC[1..n] Data 1
207
DEMONSTRATION!!!
208
C:\STM32F4-Discovery_FW_V1.1.0\Project\Exercises\MEMS\EWARM
Double-click on LIS302DL.ewwto open the project
209
Other features & softwares
210
STM32 Firmware solutions
Free solutions
From ST
From Open Source
Big 3
rd
parties network
More than 25 companies
with STM32 solutions
More than just Silicon
211
MicroXplorer: STM32 configuration tool
Product Selection
Peripherals configuration
Pinout configuration
Conflicts resolution
www.st.com/microxplorer
212
STM32F4 Support
coming soon
ST-Link
In-circuit debugger and programmer
for the STM32
JTAG and SWD interfaces
Powered by the USB Full Speed
interface
Supports target voltages from 1.65V
to 3.6V
Works with Atollic, IAR, Keil and
Tasking IDEs
Works with ST tools including ST-Link
Utility and STM Studio
213
Available from all ST distributors
Ordering code: ST-Link/V2
ST-Link Utility
214
Fast in system programming
Interfaces with all versions of
ST-Link (internal/external
V1/V2)
Supports JTAG and SWD
GUI and command line
interface
Supports flash and option
byte programming/erasing
Boot Loader / Flash Loader
Demonstrator
215
The ST boot loader code is in flash, separate
from and in addition to the user flash
The boot loader code is programmed at STs
factory and is fixed
Activated at reset based on the Boot0 pin and
Boot1 option bit configuration on the F0
Supports USART1 interface on the F0
Supports flash and option byte programming
and erasing
Flash Loader Demonstrator is a Windows
application that interfaces to the ST bootloader
(command line interface is available)
STM Studio: Software Scope
For STM8 and STM32
Non intrusive data gathering
Uses your codes variables
www.st.com/stmstudio
On the fly or snapshot acquisition
Offline Replay, Statistical analysis
Dynamic update of variable values
216
Thank you
www.st.com/stm32f4
Glossary
ART Accelerator : STs adaptive real-time accelerator
CMSIS: Cortex microcontroller software interface standard
MCU: microcontroller unit
DSC: digital signal controller
DSP: digital signal processor
FPU: floating point unit
RTC: real-time clock
MPU: memory protection unit
FSMC: flexible static memory controller
CCM : Core Coupled Memory

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STM32 F4 Seminar and Hands-On

Note: Note: Do not use discontinuous mode for both

Half Half Duplex Duplex

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