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A Benchmark System for Digital Time-Domain Simulation of an Active Power Filter

Contributors: E. D. Lavers and P. W. Lehn, Member, IEEE/Task Force Members: M. R. Iravani, Chair, D. Durbak, D. Fletcher, P. Wilson, R. Wachal, K. Sen, J. Martinez, B. Johnson, H. Tyll, B. Feero, A. Sannino, G. Sybille, and A. Keri

AbstractA benchmark system is presented for digital timedomain simulation of a shunt connected active power lter. The active power lter consists of a 3-phase voltage source converter operating under pulse-width modulation. The converter is controlled using a digital deadbeat current regulator. Harmonic prediction is employed to allow accurate harmonic compensation despite controller latencies. A PSCAD/EMTDC simulation model is developed based on a laboratory scale active power lter. By employing an experimental system as a basis, a pragmatic control structure, which accounts for all implementation constraints, is assured. Experimental measurements clearly validate the accuracy of the simulation model. Index TermsActive lters, digital control, power system harmonics, predictive control, pulse width modulated power converters.

I. INTRODUCTION

CTIVE power lters may be constructed out of singlephase or multi-phase converters using either voltage or current source converter topologies. To provide ltering action at frequencies well above the fundamental, converters must employ a switching frequency of several kHz or more. Only a very limited set of high power semiconductor devices are capable of operating at these frequencies, with the IGBT being the only device commercially available from a wide range of manufacturers. Intrinsic characteristics of the IGBT make these devices better suited for voltage source converter applications. Voltage source converters themselves are available in various congurations and include: single-phase [1], 3-wire 3-phase [2], 4-wire 3-leg 3-phase [3] or 4-wire 4-leg 3-phase [4]. Decision on the specic conguration is based on application, cost, complexity, and modularity of design. Of these four, it is the 3-phase, 3-wire converters that are typically the most cost effective, but with the caveat that they are unable to provide compensation of zero-sequence current components. Depending on application, either a xed switching frequency scheme, such as sinusoidal pulse-width modulation [5] and space vector modulation [6], or a variable switching frequency hysteresis control scheme may be selected [7]. Hysteresis based control schemes are documented to suffer from inter-phase
Manuscript received February 25, 2003; revised October 9, 2003. Paper no. TPWRD-00071-2003. The authors are with the IEEE PES Task Force on Simulation of FACTS and Customer Power Devices of the IEEE PES Working Group on Modeling and Analysis of System Transients Using Digital Programs Digital Object Identier 10.1109/TPWRD.2004.837815

distortion and the possible existence of undesirable limit cycle behavior [8]. Even if limit cycle behavior is avoided, hysteresis control still generally results in an unpredictable average converter switching frequency that varies with the operating conditions [7], [9]. It should be noted, however, that some novel hysteresis schemes have been proposed which employ a time varying hysteresis band to constrain the variations in switching frequency [10], [11]. In contrast to hysteresis type control schemes, xed switching frequency schemes produce predictable switching harmonics, predictable switching losses and they are not susceptible to limit cycle behavior. Furthermore, unlike hysteresis type control schemes, xed frequency schemes may be entirely implemented using digital components, leading to a more robust system. Review of recent literature in the area of power electronics shows a strong trend toward fully-digital control of high power converters based on predictive control techniques; also known as dead-beat control [12][16]. While various approaches to implementing such digital controllers exist, all designs target either a one switching cycle or two switching cycle controller response time. Thus, from the perspective of the power network, their responses are, to a rst order, nearly identical. Although xed frequency control schemes offer many advantages as compared to hysteresis control schemes, they suffer from more severe bandwidth limitations due to increased controller latencies. Of signicance is the fact that these latencies are precisely known a priori. Thus, for compensation of harmonic producing loads, such as diode rectiers or motor drives, harmonic prediction can be effectively used to compensate targeted harmonics with a high degree of accuracy [13], [17]. For compensation of loads with rapid time rate of change, such as welders or various other arcing loads, harmonic prediction is impossible1. In these applications the active lter must dynamically compensate the entire load current, excepting the fundamental frequency component. Complete elimination of harmonics is not achievable due to digital controller latencies and the limited response time of the converter. Although specialized hardware may be designed to minimize latencies for optimal performance [14], such specialty applications lie outside the scope of this paper.
1It should be noted that, strictly speaking, it is not valid to discuss the harmonics produced by arcing loads, since no window of periodicity exists over which to perform a Fourier Analysis. A typical spectral analyzer will only display some average harmonic spectrum from which the actual time varying load current cannot be re-constructed.

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Fig. 1.

A generalized shunt-connected active power lter conguration.

Despite the large body of work on active power lters, there exists a lack of simulation models to study generalized electromagnetic transients and lter/system interactions. Simulation using emtp-type programs is generally avoided due to the complexity of modeling digital sample-data controllers in these environments which were designed primarily for modeling circuits, machines, and analog controllers. Instead, control design is typically carried out using z-domain models based on the time averaging principle (which do not model converter switching harmonics) [1], [9], [14][17]. Although some validation can be carried out by simulation [15], [18] z-domain control design is invariably validated through experimental work on either a prototype or a scaled system [1], [4], [9], [12][18]. This paper presents a PSCAD/EMTDC simulation model of a digitally controlled 3-phase, 3-wire active power lter. The model is developed to mirror the response of a scaled laboratory active lter. Comparison of the simulation model with results taken from a 2 kVA experimental system is used to validate the model. The validated simulation model is fully parameterized so that its voltage rating, current rating, switching frequency or interface inductance may be easily modied without requiring modication of the converter controls. This allows the active power lter simulation model to be easily customized or to be interfaced to systems at different voltage levels. The structure of this paper may be summarized in the following way. First, the general operation of the active power lter is introduced. Second, the benchmark system, based on an experimental active power lter, is described, with a detailed discussion of the necessary control structure. Third, PSCAD/EMTDC simulation results are compared with experimental measurements to validate the simulation model, both transiently and in steady state. II. A GENERALIZED ACTIVE-POWER FILTER Fig. 1 shows a generic harmonic load connected to a simpli, of the ed model of an ac network. The internal voltage, network delivers power to a harmonic producing load drawing xed current . With no other elements in the circuit, the source current and load current must clearly equate. Load current harmonics therefore directly translate into source current harmonics. Source current harmonics, in turn, cause a harmonic voltage drop across the source impedance , resulting in harmonic distortion at the point of common coupling (PCC). Incorporating a shunt-connected Active Power Filter (APF) at or near the PCC, as shown in Fig. 1, can inject lter current . Under this new conguration, the xed voltage source and the

Fig. 2. Power circuit conguration used in benchmark system with relevant quantities dened.

APF act as parallel sources supplying the load, and becomes now a summation of and . This outcome is desirable because direct control of yields indirect control over , which is the intended effect. In particular, if the composition of is set to the spectrum of load harmonics, then that of is constrained solely to the load fundamental harmonic, notwithstanding some potential harmonic residue or high frequency noise. In effect, the addition of the APF will serve to lter the source current essentially of unwanted load harmonics, thereby decreasing voltage distortion at the PCC. III. THE BENCHMARK SYSTEM The active power lter benchmark system is two-part, consisting of a power electronic circuit of the general form depicted in Fig. 1 and a digital controller. Development of this system occurred rst as the establishment of a working real-time APF system in laboratory, and, second, as replication of those results in an off-line simulation created using PSCAD/EMTDC software. The PSCAD/EMTDC model is designed with the intent of identically mirroring the actual system, including all physical devices and digital control hardware, as well as important practical constraints inherent to the design of general APF systems. A. Power Circuit The power circuit, shown in Fig. 2, operates off a three-phase, 60 Hz, 115 V ac bus. A three-phase, full-bridge diode rectier, with a dc side resistor and an ac side choke, serves as a source of odd-numbered harmonics. Varying this resistance determines the peak amplitude of the load current waveform, which, in the present conguration, is about 35 A. The APF contains a Voltage Source Converter (VSC) comprised of a three-phase IGBT bridge with a large dc side capacitor. An interface inductor is used to connect the VSC with the ac bus. Specic values for these and all other relevant circuit elements are located in Table I. Diodes and IGBTs are modeled using an afne approximation of their V-I characteristic, with model parameters located in Table II. The diodes, which are used both in the load and the converter, in particular have an on-voltage of 0.7 V and an on-

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TABLE I POWER CIRCUIT SPECIFICATIONS

Fig. 3.

Overview of the active power lter VSC controller.

Fig. 4.

Control scheme used in the harmonic compensator.

TABLE II DIODE AND IGBT MODEL SPECIFICATIONS

and the PWM unit. Inputs for the VSC controller include the ac bus voltages , the load currents , the converter currents , on the dc link of the VSC; outputs and the capacitor voltage are the six gating pulses needed to operate the IGBTs in the VSC. Ac voltages and currents are vector quantities which, in general, may be expressed either as a column vector containing -variables, or as a column vector containing -variphase ables in accordance with the Clarke Transform [19]

resistance of 20 m ; the IGBTs have an on-voltage of 1.5 V and an on-resistance also of 20 m . For simulation purposes, an off-resistance of 1 M is assumed for all devices. The VSC employs sinusoidal pulse-width modulation (PWM), at a switching frequency of 3.06 kHz, in order to control the converter current . Implementation of its digital controller requires interaction between a few additional computer hardware modules. Voltage and current sensors in the circuit transmit all relevant signals to an array of Analog-to-Digital Converters (A/D), with sampling frequency of 6.12 kHz, for use in a user-dened control program written in C code. The control program is compiled and downloaded onto a TMS320C40 Digital Signal Processor (DSP) where it executes. The controller output is sent to a Complex Programmable Logic Device (CPLD), on which is dened a PWM program that generates the necessary VSC gating pulses. This interaction of software and hardware introduces a two time step implementation delay into the control of the VSC. This implies the elapse of two full sampling periods before a reference current sent into the digital controller can be seen on the ac terminals of the VSC. B. Digital Controller The VSC digital controller can be decomposed into the four essential interacting modules shown in Fig. 3: a Harmonic Compensator, a DC Voltage Controller, a Current Controller,
2 Since the source impedance was very small, only an approximate value of this impedance could be obtained; it was neglected in the simulation model. 3 The base impedance for the load was assumed to be 6.65
.

(1)

The inverse Clarke Transform may if necessary be employed -variables back into the -frame to transform

(2)

1) Harmonic Compensator: The harmonic compensator, shown in Fig. 4, captures the load current and, from it, derives , which consists of all load harmonics a current reference outside the fundamental component. To this end, it performs a one period sliding window Discrete Fourier Transform (DFT) on and resolves it into an -vector of Fourier coefcients expressed in complex magnitude-phase form. The length of this vector, although arbitrary, will typically be limitedin this case to 15by such factors as available computation time and the APF bandwidth. Regardless, this approach is robust, noise tolerant and conducive to removal of the fundamental load current component. The two principal tasks of the compensator are fullled in the frequency domain by operating on this n-vector in the following manner. The amplitude of rst coefcient is zeroed as a means of ltering the fundamental load current component from the time domain signal; to all remaining coefcients is simultaneously added a phase offset, suited to each frequency component,

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TABLE III DC VOLTAGE CONTROLLER CONSTANTS

Fig. 5.

Control scheme used in the dc voltage controller.

such that the overall effect is a two time step advance of the surviving signal components. The reasoning behind this advance is to counteract the two time step VSC implementation delay, thereby ensuring an in-phase relation between and . Finally, the processed coefcient vector is reconstituted into a time-domain waveform, which, as required, contains only load current harmonics. Fig. 4 depicts in block-diagram form this procedure. The load harmonic reference current output by the harmonic compensator will serve only as a fraction of the overall APF reference current. To it will be superimposed a small charging current, required to regulate the dc bus voltage, and described further in the following section. 2) DC Voltage Controller: The dc voltage controller, shown in Fig. 5, monitors the VSC dc side voltage and accordingly to maintain it at a user-dened requests a charging current reference. This signal, once computed, is superimposed onto to constitute the total converter reference current . is compared with A user-supplied reference voltage . The a low-pass ltered measurement of the dc voltage resulting voltage error is processed by a conventional proportional-integral (PI) controller, with characteristics located Table III. Attached to the output side of the PI is a hard limiter. These blocks together set the magnitude of the charging current to be drawn by the VSC and, if necessary, limit that current in order to avoid overloading the VSC. To ensure unity power factor operation, the phase and frequency of the charging current must be very near to those of the ac bus voltage . Therefore, the bus voltage is simply modulated by the charging current reference in order to meet this requirement. A correct phase relation with the ac bus again demands counteracting the VSC implementation delay through an initial two time step advance of . Note that the modulation process which yields introduces a scale factor of ampli. This scaling is accounted for in the tuning of the PI tude regulator. It should further be noted that normal operation of the APF may result in the appearance of dc bus voltage ripple at harmonic frequencies. It is essential that the dc voltage control loop not interfere with this natural phenomenon, otherwise ltering action will be degraded. Parameters of the low-pass lter are therefore selected to ensure that harmonic ripple does not propagate through the voltage control loop. Filter specications are also located in Table III. 3) Current Controller: The current controller, shown in Fig. 6, implements the governing equation for the active power lter system

Fig. 6. Control scheme used in the current controller.

The quantities and are the inductance and resistance of the APF lter inductor, while represents the converter current, the ac bus voltage, and the instantaneous VSC ac terminal voltage. Equation (3) is valid independent of whether voltages -quantities or and currents are expressed as vectors of phase -quantities. as vectors of By nature of the 3-phase APF topology, however, no zero sequence current can exist as the three converter currents must sum to zero. Incorporation of this constraint into the APF con-frame, since zero sequence trol equations is trivial in the components are already isolated. Thus control of only - and -currents need be realized. It is therefore sufcient to express voltages and currents in two-dimensional space vector (4) Translating (3) into discrete time via trapezoidal integration yields

(5) where represents the converter terminal voltage averaged over one sampling period. Although (5) is indeed valid for any chosen sample interval, implementation of a control based on (5) requires samples to be taken in synchronism with the peaks and valleys of the PWM carrier signal [16]. The converter current which appears in the next time step can then be controlled in the current time step. by selecting However, the VSC implementation delay is two time steps, forcing this equation to be iterated once, yielding

(3)

(6)

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A sufciently small sampling period allows for the two simplications (7) which has already been reected in (6), and (8) Additionally, the time step frequency according to is related to the system switching

(9) where is the converter switching frequency of 3.06 kHz. In this new form, it is consecutive measures of the average VSC ac terminal voltage which control the converter current that is to appear after two time steps. is normalized Finally, average VSC ac terminal voltage , by the transformation to a vector (10) is the modulation index vector, with magnitude no where greater than unity. Equating the future converter current to yields the nal form of the control the converter reference , reads equation, which, when solved for (11) In this nal form, the current controller uses the externally deto determine the normalized voltages ned reference necessary to actualize that reference on the ac terminals of the VSC in two time steps. The control equation calculates the precise VSC terminal voltage required to effect the desired change in after exactly two time steps. But it is clearly the case that the VSC cannot output on its ac side a line-to-line voltage which exceeds that residing on its dc link. A space vector limiter block is therefore attached to the output of the control equation to ensure that all requests are physically viable. This block identies all space vectors with length greater than unity and reacts accordingly by normalizing those lengths while preserving their phase relation with the real axis. All space vectors with lengths less than unity pass through this block unaffected. Note that the control will not function correctly during overmodulation without the presence of the space vector limiter. The last term in (11) represents the previously implemented a numerical quantity stored digitally in the convalue of troller. If the converter did not implement this requested value due to lack of dc voltage, control operation would be of compromised. is then transformed back The reference voltage vector -frame through the inverse Clarke Transform and into the this result is sent to the PWM unit. 4) Pulse-Width Modulator: The remaining module of importance in the digital controller is the PWM unit. The three
Fig. 7. Phase A load current, taken as a reference for an uncompensated source current.

phase components of the normalized reference voltage vector are each compared with a digitally generated triangular carrier waveform to generate gating pulses. The PWM unit operates using a triangle carrier waveform of unit magnitude and frequency of 3.06 kHz, which is half the sampling frequency of 6.12 kHz. Thus two reference voltage vectors are implemented every period of the carrier. IV. RESULTS Testing of the PSCAD/EMTDC simulation benchmark model occurs in three trials: steady-state response, load switch-on transient response, and dc voltage response. The simulation time step used for all simulation cases is 25 s. A. Steady State Response The rectier load, when connected to the 115 V rms bus, draws a 35 A peak amplitude current having the waveform shown in Fig. 7. Since and must equal in cases where the APF is not online, this waveform may also be construed as the unltered or uncompensated source current. Moreover, it has been posited that with the APF in the circuit and gating correctly, the source current is to be ltered almost entirely of its load current harmonics, resulting in a sinusoid of near equivalent fundamental magnitude and suffering only from harmonic residue and high frequency noise. Fig. 8 shows two waveforms each representing the ltered phase A source current, the rst of which is taken from the experimental setup, the second from the simulation. These two results agree with each other and with the predictions. Similar correspondence is also exhibited in the experimental and simulated converter currents, shown in Fig. 9. What is important to note in both the latter two pairs of waveforms is the close correlation between experimental and simulation in terms of high frequency harmonics. In particular,

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Fig. 8. Phase A source current, taken with the APF included in the power circuit conguration.

Fig. 10. Harmonic content of the phase A source, load and converter currents, taken with the APF included in the power circuit conguration.

Fig. 9. Phase A converter current, taken with the APF included in the power circuit conguration.

very similar relative positions and amplitudes are indicative of comparable switch duty cycles. Time domain observations are corroborated by the harmonic spectra of these waveforms, obtained through a DFT and shown in Fig. 10. Shown in these plots are only those harmonics both present in the load current in appreciable amounts and compensated for in the experimental setup. Limitations in processor speed on the DSP restricted compensation to only four harmonics of interest: 5th, 7th, 11th, and 13th. Consequently, the simulation was programmed also to compensate for only these four harmonics, even though it has the internal capability to compensate all harmonics up to and including the 31st. Of note in these two plots is the distribution of load harmonics between the source and converter currents. As intended, the source current consists almost entirely of fundamental frequency current,

while the converter current is a summation of every other nontrivial load harmonic. The near identical spectra conrm that the simulation can indeed recreate the laboratory environment. The only trend consistently differentiating the two results is the slightly superior performance of the simulation. Sources of discrepancy include: nonlinear effects and loss effects associated with the ferromagnetic cores of the experimental converter inductors, effects of switching losses, nonnegligible dead-time, and limited data precision from the A/D converters due electromagnetic interference and discretization effects. It should be recognized that supply voltage harmonics will also inuence the active lter current. This undesirable effect is mitigated to a large extent by the active lter current controller, however, large voltage harmonics will reduce the performance of the active lter to some extent. The laboratory voltage supply employed by the experimental system contained a total harmonic distortion of approximately 2%. This distortion was primarily composed of 11th, 13th, 23rd, and 25th harmonics. As seen from Fig. 11, the supply voltage harmonic distortion has only minor impact on the active lter operation. Regardless, even in the experimental system, source current dB harmonics are present in concentrations ranging from dB with respect to the fundamental harmonic. to about dB; As context, background noise was measured at about therefore even the largest residual harmonic lies only 20 dB above the noise oor of the experimental system. Considering all the sources of noise and computational limitations in the laboratory setup, this may be considered good overall performance. Fig. 11 isolates the source current from each environment and plots it against the unltered standard in order to provide a more direct comparison of performance. It clearly shows that harmonic content was almost uniformly removed from the uncompensated source current by about 20 dB, per harmonic, in

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Fig. 11. Direct comparison of ltered phase A source current with the initially unltered phase A source current.

Fig. 13. Phase A load switch-on source current, taken with the APF included in the power circuit conguration.

Fig. 12. Phase A load switch-on current, generated by the closing of a three-phase knife switch.

both experiment and simulation. Here is further conrmation of the fact that the simulation accords not only with the theoretical predictions, but with the practical implementation. B. Load Switch-On Response A 3-phase knife-switch is interposed between the load and the ac bus voltage in order to create a load switch-on transient. One such transient, shown in Fig. 12, is used to gauge the response time of the APF to a changing load. That response time is governed by how quickly the harmonic compensator can react to the new steady-state of and output the correct reference cur. Since the essential component of the compensator is a rent DFT, which requires exactly one period to adjust, theory dictates should resume one full period that correct tracking of the after the load settles into steady state. The load switch-on transients of the phase A source current, shown in Fig. 13, conrm that in both experiment and simulation, the theoretical model holds true and that proper reference tracking resumes in roughly one full period. Even though both systems exhibit transitions of a comparable length, they do in fact differ slightly. Some deviations are discernible in the source current transients, in Fig. 13, but are unmistakable in the converter current transients, shown in Fig. 14.
Fig. 14. Phase A load switch-on converter current, taken with the APF included in the power circuit conguration.

This pair of waveforms still displays correspondence between the location of waveform peaks but not in terms of their relative amplitudes. This discrepancy appears to result from the differing DFT implementation algorithms used in the two environments. In particular the DFT algorithm used in simulation responds more slowly than the one period sliding window DFT implemented experimentally. As the DFT algorithm used in simulation was a built-in function of PSCAD/EMTDC, isolating the exact source of the discrepancy was not possible. Consequently, the two ostensibly identical blocks might have anywhere from a slightly to a signicantly different response to a nonperiodic or transitional waveform. For the APF system, results appear tolerable given that peak converter currents and system currents are at least similar. This transient test clearly highlights the hazards associated with using the more sophisticated components of a simulation package. Quite often, insufcient detail is available to reliably

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modulation, as required for higher power applications. The benchmark model may be interfaced to any user-supplied network in order to carry out system studies. Furthermore, it may be employed as a starting point for the development of customized active power lter simulation models. REFERENCES
[1] M. Sedighy, S. B. Dewan, and F. P. Dawson, A robust digital current control method for active power lters, IEEE Trans. Ind. Applicat., vol. 36, no. 4, pp. 11581164, Jul./Aug. 2000. [2] H. Akagi, New trends in active lters for power conditioning, IEEE Trans. Ind. Applicat., vol. 32, no. 6, pp. 13121322, Nov./Dec. 1996. [3] P. Verdelho and G. D. Marques, Four-wire current-regulated PWM voltage converter, IEEE Trans. Ind. Electron., vol. 45, no. 5, pp. 761770, Oct. 1998. [4] D. Shen and P. W. Lehn, Fixed-frequency space-vector-modulation control for three-phase four-leg active power lters, in Proc. Inst. Elect. Eng., Elect. Power Applicat., vol. 149, Jul. 2002, pp. 268274. [5] N. Mohan, T. Undeland, and W. Robbins, Power Electronics: Converters, Applications, and Design. New York: Wiley, 2003. [6] H. W. van der Broeck, H. C. Skudelny, and G. V. Stanke, Analysis and realization of a pulsewidth modulator based on voltage space, IEEE Trans. Ind. Applicat., vol. 24, no. 1, pp. 142150, Jan./Feb. 1988. [7] D. M. E. Ingram and S. D. Round, A novel digital hysteresis current controller for an active power lter, in Proc. Int. Conf. Power Electronics Drive Systems, vol. 2, 1997, pp. 744749. [8] D. M. Brod and D. W. Novotny, Current control of VSI-PWM inverters, IEEE Trans. Ind. Applicat., vol. 21, no. 4, pp. 562570, May/Jun. 1985. [9] R. Wu, S. B. Dewan, and G. R. Slemon, A PWM AC to DC converter with xed switching frequency, IEEEInd. Applicat. Soc., vol. 1, pp. 706711, 1988. [10] L. Malesani, P. Mattavelli, and P. Tomasin, High-performance hysteresis modulation technique for active lters, IEEE Trans. Power Electron., vol. 12, no. 5, pp. 876884, Sep. 1997. [11] B. K. Bose, An adaptive hysteresis-band current control technique of a voltage-fed PWM inverter for machine drive system, IEEE Trans. Ind. Electron., vol. 37, no. 5, pp. 402408, Oct. 1990. [12] L. Rossetto and S. Buso, Digitally-controlled single-phase single-stage ac/dc pwm converter, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 326333, Jan. 2003. [13] S.-G. Jeong and M.-H. Woo, DSP-based active power lter with predictive current control, IEEE Trans. Ind. Electron., vol. 44, no. 3, pp. 329336, Jun. 1997. [14] J. Mossoba and P. W. Lehn, A controller architecture for high bandwidth active power lters, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 317325, Jan. 2003. [15] R. Ottersten and J. Svensson, Vector current controlled voltage source converterDeadbeat control and saturation strategies, IEEE Trans. Power Electron., vol. 17, no. 2, pp. 279285, Mar. 2002. [16] P. Jintakosonwit, H. Fujita, and H. Akagi, Control and performance of a fully-digital-controlled shunt active lter for installation on a power distribution system, IEEE Trans. Power Electron., vol. 17, no. 1, pp. 132140, Jan. 2002. [17] S. Mariethoz and A. C. Rufer, Open loop and closed loop spectral frequency active ltering, IEEE Trans. Power Electron., vol. 17, no. 4, pp. 564573, Jul. 2002. [18] L. Malesani, P. Mattavelli, and S. Buso, Robust dead-beat current control for PWM rectiers and active lters, IEEE Trans. Ind. Applicat., vol. 35, no. 3, pp. 613620, May/Jun. 1999. [19] E. Clarke, Circuit Analysis of AC Power Systems. New York: Wiley, 1943.

Fig. 15. VSC dc side voltage transient response to a change in the usersupplied reference value.

use sophisticated built-in modules for critical studies unless complete module source-code is available. C. DC Voltage Response The dc voltage response of the APF is treated as the resultant transient observed on the dc link of the VSC when the user-supplied reference voltage is changed. Typically residing at 220 V, this trial charted a reference increase from 200 V to 225 V. Fig. 15 summarizes the experimental and simulation results. Equivalent in terms of trajectory, these two transients differ in terms of increased harmonic rippleparticularly second harmonicand also measurement noise in the experiment. The second harmonic ripple is attributable to imbalance in the laboratory supply voltage, while further harmonic ripple likely stems from other harmonic bus voltage distortion. Noise is purely a function of the measurement apparatus, which is affected by the switching transients of the converter. Otherwise, the 25 V difference is traversed in about 75 ms and with similar overshoot in both situations. Therefore, there is still good overall agreement between the two responses. V. CONCLUSION A benchmark model for a 3-phase active lter was presented. The proposed benchmark provides an experimentally validated simulation model of a deadbeat, digitally controlled active power lter. Harmonic prediction is employed in the benchmark model to permit use of low frequency pulse-width