Ece Compilation 190

PART 1
1.1 1.2 1.3 1.4 1.5
DOs AND DONTs Inside the Laboratory Room Safety Precautions Breadboarding Guide Guidelines in Performing an Experiment Up/Down Thinking
1.1 DOs AND DONTs Inside the Laboratory Room
Dos
1. Read and follow the safety precautions given here to avoid any untoward accident 2. Familiarize yourself with the layout of your laboratory room, including the location of some materials used during an emergency such as fire extinguisher and first-aid kit. 3. Do read and follow the Standard Operating Procedure (SOP) inside the laboratory room in order to perform your experiment smoothly. 4. Refer to the breadboarding guide for faster, accurate and safe construction of experimental circuits. 5. Be more careful when working with circuits carrying a current greater than 0.03 ampere to avoid severe electric shock. 6. Familiarize yourself with the proper use and care of the laboratory equipment and instruments. 7. Take care in performing any laboratory experiment and handling materials. 8. Check the functionality of all equipment and materials before and after use. 9. Keep your working area clean. 10. Do your work quietly.
DONTs
1. Do not eat, drink or smoke inside the laboratory room. 2. Do not write anything on the chairs, tables and walls of the laboratory room. 3. Do not play with the equipment and experiment materials while performing the experiment. 4. Do not place wet materials or containers filled with liquid on top of or near the laboratory equipment and components. 5. Do not perform an experiment with your hands wet. 6. Do not let any part of your body touch the ground when you are working with high voltage or high currents circuits. 7. Do not panic in case of emergency. 8. Do not perform any cardiopulmonary resuscitation to a victim of any accident (e.g electric shock) unless you are qualified or authorized to do so. 9. Do not apply mechanical shock to the equipment and measuring instruments especially to those with analog meter reading. 10. Do not directly touch a person who has just suffered electric shock. 11. Do not use long wire connector. 12. Do not touch both end terminals of a capacitor or inductor unless you are sure that it is already discharged. 13. Do not place any combustible materials near the power outlet or the experimental circuit.
1.2
Safety Precautions
1. Do not place any combustible materials near the power outlet 2. Avoid using a power cord with defects such as loose contact and exposed conductors. 3. Avoid using connecting wires with exposed conductors. 4. Make sure that the size of the connecting wires used in experimental circuit is large enough to carry the current flowing in the circuit. 5. Do all wiring connections with the power OFF. 6. Check all the wiring and components for proper connections, sizes, values, and orientations before turning the circuits power ON. 7. Be careful when working with circuits carrying a current greater than 30 mA. Currents of about 50 mA can cause severe electric shock, and currents of about 100 mA can kill a person. 8. Remove any jewelry which is conductive. 9. Avoid touching both end terminals of a capacitor or inductor unless you are sure that it has been discharged. 10. Check your measuring instrument for proper voltage/current/resistance settings before making any measurement. 11. Do not use any instrument, component or material above its rated voltage, current and power. 12. Refer to the instruments user manual for its care and safe use. 13. Refer to the breadboarding guide for the components safety.
1.3
Breadboarding Guide
Before you perform the experiments in this manual, it is helpful to read these time-tested guidelines on breadboarding a circuit: 1. 2. 3. 4. Do all wiring with the power OFF. Keep the wiring and component lead as short as possible. Wire the supply leads first to the Integrated Circuit. Try to wire all the ground leads to one point, the common power supply. This type of connection is called star grounding. Do not use a ground bus. 5. Recheck the wiring before applying power to the circuit. 6. Connect signal voltages to the circuit only when the IC is powered. 7. Take all measurements with respect to ground. For example, if a resistor is connected between two terminals of an IC, do not connect either a meter or an oscilloscope across the resistor, instead, measure the voltage on one side of the resistor and then on the other side and calculate the voltage across the resistor. 8. Avid using ammeters, if possible. Measure the voltage as in the step 7 and calculate the current. 9. Disconnect the input signal before the direct current (DC) power is removed. 10. The ICs will stand as much abuse. But never: a. Reverse the polarity of the power supplies. b. Drive the components particularly the ICs, input pins above the +Vcc potential. c. Leave all input signal connected with no power on the IC. or: leave all input signals with no power connected to the IC. 11. If unwanted oscillations appear at the output and the circuit connections seem correct: a. Connect a 0.1 F capacitor between the ICs + V pin and the ground. b. Shorten your leads and c. Check the test instrument, signal generator, load and power supply ground leads. They should come together at one point.
1.5
Guidelines in Performing an Experiment
These guidelines are important for the students to perform the experiment smoothly, obtain accurate data and results; and come up with a good observation, analysis and conclusion, within the allowed laboratory hours, without damaging any of the components or equipment, and without hurting anybody inside the laboratory class. 1. 2. 3. 4. 5. 6. 7. Read and apply the DOs and DONTs inside the laboratory room. Read and apply the safety precautions. Read and apply the breadboarding. Understand clearly the objectives of the experiment. Read the questions given in the experiment and try to answer them on paper. Thoroughly read and understand the procedure. From the procedures and respective experiment circuits, determine which are the independent and dependent variables for you to know which variables in the experiment should be observed. An independent variable is one whose value is not affected in any way by any change in value of another variable. Its value is constant at any given condition or being varied in the experiment. A dependent variable is one whose value is affected, i.e, increase or decreases as the independent variables change. 8. Refer to the safety precautions and breadboarding guides for proper circuit construction and operation. Be aware of and consistent with the units used on each variable for accurate reading and recording and interpretation of data obtained from the experiment.
9.
10. Apply the up/down thinking method in observing and analyzing the effects of the independent variables on the dependent variables. 11. From your observation and analysis, and based on the experiment objectives, derive the conclusion. The conclusion is usually written in one sentence only. You may now proceed with your first experiment.
1.5
Up/Down Thinking
Experiment performance does not end with the complete gathering of data and results from the experimental circuits. The gathered data and results must be properly observed and analyzed in order to come up with a correct conclusion and meet the given objectives of the experiment. UP/DOWN THINKING is introduced by Albert Paul Malvino in his book Electronic principle which is very helpful in observing and analyzing the results of an experiment. It will help you understand how circuit works, use formulas intelligently and arrive at a correct conclusion. It can also be used to troubleshoot your experimental circuit whenever a problem occurs during an experiment. UP/DOWN THINKING is a method of analyzing the effect of varying an independent variable on the dependent variable in a circuit. When an independent variable increases, each of the dependent variables will usually respond by increasing or decreasing. It can applied in a circuit following the given steps below: 1. 2. 3. 4. Determine the variables in the circuit. Determine which of these are independent and dependent variables. Determine the mathematical equation or formula that shows the relationship between these two variables. Using the formula, determine the changes (up/increase or down/decrease) on the dependent variable as you make changes to the independent variables.
EXAMPLE: Below is a simple circuit with a resistor connected across a voltage source. From this circuit, we have three variables: the voltage V, resistor R, and the current I. You will see ho Up/Down thinking can be applied, with the use of one basic formula to two different condition. Given circuit:
The tables show two different conditions that might occur on the given circuit. CONDITION1: Table A: R=100 VOLTAGE,V 1V 3V 5V CURRENT, I CONDITION 2: Table B: V=5V RESISTOR, R 100 250 500, CURRENT, I
Applying Up/Down Thinking

Step: 1. Variables are V, I, and R. 2. In condition 1, as shown in Table A, resistor R is constant and the voltage V changes from 1V to 3V, then to 5V. The current I is unknown and has to be determined. Therefore R and V are the independent variables and I is the dependent variable. In condition 2, as shown in Table B, voltage V is constant and the resistor R changes from 100 to 500 . the current I is still the unknown variable. Therefore, same as in condition 1, R and V are the independent variables and I is the dependent variable. 3. Ohms Law shows the relationship among the three variables found in the given circuit above. This formula is: = 4. By using Ohms Law, we can complete tables A and B: Table A: R=100 VOLTAGE,V 1V 3V 5V CURRENT, I 0.01A 0.03A 0.05A Table B: V=5V RESISTOR, R 100 250 500, CURRENT, I 0.05A 0.02A 0.01A
The table can be expressed as follows: Table A: If R= k, as V ,I ; and as V ,I . ), I also increases ( . ), I decreases ( ); and as R decreases ( ), ); and as V decreases
This means that I R is constant, and V increases ( ( ), I also decreases ( ). Table B: If V = k, as R ,I ; and as R ,I
This means that if V is constant, and R increases ( I increases ( ).
We can now conclude, on that given circuit, that with the resistor held constant, current is directly proportional to the supply voltage; and with the supply voltage held constant, current is inversely proportional to the resistance.
PART 2
2.1 2.2 2.3 2.4 Titles of Experiment and their Objectives Summary List of Required Materials DTL-05 Digital Trainer Functional Features Definition of Terms and Variables Used in the Experimental Circuits
2.1
Titles of Experiment and their Objectives

NUMBER SYSTEM To demonstrate the count sequence of a 4-bit binary. CODE CONVERTER To construct and verify the operation of code converter circuits. DIODES AND TRANSISTORS AS SWITCHES 1. To verify the operation of a diode and transistor as switches. 2. To use the transistor switch as a light emitting diode (LED) driver. 3. To use the transistor switch as a relay driver.
EXPT. NO. 1: OBJECTIVE: EXPT. NO. 2: OBJECTIVE: EXPT. NO. 3: OBJECTIVES:
EXPT. NO. 4: OBJECTIVES:
BASIC LOGIC OPERATIONS AND GATES 1. To verify the logical properties of basic logic operators using discrete diode-transistor logic circuits and Transistor-Transistor Logic (TTL) IC logic gates. 2. To introduce the concepts of duality.
EXCLUSIVE-OR (XOR) GATES 1. To verify the operation of an XOR Gate 2. To use an XOR Gate as a controlled inverter. 3. To demonstrate the use of an XOR Gate in controlling a lamp from two different locations.
DIGITAL IC FAMILIES 1. To determine the basic characteristics of TTL and CMOS ICs. 2. To verify the operation and applications of open collector and threestate gates.
EXPT. NO. 7: OBJECTIVE:
BOOLEAN FUNCTION FORMS To introduce the standard Boolean Function forms, namely: the Standard AND-OR (SAO), also known as sum of Minterm form; Standard AND-ORInvert (SAOI) and Standard OR-AND-Invert (SOAI). SIMPLIFICATION OF BOOLEAN FUNCTIONS To simplify Boolean functions by Karnaugh-mapping. COMBINATIONAL logic circuits To design, construct and test combinational logic circuits using basic gates.
EXPT. NO. 8: OBJECTIVE: EXPT. NO. 9: OBJECTIVE:
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MULTIPLEXER 1. To verify the operation of a multiplexer (MUX). 2. To implement a Boolean function using a MUX Medium Scale Integration (MSI) device. 3. To connect two MUX ICs together to form a digital MUX with a larger number of inputs.
DECODER AND MULTIPLEXER 1. To verify the operation of a decoder and a demultiplexer (deMUX). 2. To connect a decoder/deMUX together to form a larger decoder circuit. 3. To implement a Boolean function using decoder IC and (NAND) gates.
ARITHMETIC CIRCUITS 1. 2. 3. 4. 5. To construct and verify the operation of a half-adder circuit. To construct and verify the operation of a half-subtractor circuit. To construct and verify the operation of a full-adder circuit. To verify the operation of a 4-bit binary full-adder IC-74LS83. To construct and test a 4-bit binary parallel adder-subtractor circuit using two 4-bit binary full adder IC- 74LS83 and one quad two-input XOR IC- 74LS86.
BASIC FLIP-FLOPS To construct, test and investigate the operation of various flip-flop circuits and devices. 8-BIT LATCH To verify the operation of an 8-bit latch using 74LS373. ASYNCHRONOUS OR RIPPLE COUNTERS 1. To construct and test a 4-bit binary ripple counter using flip-flop ICs. 2. To construct and test a Binary-Coded-Decimal (BCD) ripple counter using flip-flop ICs. 3. To construct and test a 4-bit binary ripple counter using 74LS93. 4. To construct and test a BCD ripple counter using 74LS93.
EXPT. NO. 14: OBJECTIVE: EXPT. NO. 15: OBJECTIVES:
SYNCHRONOUS COUNTERS 1. To construct and test binary and BCD synchronous counters using flipflop. 2. To construct and test binary and BCD synchronous counters using 74LS193
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SHIFT REGISTER To verify the different modes of operation of a shift register using a 4-bit universal shift register IC-74LS194. MEMORY DEVICES 1. To verify the behavior of a random access memory (RAM) unit and its storage capability using a 4x4 file register IC (74LS670). 2. To construct and test a read only memory (ROM) circuit using a decoder IC and diodes. 3. To expand the memory location of a RAM device. 4. To use a memory device to implement a Boolean function in combinational logic design.
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2.2
Summary List of Required Materials

1. Digital Trainer (see DTL-05 functional specs. on page)- 1 2. Multitester 1 3. ICs: 74LS07 - 1 74LS83 74LS00 - 3 74LS86 74LS02 - 1 74LS125 74LS04 - 2 74LS138 74LS08 - 1 74LS139 74LS10 - 2 74LS153 74LS20 - 2 74LS192 74LS27 - 3 74LS193 74LS32 - 1 74LS60 74LS47 - 1 74LS73 74LS74 - 1 74LS670 74LS76 - 2 74HC04 4. Transistor: PNP: 9012 - 1 NPN: 9013 - 2 1N4148 - 7 1N4000 - 1
1 1 1 1 1 1 1 1 1 1 2 1
5. Diodes:
6. Resistors (1/4W): 150 - 1 330 - 3 1k - 2 4.7k - 2 10k - 2 100k - 2 7. Trimmer Resistor: 500 - 1 8. LED - 1 9. SPDT Relay, coil source: 6Vdc - 1 10. Set of Breadboarding/ solid wire - 1
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2.3
DTL-05 Digital Trainer Functional Features

+5V DC Regulated Voltage Source Variable Clock Generator with True and Complement Output: CLK 8-bit Data Switches with True and Complement Output: D7, D6, D5, D4, D3, D2, D1, D0 2-bit Control Switches With True And Complement Output: K1, K0 8-bit Two Color LED Logic Indicators: Red Indicator = High Level Green Indicator = Low Level Dual Common Anode 7- Segment Display Breadboard System Male DB-25 Connector Female DB-25 Connector
For details on its specifications and operations, refer to its Users Manual.
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2.4
Definition of Terms and Variables Used in the Experimental Circuits

AC = alternating current BCD = binary coded decimal C = reference variable for capacitor CE = collector-emitter CLK= clock CMOS = complimentary metal oxide semiconductor CPR = cardiopulmonary resuscitation Control Switch = the switch found on DTL-05 that generates the necessary control signal for the experimental circuits. D = reference variable for diode unless otherwise specified Data Switch = refers to the switch found on DTL-05 that generates the necessary digital data for the experimental circuits. D0, D1, D2, D3, D4, D5, D6, D7 = the Data Switches of DTL-05. These are used to provide the necessary digital data to the experimental circuits. DC = direct current deMUX = demultiplexer GND = ground HI= refers to a HIGH level voltage IC = integrated circuit K0, K1 = the Control Switches of DTL-05 used to provide the necessary control signal to the experimental circuits. LED = light emitting diode LO = a LOW level voltage LSTTL = low power schottky transistor-transistor-logic L0, L1, L2, L3, L4, L5, L6, L7 = the Logic Indicators of DTL-05 used to monitor the logic state of digital signals in the experimental circuits. mA = milliampere MUX = multiplexer Q = reference variable for transistor R = reference variable for fixed resistor; used to represent the unit ohm in a circuit diagram (example: 150R means 150-ohms, 1kR means 1k-ohms, 4k7R, means 7.7k ohms). RAM = random access memory RLY = relay ROM = read only memory
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SAO = standard AND-OR SOA = standard OR-AND SOAI = standard OR-AND-Invert SAOI = standard AND-OR-Invert SOP = sum of products SPDT = single-pole-double-throw SD = reference variable for switching signal diode Vcc = supply voltage for TTL (74LSXX) device Vce = collector- emitter voltage VDD = supply voltage for CMOS (74HCXX) device VR = reference variable for variable resistor XOR = exclusive- OR 0 = a LOW level voltage unless otherwise specified 1 = a HIGH level voltage unless otherwise specified P = pico, x 1012 = micro, x10-6 m = milli, x10-3 k = kilo, x103 M = Mega, x106
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PART 3
EXPERIMENTS
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EXPT. NO. 1: NUMBER SYSTEM OBJECTIVE: To demonstrate the count sequence of a 4-bit binary.
SUGGESTED READINGS: Discussion about the different number systems like decimal, binary, octal, hexadecimal, etc. Digital Computer Electronics by Malvino & Brown, pp. 1-15; Digital Design by Mano, pp.4-20. REQUIRED SKILLS: To proceed smoothly, the students must be familiar with the use of DTL-05 or any similar digital trainer. MATERIALS REQUIRED: Description DTL-05 (Digital trainer) ICs: 74LS47 74LS192 74LS193 Resistor: 150- Breadboarding wire WARNING: 1. Do all wiring with power OFF. 2. Make sure you are using the correct power supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to Appendix B for the ICs and other components pin configurations. PROCEDURE: 1. With power switch OFF, connect the 74FS47 IC as shown in circuit of Fig. 1-1. Fig. 1-1: Qty. 1 1 1 1 1 1 set
2.
Turn the power switch ON and set the data switches D3-D0 to sixteen (16) different combinations (1=III. 0=LO) given in Table 1-1. Draw the actual 7-segment display pattern of each of the 16 given combinations under the column 7-segment Display Pattern of Table 1-1.
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3.
Turn OFF the power and connect the circuit shown in Fig. 1-2
Fig. 1-2
4.
Turn the power ON and set the CLK frequency to minimum for easy monitoring of the Count sequence on the Logic Indicators and the 7-segment display. Record the binary count sequence, as it starts from 0000, and its corresponding decimal equivalent in Table 1-2. Turn the power OFF and replace the IC (74LS192) with 74LS193 without changing any connection in the circuit. Turn the power ON and record the binary count sequence, as it stars from 0000, and its corresponding decimal equivalent in Table 1-3.
5.
6.
7.
Table 1-1: Table for step #2
DATA SWITCHES D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
7- SEGMENT DISPLAY PATTERN
DATA SWITCHES D3 D2 D1 D0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
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Table 1-2: for step #5 LOGIC INDICATORS L3 L2 L1 L0 7- SEGMENT DISPLAY PATTERN
LOGIC INDICATORS L3 L2 L1 L0
LOGIC INDICATORS L3 L2 L1 L0
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OBSERVATION AND ANALYSIS:
CONCLUSION:
When you have completed all of the above, have your laboratory instructor sign below:
QUESTIONS: 1. In Fig. 1-1. 1-1. What number system is being represented by the output of the 7-segment display? a) binary b) BCD c) hexadecimal d) none of the above 1-2. What maximum valid number has the 7-segment display for the binary input of 0000 to 1111? Why? 1-3. How do you describe the function of the IC used in the circuit of Fig. 1-1? In Fig. 1-2. 2-1. What count sequence is demonstrated using 74LS192? a)binary b)BCD c) Hexadecimal d) none of the above 2-2. How do you describe the function of this IC? 2-3. What count sequence is demonstrated using 74LS193?
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2.
2-4. 3. 4.
a)binary b)BCD c) Hexadecimal How do you describe the function of 74LS193?
d) none of the above
Convert the binary number 101010110110 to decimal and hexadecimal numbers. In writing a number, the number system being used can be determined by placing a letter, b for binary and d for decimal, right after the rightmost digit. What letter is used to Indicate that the number is octal? hexadecimal? Define the following terms: bit binary byte hex nibble BCD LSB MSB
5.
ANSWERS TO QUESTIONS:
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EXPT. NO. 2: CODE CONVERTER OBJECTIVE: To construct and test code converter circuits.
SUGGESTED READINGS: Topics covering different codes used in digital systems such as BCD, gray code, excess three codes, etc. Digital Computer Electronics by Malvino & Brown, pp. 1-15; Digital Design by Mano, pp. 17-24. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of DTL-05 or any similar digital trainer. MATERIALS REQUIRED: Description Digital trainer ICs: 74LS00 74LS10 74LS47 74LS86 Breadboarding wire WARNING: 1. Do all wiring or any change in wiring with the power OFF unless Otherwise specified in the procedure. 2. Make sure you are using the correct supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to appendix V for the ICs and other components pin configurations. PROCEDURE: Part 1: Gray code-to-Binary converter 1. The logic diagram for Fig. 2-1 is a 3-bit Gray code-to-binary converter circuit. Table 2-1 gives the corresponding output in binary for every gray code input. Verify the conversion from gray code to binary of Fig. 2-1 by completing the columns L2, L1 and L0. Qty. 1 3 2 1 1 1 set
Fig. 2-1: Gray code-to-binary converter
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Table 2-1: Truth table for a Gray code-to-binary converter GRAY C 0 0 0 0 1 1 1 1 B 0 0 1 1 1 1 0 0 A 0 1 1 0 0 1 1 0 X 0 0 0 0 1 1 1 1 BINARY Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 LOGIC INDICATORS L2 L1 L0
Part 2: BCD-to-excess three code converter 2. The diagram of a BCD-to-excess three code converter is given in Fig. 2-2. Verify the code conversion by completing the data on Table 2-2.
Table 2-2: Truth table for BCD-to-excess three code converter
BCD C 0 0 0 0 1 1 1 1 B 0 0 1 1 1 1 0 0 A 0 1 1 0 0 1 1 0
EXCESS THREE X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1
LOGIC INDICATORS L2 L1 L0
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Fig. 2-2: BCD-to-excess three code converter
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CONCLUSION:
QUESTIONS: 1. In the given code of Table 2-1, how many hits in the code group changed from one Number to the next? When using BCD, what is the next higher number to 1001? Represent a decimal 386 in BCD and excess three code. What is the standard 7-bit code used by the computer to represent numbers, letters and Other symbols? With an ACSCII keyboard, each stroke produces the ASCII equivalent of the designated character. Suppose you type GERALD. What is the output of the ASCII keyboard?
2. 3. 4. 5.
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EXPT NO. 3: DIODES AND TRANSISTORS AS SWITCHES OBJECTIVES: 1. To verify the operation of a diode and transistor as switches. 2. To use the transistor switch as a LED driver. 3. To use the transistor switch as a relay driver. SUGGESTED READINGS: Discussion on the basic operation and characteristic of a diode and transistor as switches. Electronic principles by Malvino, pp. 62-65, 158-171, 211-213, 258-263. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of a multitester and the DTL-05 or any similar digital trainer. MATERIALS REQUIRED: Description Digital trainer Multitester 1N4148 Signal diode 1N4000 Rectifier diode 9013 NPN Transistor 9012 PNP Transistor LED Resistors, 1/4W: 330 1k 4.7K 10K Relay, SPDT, coil 6Vdc Breadboarding wire WARNING: Qty. 1 1 1 1 1 1 1 1 1 1 1 1 1 set
1. Do all wiring with the power OFF. 2. Make sure you are using the correct power supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to Appendix B for ICs and other components pin configurations.
PROCEDURE: Part 1: diode as a Switch 1. Construct the circuits shown in Fig. 3-1. Test each circuit and record the results on the space provided.
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Fig. 3-1a:
Fig.c3-1b:
Measured voltage =
Measured voltage =
Part 2: Transistor as a Switch 2. Construct the circuit as shown in Fig. 3-2. Verify the circuit and record the results in Table 3-1.
Fig. 3-2:
Table 3-1: Table for the circuit of Fig. 3-2. DATA SWITCH D0 L0 H1 MEASURED VOLTAGE VBE VCE VOUT
3. Construct the circuit shown in Fig. 3-3. Verify the circuit and record the results in Table 3-2. Fig. 3-3:
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Table 3-2: Table for the circuit of Fig. 3-3. DATA SWITCH D0 L0 H1 4. MEASURED VOLTAGE VBE VCE VOUT
Construct the circuit shown in Fig. 3-4. Verify the circuit and record the results in Table 3-3.
Fig. 3-4:
Table 3-3: Table for the circuit of Fig. 3-4. DATA SWITCH D0 L0 H1 OUTPUT LED (ON/OFF)
VCE
5.
Construct the circuit shown in Fig. 3-5. Verify the circuit and record the results in Table 3-4.
Fig. 3-5:
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Table 3-4: Table for the circuit of Fig. 3-5. DATA SWITCH D0 L0 H1 VCE L0 (H1/L0) OUTPUT L1 (H1/L0) RELAY (ENERGIZED/ DEENERGIZED)
CONCLUSION:
When you have finished all of the above, have your laboratory instructor sign below:
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QUESTIONS: 1. Consider the diode on the circuit of Fig. 3-1a as ideal diode. What should be your measured voltage? Draw the switch equivalent circuit of Fig. 3-1a and 3-1b.
2.
3.
In the circuit of Fig. 3-2, what Data Switch setting causes a maximum flow of collector current? Draw the switch equivalent circuit of the collector-emitter (CE) junction of the transistor in Fig. 3-3 when the Data Switch is set to H1.
4.
5.
The Cut-Off method is one way of testing a saturated transistor in circuit, to determine if it operates normally as a switch by shorting the base-emitter junction. What should be the normal collector-emitter voltage (VCE) reading if we apply the Cut-Off method to the transistor of Fig. 3-2? If we describe the output of the circuit in Fig. 3-4 as active HIGH, how would you describe Its input, active HIGH or active LOW? In the circuit of Fig. 3-4, compute for the amount of current flowing to the LED using your result in Table 3-3. Assume the LED has a voltage drop of 1.7V. Draw the switch equivalent circuit of the transistor in Fig. 3-5 when the relay is energized and deenergized.
6.
7.
8.
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EXPT. NO. 4: BASIC LOGIC OPERATIONS AND GATES OBJECTIVES: 1. 2. To verify the logical properties of basic logic operators using discrete Diode-transistor logic circuits and TTL IC logic gates. To introduce the concepts of duality.
SUGGESTED READINGS: Discussion on the basic operation and characteristics of a diode and transistor as switches, the basic logic functions and gates, and the positive and negative logic. Electronic Principles by Malvino, pp. 62-65, 158-171, 211-213, 258-263, Digital Computer Electronics by Malvino & Brown, pp. 19-36; Digital Design by Mano, pp. 36-68. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of a multitester and the DTL-05 or any similar digital trainer. MATERIALS REQUIRED: Description Digital trainer 1N4148 Signal diode 9013 NPN Transistor ICs: 74LS00 74LS02 74LS04 74LS08 74LS32 74LS08 Resistors: 4.7K 10K Breadboarding wire WARNING: 1. Do all wiring with the power OFF. 2. Make sure you are using the correct power supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to Appendix B for ICs and other components pin configurations. Qty. 1 3 3 3 1 1 1 1 1 2 2 1 set
PROCEDURE: Part 1. Transistor Inverter 1. Construct the circuit as shown in Fig. 4-1. Verify the circuit and record the results in Table 4-1.
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Fig. 4-1:
Table 4-1: Table for the circuit of Fig. 4-1. INPUT DATA D0 L0 H1 OUTPUT INDICATOR L0 POSITIVE LOGIC INPUT A OUTPUT Q NEGATIVE LOGIC INPUT A OUTPUT Q
Part II. Resistor-Transistor Gate 2. Construct the circuit as shown in Fig. 4-2. Verify the circuit and record the results in Table 4-2.
Fig. 4-2:
Table 4-2: Table for the circuit of Fig. 4-2. INPUT DATA D1 D0 L0 L0 L0 H1 H1 L0 H1 H1 OUTPUT INDICATOR L0 POSITIVE LOGIC NEGATIVE LOGIC INPUT OUTPIT INPUT OUTPUT B A Q B A Q
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Part III. Diode Gates 3. Construct the circuit as shown in Fig. 4-3A. Verify the circuit and record the results in Table 4-3A
Fig. 4-3A
Table 4-3A: Table for the circuit of Fig. 4-3A. INPUT DATA D1 D0 L0 L0 L0 H1 H1 L0 H1 H1 OUTPUT INDICATOR L0 POSITIVE LOGIC NEGATIVE LOGIC INPUT OUTPIT INPUT OUTPUT B A Q B A Q
4.
Construct the circuit shown in Fig. 4-3B. verify the circuit and record the results in Table 4-3B.
Fig. 4-3B:
Table 4-3B: Table for the circuit of Fig. 4-3B. INPUT DATA D1 D0 L0 L0 L0 H1 H1 L0 H1 H1 OUTPUT INDICATOR L0 POSITIVE LOGIC NEGATIVE LOGIC INPUT OUTPIT INPUT OUTPUT B A Q B A Q
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Part IV. Diode-Transistor Logic Gate 1. Construct a circuit as shown in Fig. 4-4. Verify the circuit and record the result in Table 4-4.
Fig. 4-4:
Table 4-4: Table for the circuit of Fig. 4-4: INPUT DATA D1 D0 LO LO LO HI HI LO HI HI OUTPUT INDICATOR LO POSITIVE LOGIC INPUT OUTPUT B A Q NEGATIVE LOGIC INPUT OUTPUT B A Q
2. Open the circuit effects: For the circuit shown in Fig. 4-4, set input B to HI and record the effects of the following on the output: Q (input A= HI) =____________________ Q (input A= LO) =____________________ Q (input A= open circuit) =____________________
Part V. IC Logic Gates 1. Use one gate from each IC listed above and obtain the truth table of the gate using the positive and negative logic. Refer to appendix B for pin configuration of each IC. Never reverse the polarity of the supply voltage. 2. Open circuit effects: for the 74LS00 IC, set one input pin of the gate open and record the effects of the following on the output: OUTPUT (other input = HI) = _______________ OUTPUT (other input = LO) = _______________ OUTPUT (other input = open circuit) = _______________
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OBSERVATION AND ANALYSIS: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
When you have completed the entire above, have your laboratory instructor sign below:
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QUESTIONS: 1. What will be the resulting logic operations if we connect the output of the circuit in fig.4-2 to the input of the circuit in figure 4-1? Show the truth table of the combined circuits. 2. Draw the equivalent circuit of a NOR gate using diode-transistor logic. 3. When you need only one gate, which is more economical to use, discrete devices or ICs? 4. What will be the resulting output of a 74LS32 gate if you apply power to the IC without applying any signal to its input? 5. Using one 74LS00 IC, draw the circuit that can perform the logic operation of a two-input OR-gate. 6. What is a universal gate? Give two examples.
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EXPT. NO.5: EXCLUSIVE-OR (XOR) GATES OBJECTIVES: 1. To verify the operation of an XOR Gates. 2. To use an XOR Gate as a controlled inverter 3. To demonstrate the use of an XOR Gate in controlling a lamp from two different locations. SUGGESTED READINGS: Discussion about XOR Gate, Digital Computer Electronics by Malvino & Brown, pp.37-43; Digital Design by Mano, pp. 59, 142-148. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of DTL05 or any similar digital trainer. MATERIALS REQUIRED: Description Digital trainer IC: 74LS86 LED Resistors: 330 10K Transistor: 9013 Bread boarding wire WARNING: 1. Do all with power OFF. 2. Make sure you are using the correct power supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to appendix B for the ICs and other components pin configurations. Qty. 1 1 1 1 1 1 1 set
PROCEDURE: Part 1. XOR Basic Operation 1. With power switch OFF, construct the circuit as shown in Fig, 5-1. Fig. 5-1:
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2. Turn the power ON and verify the circuit operation. Record the result in Table 5-1. Table 5-1: Table for Step #2. DATA SWITCHES D1 LO LO HI HI D0 LO HI LO HI OUTPUT L0
3. From the result recorded in Table 5-1, derive the Boolean equation of the circuit of Fig. 5-1. 4. Turn the power off and construct the circuit as shown in Fig. 5-2. Fig. 5-2:
5. Turn the power switch ON, verify the circuit operation and record the results in Table 5-2. 6. Construct the circuit as shown in Fig. 5-3. Verify the circuit operation and record the results in Table 5-3. Fig. 5-3:
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Table 5.2: Table for step #5 CONTROL SWITCH K0 LO HI LO HI LO HI LO HI LO HI LO HI LO HI LO HI LO HI LO HI LO HI LO HI LO HI LO HI LO HI LO HI DATE SWITCHES D3 LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO HI HI HI HI HI HI HI HI HI HI HI HI HI HI HI HI D2 LO LO LO LO LO LO LO LO HI HI HI HI HI HI HI HI LO LO LO LO LO LO LO LO HI HI HI HI HI HI HI HI D1 LO LO LO LO HI HI HI HI LO LO LO LO HI HI HI HI LO LO LO LO HI HI HI HI LO LO LO LO HI HI HI HI D0 LO LO HI HI LO LO HI HI LO LO HI HI LO LO HI HI LO LO HI HI LO LO HI HI LO LO HI HI LO LO HI HI

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LOGIC INDICATORS 1.3 1.2 1.1 1.0
Table 5-3: Table for Step #6 DATA SWITCHES D1 D0 LO LO LO HI HI LO HI HI OUTPUT (ON/OFF)
OBSERVATION AND ANALYSIS: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
____________________________________
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QUESTIONS: 1. 2. 3. 4. 5. Draw the equivalent logic circuit of Fig. 5-1 using AND & OR Gates. Assume that the complements of D0 & D1 are available. In Fig. 5-2, what is the function of K0? Modify the circuit of fig. 5-3 to control the LED (ON/OFF) by the three digital data D0, D1 & D2. What electromechanical device can be added to the circuit of fig. 5-3 to practically control the ON & OFF of a 220-Vac incandescent bulb two different locations? Give two other applications of the XOR-gate.
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EXPT. NO.6: DIGITAL IC FAMILIES OBJECTIVES: 1. To determine by experiment the basic characteristics of TTL and CMOS ICs. 2. To verify the operation and applications of open collector and threestate gates. SUGGESTED READINGS: Discussions on digital ICs fan-in/fan-out, noise margin. Valid HIGH and LOW voltage level, propagation delay, and other electrical ratings found on a device data sheet. Digital Computer Electronics by Malvino & Brown, pp.48-58; Digital Design by Mano, pp.62-67. REQUIRES SKILLS: To proceed smoothly, the student must be familiar with the used of the digital trainer and be able to understand a device databook. MATERIALS REQUIRED: Description Digital tester Multitester ICs: 74LS04 74LS125 74LS07 74HC04 Resistors, W: 4.7K 47K Trimmer resistor: 500 Ceramic capacitor 20pF Bread boarding wire
Qty. 1 1 2 1 1 1 1 2 1 2 1 set
WARNING: 1. Do all writing or any change in writing with the power OFF unless otherwise specified in the procedure. 2. Make sure you are using the correct supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent the damage to the IC. Refer to Appendix B for the ICs and the other components pin configuration. PROCEDURE: Part 1 Noise Margin 1. Construct the circuit as shown in Fig. 6-1. 2. Adjusting the trimmer resistor VR, set VI to 2.0V and record the measured output voltage V2 under the column of Table 6-1. Set VI to 0.8V and record the measured output voltage V2 under the column of of the table 6-1.
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Fig. 6-1:
Table 6-1: Table for step #2 VI 2.0 V xxx xxx 0.8V xxx V2 Xxx
3. Using the given and and recorded the and of the table- 6-1, determine the high level and low-level noise margin of a circuit when the output of an LSTTL device is used to drive another LSTTL device. Refer to Fig.6-2 in determining the noise margin of a circuit and write your answers on the spaces provided below. Fig. 6-2: Signals for evaluating noise margin.
Noise margin for LSTTL to LSTTL logic: Low-level noise margin: = ____________ High-level noise margin: = ____________
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4. Replace the 74LS04-TTL inverter gate of Fig. 6-1 with a 74HC04-CMOS inverter gate and determine the noise margin for CMOS to CMOS logic using using the same steps used on LSTTL logic. However, refer to table 6-2 for the setting of VI and recoer the responsive measured voltage under and of column V2. Table 6-2: table foe step #4 VI xxx 70% xxx 30% V2 xxx
Xxx
Note: refers to the supply voltage of a CMOS device. Noise Margin for CMOS to CMOS logic: Low-level noise margin: = ____________ High-level noise margin: = ____________ Part 2: Fan-in/Fan-out 5. Refer to the data sheets of the 74LS04 TTL-inverter and the 74HC04 CMOS-inverter (or appendix C) and complete Table 6-3. Table 6-3: Table foe step 5 Driving device 74LS04 74HC04 Parameter (mA) (A) (mA) (A) Number of loads given 74LSXX 74HCXX
Part 3: OPEN COLLECTOR GATES 6. Construct the circuit as shown in Fig. 6-3. Fig. 6-3:
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7. Set D0 specified below and record the output voltage for each setting. D0= LO : Vo = ___________________ D0= HI : Vo = ___________________ 8. Add a 1-k-ohm resistor between the =5V terminal and the output terminal of the gate in Fig.6-3. Set D0 as specified below and record the output voltage for each setting. D0= LO : Vo = ___________________ D0= HI : Vo = ___________________ 9. Construct the circuit as shown in Fig. 6-4. Fig. 6-4:
10. Using positive logic, derive the truth table and the logic function of the circuit in Fig. 6-4. Use Table. 6-4. Table. 6-4.: Table for step #10. OUTPUT L0
INPUT D1 D0 LO LO LO HI HI LO HI HI
Part 4: Three-State Gates 11. Construct the circuit as shown in Fig.6-5. Verify the circuit operation and complete Table 6-5. Fig. 6-5:
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Table 6.5: Table for step #11 INPUT ENABLE DATA (K0) (D0) LO LO LO HI HI LO HI HI OUTPUT L0
Part 5: Propagation Delay (optional) 12. Construct the circuit as shown in Fig. 6-6. Fig. 6-6.
13. Set the oscilloscope to dual mode and adjust the volts/div. and time/div. setting for proper display of the input and output waveforms. 14. Determine the total propagation delay from the input of the first inverter to the output of the sixth inverter during the upswing ( And again during the downswing of the pulse.
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15. Compute the propagation delay of each gate using the formula below.
per gate = per gate =
per gate = _________________ per gate = _________________
OBSERVATION AND ANALYSIS: ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________
CONCLUSION: ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________
When you have completed all of the above, have your laboratory instructor sign below.
_________________________________________
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QUESTIONS: 1. What is a noise margin? 2. What will be the noise margin of the circuit if the 74LS20 is taking its inut signal from a device which has a HIGH output voltage of 4.V and a LOW output voltage of 0.2V? 3. Can we use the 74LS04 as a driver to LED indicator with the current through the LED limited to 10 mA? Why? 4. How many 74LS10 inputs can be connected to a 7400 output? 5. Can we connect directly connect the output of TTL logic device to the input of a CMOS device provided they are both using +5V supply? Why? 6. What type of TTL device is usully used as an interface between a TTL logic IC and a CMOS logic IC? 7. What are the states that a three-state gate exhibits? 8. How many standard TTL inverter gates should be connected to produce a delay of 0.242 microseconds?
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EXPT NO. 7: BOOLEAN FUNCTION FORMS OBJECTIVE: To introduce the four standard Boolean function forms, namely: sum of minterm (SAO) product of maxterm (SOA), Standard-AND-OR-invert (SAOI), and Standard OR-AND-LNVERT (SOAI). SUGGESTED READINGS: Canonical and standard Boolean expressions, duality theorem, and Boolean minimization. Digital Computer Electronics by malvino & Brown, pp.23-25, 33-36, 64-70; Digital Design by Mano, pp. 49-58, 67-68, 88-98. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use DTL-05 or any similar digital trainer.
Materials required: Description digital trainer IC: 74LS10 74LS27 74LS260 Breadboarding wire Qty. 1 2 3 1 1 set
WARNING: 1. Do all wiring or any change in wiring with the power OFF unless otherwise specified in the procedure. 2. Make sure you are using the correct supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to Appendix B for the ICs and other components pin configurations.
PROCEDURE: 1. Convert the function F=AC + AB to a standard truth table (column F) as given in Table 7-1.
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Table 7-1: Boolean Functions Forms INPUT C 1 2 3 4 5 6 7 B A F SAO OUTPUT SOA SOAI
2.Write the F in the Boolean function form given below and draw the logic diagram using the basic gates on the space provided below: A. F(SAO)
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B. F(SAOI)
C. F(SOA)
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D. (SOAI):
3. Verify the circuit implementation for each form in step #2 by completing the data in Table 7-1. 4. Draw the circuit implementation of function F in the SAO form using the available NAND gates IC (see materials required) only. Assume that all the complements are available.
5. Construct the circuit implementation of step #4 and test if it allows the data under column SAO of Table 7-1. 6. Draw the circuit implementation of function F in the SAOI from using the available NOR gates IC (see materials required. Assume that all the complements are available.
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7. Construct the circuit implementation of step #4 and test if it follows the data under column SOAI of Table 7-1.
OBSERVATION AND ANALYSIS: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
______________________________
QUESTIONS: 1.] Express the function given in step #1 in a. sum of minterm notation b. product of maxterm notation How do you call the logical product of variables and complements that produces a high output for a given input condition?
2.]
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3.]
A majority function is generated in a combinatorial logic circuit when the output is equal to 1 of the input variables have more 1s than 0s. The output is 0 otherwise. Design a three-input majority function by following the steps and conditions given below: 1. Derive the truth table. 2. Express the function in the SAO form. 3. Implement the function using only NAND gates. Assume that all the complements are available.
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EXPT. NO 8: SIMPLIFICATION OF BOOLEAN FUNCTIONS OBJECTIVE: To simplify Boolean functions by Karnaugh-mapping (K-mapping). SUGGESTED READINGS: Boolean Minimization using K-mapping techniques up to four variable functions. Digital Computer Electronics by Malvino & Brown, pp. 70-77; Digital Design by Mano, pp 72-82. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of DTL-05 or any similar digital trainer. MATERIALS REQUIRED: Description Digital trainer ICs: 74LS00 74LS10 74LS20 Breadboarding wire WARNING: 1. Do all wiring or any change in wiring with the power OFF unless otherwise specified in the procedure. 2. Make sure you are using the correct supply voltage specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to appendix B for the ICs and other components pin configurations. PROCEDURE: Part 1: Logic Diagram Implementation 1. Obtain the truth table of the circuit shown in Fig. 8-1 by completing column F1 of Table 8-1. Qty. 1 2 1 1 1 set
Table 8-1: X 0 0 0 0 1 1 1 1 INPUT Y Z 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 OUTPUT F1 L0
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Fig. 8-1: Logic Diagram to be simplified.
2.
Obtain the Boolean function, F1, in sum of minterm form. Write your answer on the space provided below. F1(X, Y, Z) = (__________)
3.
Simplify the obtained Boolean function, F1, from step #2 by K-mapping. In the sum of products (SOP) form, write the simplified expression of F1, as F2 on the space provided below. F2(X, Y, Z) = ______________________
4.
Assuming that the complement of each variable (X,Y,Z) is not available; implement the simplified expression of step #3 using a single 74LS00-QUAD 2-input NAND gate IC. Draw your circuit implementation on the space provided below. Circuit implementation of Boolean function F1 using a single 74Ls00-Quad 2-input NAND gate IC.
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5.
Construct your circuit implementation by connecting the inputs X, Y and Z to Data Switches D2, D1 and D0 respectively, and the output F2 to the Logic Indicator L0 as illustrated in the block diagram of Fig 8-2. Test the circuit and record the results by completing the column L0 of Table 8-1.
6.
Fig. 8-2: Block diagram showing where the inputs and output should be connected.
Part 2: Boolean Functions 7. Simplify the two Boolean functions given below by K-mapping. Write the simplified functions in SOP form on the space provided below. F1(K, L, M, N) = (0,1,4,5,9,11,13,15) simplified SOP form of F1(K,L,M,N) = ________________________________ F2(K, L, M, N) = KLN + KLM + LN + KLN + KLM simplified SOP form of F2(K,L,M,N) = ________________________________ 8. Using a minimum number of NAND gates, draw the logic implementation of the simplified expressions of functions F1 &F2, from step #7, on the space provided below. Assume that the complement of each variable (K,L,M,N) is not available. Circuit implementation of the simplified F1 & F2 using a minimum number of NAND gates.
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9.
Construct and test your simplified circuit from step#8 by connecting the inputs K,L,M,N to Data Switches D3,D2,D1.D0 and the outputs F1, F2 to Logic Indicators L1, L0, respectively. Record the results in Table 8-2.
Table 8-2: INPUT K L M N (D3) (D2) (D1) (D0) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 OUTPUT F2 F1 (L1) (L0)
where 0 = LO, and 1 = HI
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CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
_______________________________
QUESTIONS: 1. 2. What does each square on a Karnaugh map represent? Describe the following: a. pair b. quad c. octet Write a procedure on how to use the Karnaugh map to simplify logic circuits. Simplify the following functions by using the Karnaugh map: a. S= BD + BCD + ABCD b. Y(ABCD) = sum of minterms (0,2,5,7,10,13)
3. 4.
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EXPT. NO 9: COMBINATIONAL LOGIC CIRCUITS OBJECTIVE: To design, construct and test combinational logic circuits using basic gates. SUGGESTED READINGS: Basic logic gates and Boolean function simplification, combinatorial logic circuits. Digital Computer Electronics by Malvino & Brown, pp. 64-75; Digital Design by Mano, pp 72-110 or 72,110-148. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of DTL-05 or any similar digital trainer. MATERIALS REQUIRED: Description Digital trainer ICs: 74LS00 74LS10 74LS20 74LS86 Breadboarding wire WARNING: 1. Do all wiring or any change in wiring with the power OFF unless otherwise specified in the procedure. 2. Make sure you are using the correct supply of voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to appendix B for the IC and other components pin configurations. PROCEDURE: Step-by-Step Design Procedure for the Combinatorial Circuits 1. Go over the Step-by-Step Design Procedure stated below and apply it to design the three combinatorial circuits described in the given problems. A. B. C. D. Obtain the truth table of the circuit. Simplify the output function. Draw the circuit diagram using a minimum number of NAND gates. Construct the circuit and test it for proper operation by verifying the input/output relationship. Qty. 1 2 2 2 1 1 set
2.
After testing and verification of your designed combinatorial logic circuit, have your laboratory instructor check it.
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PROBLEMS: Design Problem #1: Design a combinatorial circuit with four inputs A,B,C and D and one output, F. F is equal to logic 1 when A = 1, provided that B = 0, or when B = 1 provided that either C or D is also equal to 1. Otherwise, the output is equal to 0. Answer to Design Problem #1:
Design Problem #2: A majority logic is a digital circuit whose output is equal to logic 1 if the majority inputs are 1s. The output is 0 otherwise. Design and test a three-input majority circuit using NAND gates with a minimum number of ICs. Answer to Design Problem #2:
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Design Problem # 3: Design, construct and test a circuit that penetrates an even parity bit from four-message bits. Use gates. Answer to Design Problem # 3:
OBSERVATION AND ANALYSIS: _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________
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CONCLUSION: _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________
_________________________________
QUESTIONS: 1. 2. Describe a combinatorial logic circuit. Why do we always use the NAND gates in most combinatorial logic circuits?
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EXPT. NO 10: MULTIPLEXER OBJECTIVE: 1. To verify the operation of a multiplexer (MUX). 2. To implement a Boolean function using an MUX (MSI) device. 3. To connect two MUX ICs together to form a digital MUX with a larger number of inputs. SUGGESTED READINGS: Discussions on multiplexers operation and applications. Digital Computer Electronics by Malvino & Brown, pp. 58-60; Digital Design by Mano, pp 72-110 or 72,110-148. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of DTL-05 or any similar digital trainer. MATERIALS REQUIRED: Description Digital trainer ICs: 74LS00 74LS32 74LS153 Breadboarding wire Qty. 1 1 1 1 1 set
WARNING: 1. Do all wiring or any change in wiring with the power OFF unless otherwise specified in the procedure. 2. Make sure you are using the correct supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to appendix B for the ICs and other components pin configurations.
PROCEDURE: Part 1: Multiplexer Operation 1. 74LS153 IC is a dual 4-line to 1-line multiplexer. Verify its operation by constructing the circuit shown in Fig. 10-1 and record the results by completing column L0 of Table 10-1.
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Fig. 10-1: 4-line to 1-line multiplexer experiment circuit
Table 10-1: Truth table of a 4-line to 1-line multiplexer SELECT LINES ENABLE INPUT DATA S1 S0 C3 C2 C1 E (K1) (K0) (D3) (D2) (D1) x x 1 x x x 0 0 0 x x x 0 0 0 x x x 0 1 0 x x 0 0 1 0 x x 1 1 0 0 x 0 x 1 0 0 x 1 x 1 1 0 0 x x 1 1 0 1 x x Note: x means dont care HI-Z means high impedance Part 2: Multiplexer as a Universal Logic Circuit
C0 (D0) x 0 1 x x x x x x
OUTPUT DATA LOGIC INDICATOR Y LO HI-Z 0 1 0 1 0 1 0 1
2.
For a given function F, F = AB + AB, implement the logic circuit using the two different circuits shown in Fig. 10-2a and Table 10-2b. Verify that the circuits produce the same output. Record the results in table 10-2a and Table 10-2b.
Fig. 10-2a: Logic circuit implementation of the given Function F of step #2 using discrete NAND gates only.
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Fig. 10-2b: Logic circuit implementation of the given Function F of step #2 using discrete a 74LS153 multiplexer IC.
Table 10-2a: Table for step #2, logic circuit implementation using NAND gates INPUT B (D1) 0 0 1 1 A (D0) 0 1 0 1 OUTPUT LO
Table 10-2b: Table for step #2, logic circuit implementation using NAND gates INPUT B (D1) 0 0 1 1 A (D0) 0 1 0 1 OUTPUT LO
Part 3: Multiplexer Expansion The block diagram of Fig, 10-3 shows the expansion of 2 four-line to 1-line multiplexers to an 8-line to 1-line multiplexer. Realize the given block diagram by constructing the circuit shown in Fig. 10-4. Verify the circuit operation by completing the data on Table 10-3.
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Fig. 10-3: Block diagram for MUX expansion.
Fig. 10-4: Experimental circuit for MUX expansion.
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Table 10-1: Truth table of a 4-line to 1-line multiplexer SELECT LINES K2 K1 K0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 INPUT DATA D4 D3 D2 x x x x x x x x x x x x x x 0 x x 1 x 0 x x 1 x 0 x x 1 x x x x x x x x x x x x x x x x x x x x OUTPUT L0
D7 x x x x x x x x x x x x x x 0 1
D6 x x x x x x x x x x x x 0 1 x x
D5 x x x x x x x x x x 0 1 x x x x
D1 x x 0 1 x x x x x x x x x x x x
D0 0 1 x x x x x x x x x x x x x x
Note: For the select line K2, 1 = +5V and 0 = GND.
OBSERVATION AND ANALYSIS: _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________
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CONCLUSION: _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________ _________________________________________________________________________
_________________________________
QUESTIONS: 1. 2. 3. Describe a digital multiplexer. What is another term for MUX?? An 8-line to 1-line MUX has inputs A, B and C connected to the select inputs S2, S1 and S0, respectively. The data inputs, I0 and I7 are as follows: I1 = I2 = I7 = 0; I3 = I5 = 1; and I6 = D. Determine the Boolean function that the MUX implements. A 74LS152 is an 8-line to 1-line MUX. However, it cannot be used to produce an MUX with 16 input lines. Why? Draw the circuit showing hot two 72LS151 (8-input MUX) ICs can be connected to produce a 16-input MUX.
4.
5.
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EXPT. NO 10: DECODER AND DEMULTIPLEXER OBJECTIVE: 1. To verify the operation of a decoder and a demultiplexer (deMUX). 2. To connect a decoder and a deMUX together to form a larger decoder circuit 3. To implement a Boolean function using a deMUX MSI device and NAND gates. SUGGESTED READINGS: Topics about the basic operation and applications of MSI devices such as decoder and demultiplexer. Digital Design by Mano, pp 166-170. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of digital trainer and be able to read and interpret a device data sheet. MATERIALS REQUIRED: Description Digital trainer ICs: 74LS00 74LS139 74LS86 Breadboarding wire Qty. 1 1 1 1 1 set
WARNING: 1. Do all wiring with power OFF. 2. Make sure you are using the correct supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to appendix B for the ICs and other components pin configurations.
PROCEDURE: Part 1: Decoder/Demultiplexer Operation 1. Construct the circuit as shown in Fig. 11-1. Verify the circuit operation and record the results in Table 11-1. Fig. 11-1:
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Table 11-1: Truth Table of a decoder with enable input (step #1) INPUT ENABLE K0 0 0 0 0 1 1 1 1 SELECT LINES D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 OUTPUT LOGIC INDICATORS L3 L2 L1 L0
2. Construct the circuit as shown in Fig. 11-2. Verify the circuit operation and record the results in Table 11-2. Fig. 11-2: Experimental circuit for decoder/de MUX operation
Table 11-2: Truth table of demultiplexer (Step #2) INPUT SELECT LINES K1 0 0 0 0 1 1 1 1 K0 0 0 1 1 0 0 1 1 DATA D1 0 1 0 1 0 1 0 1 OUTPUT LOGIC INDICATORS L3 L2 L1 L0
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Part 2: Decoder Expansion 3. Construct a 3-o-8 line decoder using two 2-to-4 line decoders of the 74LS139 as shown in Fig. 11-3. Test the validity of the given circuit and record the results in Table 11-3. Fig. 11-2: Decoder Expansion
Table 11-3: Truth table of demultiplexer (Step #2) INPUT ENABLE K0 0 0 0 0 1 1 1 1 SELECT LINES D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 L3 L2 OUTPUT LOGIC INDICATORS
L1
L0
L0
L0
L0
L0
Part 3: Implementation of Boolean Function using a Decoder 4. For the given function F = AB + AB, construct and test each logic implementation given in Fig. 11-4a, -4b and -4c. Record the results by completing Table 11-4.
Fig. 11-4a:
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CONCLUSION: ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________
When you have completed all of the above, have your laboratory instructor sign below. ________________________ QUESTIONS: 1. Describe a digital multiplexer. 2. What is another term for MUX? 3. An 8-line to 1-line MUX has inputs A, B and C connected to the select inputs S2, S1 and S0 respectively. The data inputs, I0 trough I7 are as follows: I1 = I2 = I7 = 0; I3 = I5 = 1; I6 = D. Determine the Boolean function that the MUX implements. 4. A 74LS152 is an 8-line to 1-line MUX. However, it cannot be used to produce an MUX with 16 input lines. Why? 5. Draw the circuit showing how to 74LS151 (8-line MUX) ICs can be connected to produce a 16-input MUX.
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EXPT. NO. 11: DECODER AND DEMULTIPLEXER OBJECTIVES: 1. To verify the operation of a decoder and a demultiplexer (deMUX). 2. To connect a decoder and a deMUX together to form a larger decoder circuit. 3. To implement a Boolean function using deMUX MSI device and NAND gates. SUGGESTED READINGS: Topics about the basic operation and applications of MSI devices such as decoder and demultiplexer. Digital Design by Mano, pp. 166-170. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of a digital trainer and be able to read and interpret a device datasheet. MATERIALS REQUIRED: Description Digital Trainer ICs: 74LS00 74LS139 74LS86 Breadboarding Wire Qty. 1 1 1 1 1 set
WARNING: 1. Do all wiring with power off. 2. Make sure you are using the correct supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage on the IC, Refer to Appendix B for the ICs and other components pin configuration.
PROCEDURE: Part 1: Decoder/Demultiplexer Operation 1. Construct the circuit as shown in the Fig. 11-1. Verify the circuit operation and record the results of Table 11-1.
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Fig, 11-1:
OUTPUTS SELECT LINES LOGIC INDICATORS
ENABLE
Table 11-1: Truth table of a decoder with enable input (step #1) INPUT ENABLE SELECT LINES K0 D1 D0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 OUTPUT LOGIC INDICATORS L3 L2 L1 L0
2. Contract the circuit as shown in Fig. 11-2. Verify the circuit operation and record the results in Table 11-2. Fig. 11-2: Experimental circuit for decoder/deMUX operation
OUTPUTS SELECT LINES LOGIC INDICATORS ENABLE
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Table 11-2: Truth table of demultiplexer (Step #2) INPUT SELECT DATA LINES K1 K0 D1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 OUTPUT LOGIC INDICATORS L3 L2 L1 L0
Part 2: Decoder Expansion 3. Construct a 3-to-8 line decoder using two 2-to-4 line decoder of the 74LS139 as shown in Fig. 11-3. Test the validity of the given circuit and record the results in Table 11-3. Fig. 11-3:
OUTPUTS LOGIC INDICATORS
SELECT LINES
LOGIC INDICATORS
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Table 11-3: Truth Table of a 3-to-8 line decoder (step #3) INPUT SELECT LINES K0 D1 D0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 OUTPUT LOGIC INDICATORS L3 L2 L1 L0 L0 L0 L0 L0
Part 3: Implementation of Boolean Function using a Decoder 4. For the given function F = AB + AB, construct and test each logic implementation given in Fig. 11-4a, -4b and -4c. Record the results by completing Table 11-4. Fig. 11-4a:
INPUT DATA
OUTPUT LOGIC INDICATOR
Fig. 11-4b:
INPUT DATA OUTPUT LOGIC INDICATOR
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Fig. 11-4c:
INPUT DATA OUTPUT LOGIC INDICATOR
Table 11-4: Truth table for the function F (step #4) INPUT B D1 0 0 1 1 A D0 0 1 0 1 F OUTPUT LOGIC INDICATORS L0 LO LO
OBSERVATION AND ANALYSIS: ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________
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CONCLUSION: ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________
When you have completed all of the above, have your laboratory instructor sign below. ________________________
QUESTIONS: 1. What is the difference between a decoder and a demultiplexer? 2. A 74LS138 is a 3-to-8 line decoder demultiplexer IC. Use two 74LS138s to produce a 4to-16 line decoder. 3. Write a step-by-step procedure on how to implement a Boolean function using a decoder and NAND gates. 4. A combinational circuit is defined by the following two Boolean functions. Design the circuit with a 74LS138 and NAND gates. F1 = XYZ + XZ F2 = XYZ + XY F3 = XYZ + XY
ANSWERS TO QUESTION:
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EXPT. NO. 12: ARITHMETIC CIRCUITS OBJECTIVES: 1. To construct and verify the operation of a half-adder circuit. 2. To construct and verify the operation of a half-subtractor circuit. 3. To construct and verify the operation of a full-adder circuit. 4. To verify the operation of a 4-bit binary full-adder IC 74LS83. 5. To construct and test a 4-bit binary parallel adder-subtractor circuit using one 74LS83 and one 74LS86. SUGGESTED READINGS: Topics covering half-adder, full-adder, parallel-adder, adder/subtartor. Digital Computer Electronics by Malvino & Brown, pp. 7989; Digital Design by Mano, pp. 116-123, 154-163. REQUIRED SKILLS: To proceed smoothly, the students must be familiar, with the use of DTL-05 or any similar digital trainer, and be able to read and interpret the TTL databook. MATERIALS REQUIRED: Description Digital trainer ICs: 74LS08 74LS86 74LS83 Breadboarding wire Qty. 1 1 1 1 1 set
WARNING: 1. Do all wiring or any change in wiring with power OFF unless otherwise specified in the procedure. 2. Make sure you are using the correct supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage on the IC. Refer to appendix B for the ICs pin configuration.
PROCEDURE: Part 1: Half-adder 1. Construct the half-adder circuit in Fig. 12-1. Test the logical operation by completing the date in Table 12.1.
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Fig. 12-1 Logic Diagram of a half-adder circuit

INPUT DATA OUTPUTS
Table 12-1: Truth table for a half-adder circuit INPUT D1 0 0 1 1 D0 0 1 0 1 OUTPUT CARRY SUM (L1) (L0)
Part2: Half-subtractor 2. Construct the half-subtractor of Fig. 12-2. Test the logical operation by completing the data in Table 12-2. Fig. 12-2: Logic diagram of a half-subtractor circuit
INPUT DATA OUTPUTS MINUEND SUBTRAHEND
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Table 12-2: Truth table for a half-subtractor circuit INPUT OUTPUT A B BORROW DIFFERENCE (D1) (D0) (L1) (L0) 0 0 0 1 1 0 1 1
Part 3: Full-adder 3. Construct the full-adder of Fig. 12-3. Test its logical operation by completing the data in Table 12-3. Fig. 12-3: Logic diagram of a full-adder circuit
Table 12-3: Truth table for a full-adder circuit INPUT D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 OUTPUT CARRY SUM (L1) (L0)
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Part 4: 4-Bit Parallel Adder 4. Construct the logic diagram of Fig. 12-4. Test its arithmetic operation by completing the data in Table 12-4. Fig. 12-4: 4-bit parallel adder using a 74LS83 MSI device
DATA GROUP A
DATA GROUP B CARRY - IN
Table 12-4: 4-bit parallel adder using a 74LS83

INPUT OUTPUT DATA GROUP B DATA GROUP A CARRY-OUT SUM D7 D6 D5 D4 D3 D2 D1 D0 L4 L3 L2 L1 L0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
CARRY IN K0 0 0 0 1 1
Part 5: 4-Bit Binary Adder and Subtractor using 74LS83 MSI 5. Construct the logic diagram of Fig. 12-5. Verify its arithmetic operation by performing the following operations in binary. Record the results by completing the data in Table 12-5. 9 + 5, 9 + 9, 9 + 15, 95 99 9 15
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Fig. 12-5: Binary adder and subtractor using 74LS83 and 74LS86 ICs
DATA GROUP A
SUM / DIFFERENCE
CARRY / BORROW
DATA GROUP B
ADD / SUBTRACT
Table 12-5: Simple arithmetic operation using 74LS83 Add/Subtract K0 0 0 0 1 1 1 ARTIHMETIC OPERATION (A B) 9+5 9+9 9+15 9-5 9-9 9-15 OUTPUT Carry/Borrow Sum/Difference L4 L3 L2 L1 L0
OBSERVATION AND ANALYSIS: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
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CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
QUESTIONS: 1. 2. 3. 4. What is the main difference between a half-adder and a full-adder? Is the logic circuit that adds 4-bits a full-adder? What is the function of the XOR gates in the circuit of Fig. 12-5? What method does the circuit of Fig. 12-5 apply to subtract binary numbers?
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EXPT. NO. 13: BASIC FLIP-FLOPS OBLECTIVES: To construct and investigate the operation of various flip-flop circuits and devices. SUGGESTED READINGS: Introduction to sequential circuits, basic memory cell, types of flip-flop, triggering of flip-flops, IC flip-flops. Digital Computer Electronics by Malvino & Brown, pp. 90-102, Digital Design by Mano, pp. 202-218. REQUIRED SKILLS: To proceed smoothly, the students must be familiar with the use of DTL-05 or any similar digital trainer, and be able to read and interpret the TTL databook. MATERIALS REQUIRED: Description Digital Trainer ICs: 74LS00 74LS02 74LS04 74LS10 74LS74 74LS76 Resistors: 1k Breadbording wire Qty. 1 1 1 1 1 1 1 2 1 set
WARNING: 1. Do all wiring or any change in wiring with power OFF unless otherwise specified in the procedure. 2. Make sure you are using the correct supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage on the IC. Refer to appendix B for the ICs pin configuration.
PROCEDURES: Part 1: NAND RS Latch 1. Construct the NAND RS Latch of Fig. 13-1.
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Verify the logical property of the NAND RS Latch by completing the data in Table 13-1.
Fig. 13-1: NAND RS Latch
Table 13-1: Truth table for NAND RS Latch INPUT S 1 0 1 0 R 1 1 0 0 OUTPUT Q Q (L0) (L1)
Part 2: NOR RS Latch 2. Construct the NOR RS latch of Fig. 13-2 and verify its logical property by completing the data in Table 13-2. Fig. 13-2: NOR RS Latch
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Table 13-2: Truth Table for NOR RS Latch INPUT S 1 0 1 0 R 1 1 0 0 OUTPUT Q Q (L0) (L1)
Part 3: Clocked RS Flip-Flop 3. Construct the logic diagram of Fig. 13-3. Verify its logical property by completing the data in Table 13-3. Take note of the effect of CLOCK on the output. Fig. 13-3: Clocked RS Flip-Flop
CLOCK
Table 13-3: Truth table of a clocked RS Flip-Flop INPUT S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 CLOCK 0 1 0 1 0 1 0 1 OUTPUT Q Q (L0) (L1)
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Part 4: D Flip-Flop 4. Construct the logic diagram of Fig. 13-4. Verify the logical property of the D Flip-Flop by completing the data in the Table 13-4. Take note of the effect of CLOCK on the output. Fig. 13-4: Clocked D Flip-Flop
CLOCK
Table 13-4: Truth table of clocked D flip-flop INPUT D 1 0 1 0 CLOCK 1 1 0 0 OUTPUT Q Q (L0) (L1)
Part 5: IC type Dual JK Flip-Flop 5. Construct the experimental circuit of Fig. 13-5 and verify its truth table given in Table 13-5.
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Fig. 13-5: 74LS76 IC type Dual JK flip-flop
Table 13-5: Truth table of the 74LS76 Dual JK flip-flop INPUT CLOCK PRESET CLEAR x x x x x x x x x 0 0 1 1 0 0 1 1 Note: OUTPUT Q L1 L0 0 1 1 q 1 0 q
J K Q x x 1 x x 0 x x 1 0 0 q 0 1 1 1 0 0 1 1 q
means clock transition from HIGH to LOW level.
Part 6: IC type Dual D-type Flip-Flop 6. Construct the experimental circuit of Fig. 13-6 and verify its truth table given in Table 13-6. Fig. 13-6: 74LS74 dual D-type flip-flop
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Table 13-6: Truth table of the 74LS74 dual D-type flip-flop INPUT OUTPUT CLOCK PRESET CLEAR D Q Q L1 L0 x 0 1 x 1 0 x 1 0 x 0 1 x 0 0 x 1 1 1 1 1 1 0 1 1 0 0 1 0 1 1 x q q 1 1 1 x q q Note: means clock transition from LOW to HIGH level.
OBSERVATION AND ANALYSIS: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
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QUESTIONS: 1. 2. 3. 4. 5. 6. What is race condition? Is a flip-flop a bi-state device? Why? Do all available flip-flops have two complementary outputs? What is the difference between a level-triggered and an edge-triggered device? What is a T flip-flop? Draw the circuit implementation of a flip-flop using a 74LS76 IC. The output of a flip-flop can be cleared or set automatically upon initial application of power to the circuit. Draw the circuit to show how to initially clear the output of the 74LS76 flip-flop IC upon application of power to it by adding resistor and capacitior.
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EXPT. NO. 14: 8-BIT LATCH OBJECTIVE: To verify the operation the operation of an 8-bit latch using 74LS373.
SUGGESTED READINGS: Discussion about latches and tri-state gates. Digital Computer Electronics by Malvino & Brown, pp. 95-98; Digital Design by Mano, pp. 207-208. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of DTL05 or any digital trainer. MATERIALS REQUIRED: Description Digital trainer IC: 74LS373 Breadboarding wire Qty. 1 1 1 set
WARNING: 1. Make sure you are using the correct supply voltage as specified. 2. Do all wiring with power OFF. 3. Never reverse the polarity of the power supply to prevent damage on the IC. Refer to Appendix B for the ICs and other components in pin configurations.
PROCEDURE: 1. With power OFF, construct the circuit as shown in Fig. 14-1. Fig. 14-1:
2. Set all the DATA (D7-D0) and CONTROL (K1, K0) switches to LO before applying power to the circuit.
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3. Apply power to the circuit and record the output states of the logic indicators in Table 14-1. 4. Change the DATA (D7-D0) switch settings to 10101010 and record the resulting logic indicator output in the Table 14-1. Table 14-1: table for step #4 INPUT
STEP
CONTROL
OUTPUT LOGIC INDICATORS

D0 L7 L6 L5 L4 L3 L2 L1 L0
DATA SWITCHES
SWITCHES
NO.
K1
K0
D7
D6
D5
D4
D3
D2
D1
3 4 5 6 7 8 9 Note:
0 0 0 1 0 1 0
0 0 0 0 0
0 1 1 1 1 1 1
0 0 0 0 0 1 1
0 1 1 1 1 0 0
0 0 0 0 0 0 0
0 1 1 1 1 0 0
0 0 0 0 0 1 1
0 1 1 1 1 1 1
0 0 0 0 0 0 0
means momentary HIGH state.
5. Using the same setting of DATA switches as in step 4, set the CONTROL switch K0 momentary, to H1 and record the resulting logic indicator output in Table 14-1. 6. Then set the CONTROL switch K1 to H1 and record the results in Table 14-1. 7. Return the CONTROL switch K1 to L0 and record the results in the Table 14-1. 8. Again, set the CONTROL switch K1 to H1, then change the DATA (D7-D0) switches to 11000110 and set the CONTROL switch K0 momentary to H1. Record the results in Table 14-1. 9. Set the CONTROL switch K1 to L0 and record the results in Table 14-1. 10. Set the DATA switches (D7-D0) to any combination and observe what happens to the output display by the logic indicator. 11. Repeat step # 10 with the CONTROL switch K0 set to H1.
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OBSERVATION AND ANALYSIS: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ When you have completed all of the above, have your laboratory instructor sign below: ________________________________
QUESTIONS: 1. 2. 3. 4. Describe the functions of the two input pins G and OC of the 74LS373. What specific type of triggering does the 74LS373 used? Can we tie respective inputs of two or more 74LS373 as in the so called bus sharing? How about the outputs? Why? In the Signetics TTL Data Manual, the 74LS373 is described as an octal transparent latch with 3-state outputs while the 74LS374 is described as an octal D flip-flop with 3-state outputs. Can we always use the 74LS374 as a substitute for 74LS373 and vice versa? Why?
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EXPT. NO. 15: ASYNCHRONOUS OR RIPPLE COUNTERS OBJECTIVES: 1.To construct and test a 4-bit binary ripple counter using flip-flop ICs. 2. To construct and test a BCD ripple counter using flip-flop ICs. 3. To construct and test a 4-bit binary ripple counter using 74LS93. 4. To construct and test a BCD ripple counter using 74LS93.
SUGGESTED READINGS: Design and construct of ripple counters and their characteristics, divide-by-n counters and frequency dividers. Digital Computer Electronics by Malvino & Brown, pp. 110-120; Digital Design by Mano, pp. 272-277. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of a digital trainer and an oscilloscope, and be able to read and interpret the TTL, data book. MATERIALS REQUIRED: Description Digital trainer Oscilloscope ICs: 74LS00 74LS93 74LS76 74LS08 Breadboarding wires
Qty. 1 1 1 1 2 1 1 set
WARNING: 1. 2. 3. Do all wiring or any change in wiring with power OFF unless otherwise specified in the procedure. Make sure you are using the correct supply voltage as specified. Never reverse the polarity of the power supply to prevent damage to the IC. Refer to Appendix B for the ICs and other components pin configuration.
PROCEDURE: Part 1: 4-Bit Binary Ripple Counter using Flip-flop ICs 1. Construct the circuit as shown in Fig. 15-1. Clear the counters output by referring to the function table shown in Table 15-1. Set the CLK output to approximately 1 Hz and verify the circuits count sequence by completing the data in Table 15-2.
2.
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Fig. 15-1: 4-bit ripple counter using flip-flops
Table 15-1: Function table of the circuits of Fig. 15-1 and Fig. 15-2 INPUT START/STOP CLEAR x 1 0 0 1 1 CLK x FUNCTION clear output count up no change
Note: x means dont care. means CLK transition from HIGH to LOW level.
3.
Set clock frequency to 500Hz and measure the frequency of all the outputs Q1, Q2, Q4 and Q8 using an oscilloscope. Record your answers on the spaces provided below. Output Q8 Q4 Q2 Q1 Frequency _________ _________ _________ _________
= = = =
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Table 15-2: Count Sequence for counter of step #2 Q8 (L3) Q4 (L2) Q2 (L1) Q1 (L0) DECIMAL EQUIVALENT
Part 2: BCD ripple counter using flip-flop ICs 4. Construct the circuit as shown in Fig.15-2. Verify its count sequence by repeating steps #1 and #2; however, record the data in Table 15-3. Fig. 15-2: BCD ripple counter using flip-flop ICs
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Table 15-3: Count Sequence for the counter of step #4 Q8 (L3) Q4 (L2) Q2 (L1) Q1 (L0) DECIMAL EQUIVALENT
Part 3: 4-Bit Binary Ripple Counter using 74LS93 IC 5. Construct the circuit of Fig. 15-3.
Fig. 15-3: 4-bit binary ripple counter using 74LS93 IC
6.
Clear counter by momentarily switching K0 to a H1 condition. Verify its count sequence by repeating step #2; however, record the data in Table 15-4. Set clock frequency to 500 Hz and measure the frequency of all the outputs Q1, Q2, Q4 and Q8 using an oscilloscope. Record your results on the spaces provided below. Output Frequency Q8 = _________ Q4 = _________ Q2 = _________ Q1 = _________
7.
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Table 15-4: Count Sequence for the counter of step 6 Q8 (L3) Q4 (L2) Q2 (L1) Q1 (L0) DECIMAL EQUIVALENT
Part 4: BCD Ripple Counter using 74LS93 IC 8. Construct the circuit of Fig. 15-4. Repeat step #6 and record your results in Table 15-5.
Fig. 15-4: BCD ripple counter using 74LS93 IC.
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Table 15-5: Count Sequence for the counter of step #8 Q8 (L3) Q4 (L2) Q2 (L1) Q1 (L0) DECIMAL EQUIVALENT
OBSERVATION AND ANALYSIS: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
When you have completed all of the above, have your laboratory sign below:
____________________________
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QUESTIONS: 1. 2. 3. 4. 5. Basically, each can JK flip-flop in the circuit of Fig. 15-1 is configured as ______flipflop. Referring to the results of step #3, what is the function of each stage of JK flip-flop in the circuit of Fig. 15-1? How many T flip-flop are needed to generate a 4-Hz clock signal from a clock source of 256 Hz? A divide-by-6 counter divides the input clocks frequency by 6. Draw the circuit showing how a 74LS93 ripple counter IC can be used to construct a divide-by-6 counter. A real-time clock can be constructed by cascading ripple counters. From a 1-Hz clock source, determine the numbers of divide-by 10 and divide-by-6 counters needed to construct a real-time clock. Draw its block diagram.
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EXPT. NO. 16: SYNCHRONOUS COUNTERS OBJECTIVES: 1. To construct and test a 4-bit binary synchronous counter using flip-flop ICs. 2. To construct and test a BCD synchronous counter using flip-flop ICs. 3. To verify the operation of 74LS193-presettable 4-bit binary up/down synchronous counter IC. 4. To construct and test a BCD synchronous counter using 74LS193 IC and NAND gate.
SUGGESTED READINGS: Discussions on construction and analysis of synchronous counters with up/down count sequence and parallel loading. REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of the digital trainer, and be able to read and interpret the TTL data book. MATERIALS REQUIRED: Description Digital trainer ICs: 74LS76 74LS193 74LS08 74LS10 Breadboarding wires WARNING: 1. 2. 3. Do all wiring or any change in wiring with power OFF unless otherwise specified in the procedure. Make sure you are using the correct supply voltage as specified. Never reverse the polarity of the power supply to prevent damage on the IC. Refer to Appendix B for the ICs and other components pin configurations. Qty. 1 2 1 1 1 1 set
PROCEDURE: Part 1: 4-Bit Binary Synchronous Counters using Flip-flop ICs 1. Construct the circuit as shown in Fig. 16-1. Clear the counters output by referring to the function table shown in Table 16-1. Set the CLK output to approximately 1 Hz and verify the circuits count sequence by completing the data in Table 16-2.
2.
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Fig. 16-1: 4-bit binary synchronous counter using flip-flops
Table 16-1: Functions table of the circuits of Fig. 16-2 INPUT START/STOP CLEAR (K1) (K0) x 1 0 Note: x means dont care Means CLK transition from HIGH to LOW level. 0 1 1
FUNCTION CLK x Clear output Count up No change
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Table 16-2: Count Sequence for counter of step #2 Q8 (L3) Q4 (L2) Q2 (L1) Q1 (L0) DECIMAL EQUIVALENT
Part 2: BCD Synchronous Counter using Flip-flop ICs 3. Construct the circuit as shown in Fig. 16-2. Verify its count sequence using the same function table shown in Table 16-1, and record the results in Table 16-3.
Table 16-3: Count sequence for the counter of step #3 Q8 (L3) Q4 (L2) Q2 (L1) Q1 (L0) DECIMAL EQUIVALENT
106
Fig. 16-2: BCD synchronous counter using flip-flop ICs
Part 3: Functional Operation of 74LS193 IC 4. Construct the circuit of Fig. 16-3.
Fig. 16-3: 4-bit binary synchronous counter using the 74LS193 IC counter
5.
Verify the function table of the 74LS193 IC counter given in Table 16-4. Adjust the CLK frequency for an easy monitoring of its count sequence. Record its count-up sequence that starts from 0000 in Table 16-5.
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Table 16-4: Function table of the 74LS193 IC counter INPUT CLR (K0) 1 0 0 0 LOAD (K1) x 0 1 1 UP (CLK) x x NC DN (CLK) x x NC Clear counter output Load input data Count up Count down FUNCTIONS
Note: x means dont care. NC means no connection. Means CLK transition from LOW to HIGH level.
Table 16-5: Count-up sequence of the 74LS193 circuit of step #5 Q8 (L3) Q4 (L2) Q2 (L1) Q1 (L0) DECIMAL EQUIVALENT
Part 4: 74LS193 IC Counter Applications 6. Construct the circuit of Fig. 16-4. Using the functions table of Table 16-4, verify the circuit operation and record your results in Table 16-6.
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Fig. 16-4: 74LS193 IC application circuit as a BCD counter
Table 16-6: Count Sequence for the counter circuit of step #7 Q8 (L3) Q4 (L2) Q2 (L1) Q1 (L0) DECIMAL EQUIVALENT
OBSERVATION AND ANALYSIS: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
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CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
___________________________
QUESTIONS: 1. 2. 3. 4. 5. What do you mean by synchronous clocking? What is decade counting? Why is the 74LS193 described as presettable? Referring to the TTL Data Manual, what single IC can we use to implement the BCD counter circuit of Fig. 16-4? Draw the circuit that implements a mod-12 counter using 74LS193 and external gates.
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EXPT. NO. 17: SHIFT REGISTERS OBJECTIVE: To verify the different modes of operation of a shift register using a 4-bit universal shift register IC 74LS194. SUGGESTED READINGS: Shift registers types, operations and applications. Digital Computer Electronics by Malvino & Brown, pp. 106-110; Digital Design by Mano, pp. 257-271. REQUIRED SKILLS: The students must be familiar with the use of digital trainer and be able to read and interpret a device function table. MATERIALS REQUIRED: Description Digital trainer ICs: 74LS194 Breadboarding wires Qty. 1 1 1 set
WARNING: 1. 2. 3. Do all wiring or any change in wiring with power OFF unless otherwise specified in the procedure. Make sure you are using the correct supply voltage as specified. Never reverse the polarity of the power supply to prevent any damage to the IC. Refer to Appendix B for the ICs and other components pin configurations.
PROCEDURE: Part 1: Parallel Loading 1. Study the functions table of the 74LS194 IC shown in Table 17-1 and construct the circuit as shown in Fig. 17-1. Do not disconnect this circuit after you are through with this part. You will be using this circuit all throughout the experiment. Verify its parallel load operation using the data given in Table 17-2 and record your results under the OUTPUT column. Take note that the CLK is manually controlled by the DATA Switch D7. You should set the required CONTROL and DATA inputs given in Table 17-2 before activating the said CLK (D7).
2.
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Fig17-1: Shift register using 74LS194 IC
DATA & CONTROL SWITCHES NOTE: D3, D2, D1, D0 = PARALLEL INPUT DATA (D, C, B, A) L3, L2, L1, L0 = PARALLEL OUTPUT DATA (QD, QC, QB, QA) L0 = SHIFT LEFT SERIAL DATA OUTPUT L3 = SHIFT RIGHT SERIAL DATA OUTPUT D5 = SHIFT RIGHT SERIAL DATA INPUT (SR) D4 = SHIFT LEFT SERIAL DATA INPUT (SL) D6 = CLEAR INPUT (CLR) D7 = MANUAL CLOCK INPUT (CLK) K1-K0 = MODE SELECT INPUTS (S1-S0)
Table 17-1: Function Table of 74LS194IC

INPUT SERIAL DATA DS DS L R X x X X X X l H X X l h X X OUTPUT PARALLEL DATA A X X dA X X X x B x X dB X X X X C X X dC X X X x D x X dD X X X X PARALLEL DATA QA L qA qA QB qB L H QB L qB qB qC qC qA qA QC L qC qC qD qD qB qB QD L qD qD L H qC qC
OPERATING MODE Reset Hold Parallel load Shift left
CONTROL SIGNALS CLK 0 CL K L H H H H S 1 X l L h l l l S0 X l h l l h h
Shift right
H H
Note:
H = HIGH voltage level L = LOW voltage level h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition. l = LOW voltage level one setup prior to the LOW-to-HIGH clock transition. X = dont care d (q) = lower case letter indicates the state of the referenced input(output) one setup time prior to the LOW-to-HIGH clock transition = LOW-to-HIGH clock transition
112
Table 17-2: Parallel load mode

INPUT SERIAL DATA DSR DSL D5 D4 X x X X X X X X X X x X OUTPUT PARELLEL DATA A D0 X h l l l h B D1 X l h l l h C D2 X h l h h l D D3 X l h h h l PARELLEL DATA QA L0 QB L1 QC L2 QD L3
CLK NO. 1 2 3 4 5 6
CONTROL SIGNALS CLK CLK D7 D6 X L H H H H H S1 K1 X h h l h h S0 K0 X h h l h h
Note:
means momentary HIGH state of D7 See note below Table 17-1 about other variables.
3. Verify its shift left operation using the data given in Table17-3 and record your results under the OUTPUT column. As in part 1, you should set the required CONTROL and DATA inputs before activating the CLK (D7).
Part 2: Shift Left Operation Table 17-3: Shift left Mode

INPUT SERIAL DATA DSR DSL D5 D4 X X X X X l X l X l X l X X X h X h X h x h OUTPUT PARALLEL DATA A D3 l X X X X X h X X X X B D2 h X X X X X l X X X X C D1 l X X X X X h X X X x D D0 h X X X X X l X X X X PARALLERL DATA QA L0 QB L1 QC L2 QD L3
CLK NO. 1 2 3 4 5 6 7 8 9 10 11
CONTROL SIGNALS CLK CLK D7 D6 H H H H H H H H H H H S1 K1 h l h h h h h h h h h S0 K0 h l l l l l h l l l l
Note:
means momentary HIGH state of D7. See note below Table 17-1 about other variables.
113
Part 3: Shift Right Operation 4. Verify its shift right operation using the data given in Table 17-4 and record your results under the OUTPUT column. As in part 1, you should set the required CONTROL and DATA inputs before activating the CLK (D7).
Table 17-4: Shift Right Mode

INPUT SERIAL DATA DSR DSL D5 D4 x X x X l X l X l X l X x X h X h X h X h x OUTPUT PARALLEL DATA A D0 h x x x x x l x x x x B D1 l x x x x x h x x x x C D2 h x x x x x l x x x x D D3 l x x x x x h x x x PARALLEL DATA
CLK NO. 1 2 3 4 5 6 7 8 9 10 11
CONTROL SIGNALS CLK CLK D7 D6 H H H H H H H H H H H S1 K1 h L H H H H H H H H H S0 K0 h l l l l l H l l l l
Note:
means momentary HIGH state of D7. See note below Table 17-1 about other variables.
________________________________________________________________________
114
CONCLUSION:
_________________________________ QUESTIONS: 1. Define the following : 2. 3. 4. 5. PISO SIPO PIPO SISO What is a controlled shift register? Why is a 74LS194 IC described as a universal shift register? Can we consider a shift register a storage register? Give at least two applications of a shift register.
115
EXPT. NO. 18: MEMORY DEVICES OBJECTIVES: 1. To verify the behavior of a random access memory (RAM) unit and its Storage capability using a 44 file register IC (74LS670). 2. To construct and test a read only memory (ROM) circuit using a decoder IC and diodes. 3. To expand the memory location of a RAM device 4. To use a memory device to implement a Boolean function in combinational logic design.
SUGGESTED READINGS: Topics converting RAM? ROM devices, file registers, combinational logic design. Digital Computer Electronics by Malvino &Brown, pp. 130-137: Digital Design by Mano,pp. 180-186,289-299. REQUIRED SKILLS: The student must be familiar with the use of a digital trainer and be able to read and interpret a device function table. MATERIALS REQUIRED: Description Digital Trainer ICs: 74LS86 74LS138 74LS670 Diodes: IN4148 Resistors: 4.7K Breadboarding wire WARNING: 1. Do all wiring or any change in wiring with the power OFF unless otherwise specified in the procedure. 2. Make sure you are using the correct supply voltage as specified. 3. Never reverse the polarity of the power supply to prevent damage on the IC. Refer to Appendix B for the ICs and other components pin configurations Qty. 1 1 1 2 7 4 1set
PROCEDURE: Part 1: RAM Functional Operation 1. Connect the circuit as shown in the Fig. 18-1 and verify its function table, shown in Table 18-1, by writing and reading the data in the corresponding memory location give in Table 18-2.
2. Ask your instructor to check that you have already stored the data given in Table 18-2. 116
FIG. 18-1: RAM Experimental Circuit
DATA LINE
LOGIC INDICATIONS ADDRESS
LINE ENABLE
Table 18-1: 74LS670 function tables; read and write mode A. Write Mode: OPERATING MODE Write Data Data latched B. Read Mode: OPERATING MODE Write data Data latched Note: x means dont care Z means high impedance INPUT RE L L H INTERNAL LATCHES L H x OUTPUT Qn L H (z) INPUT WE L L H Dn L H X INTERNAL LATCHES L L No change
Table 18-2: Table for step #1 ADDRESS B 0 0 1 1 A 0 1 0 1 D3 0 0 0 1 D2 0 0 1 0 DATA D1 0 1 0 0 D0 1 0 0 0
117
Part 2: Read Only Memory (ROM) 3. Connect the circuit as shown in Fig.18-2 and verify its function table, shown in Table18-3, by and reading the stored data in the corresponding memory location given in Table18-4. Fig.18-2: ROM experimental circuit
Table 18-3: ROM circuit function table

MODE OF OPERATION Read Disabled READ ENABLE (K0) L H OUTPUT (Q3-Q0) Content of selected address H
Table 18-4: Table for step #3.

ADDRESS D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 118 Q3 (L3) OUTPUT Q2 Q1 (L2) (L1)
Q0 (L0)
Part 3: Memory Expansion 4. Construct the circuit as shown in Fig. 18-3. This circuit also follows the function table shown in Table 18-1. 5. Verify its operation by writing and reading the data in the corresponding memory location given in Table 18-5. Do not disconnect the circuit after finishing this part. You will be using it on the next part of this experiment. 6. Ask your instructor to check that you have already stored the data given in Table 18-5. Fig.18-3: 44 memory device expanded to 84
119

ADDRESS D1 0 0 1 1 0 0 1 1 OUTPUT D0 0 1 0 1 0 1 0 1 Q3 0 0 0 1 1 0 0 1 Q2 0 0 1 0 0 0 1 0 Q1 0 1 0 0 0 1 0 1 Q0 1 0 0 0 1 0 0 0
D2 0 0 0 0 1 1 1 1
Part 4: Boolean Function Implementation 7. Using Table 18-6, derive the truth table of the given Boolean functions below: F1 (A2, A1, A0) = (3, 5, 7) F2 (A2, A1, A0) = (2, 5, 6, 7) F3 (A2, A1, A0) = (1, 4, 7) F4 (A2, A1, A0) = (0, 1, 3, 6) 8. Implement the Boolean FUNCTIONS GIVEN IN STEP #5 USIG THE EXPERIMENTAL CIRCUIT OF Fig.18-3 and derive the truth table in Table 18-6. Assign the four given Boolean functions to the four logic indicators as follows: F1=L0, F2=L1, F3=L2, F4=L3. 9. Test your implementation and record the results by completing the column under the logic indicators, L3-L0, in Table 18-6. Table 18-6: Table for steps #7 to #9
INPUT A1 0 0 1 1 0 0 1 1 OUTPUT A0 F4 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 FUNCTIONS F3 F2 F1 LOGIC INDICATOR L3 L2 L1 L0
A2
120
CONCLUSION: ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
_____________________________________
121
QUESTIONS: 1. 2. 3. 4. 5. What is a RAM? What are volatile and non-volatile memory devices? Classify the circuits of Fig. 18-2 and fig. 18-2 as volatile or non-volatile. Define the organizational structure of the circuit of Fig. 18-2. What is the difference between the memory capacity and memory organization?
122
4.1 Appendix A: Electrical/electronic Symbols
No.
Component
Symbol
Reference Variable
FIXED RESISTOR
TRIMMER RESISTOR
VR
POTENTIOMETER
VR or POT
LDR (Light dependent Resistor)
LDR
THERMISTOR
R, TH
NON-POLARIZED CAPACITOR
POLARIZED CAPACITOR
INDUCTOR
TRANSFORMER
10
DIODE
11
LED
D, LED
12
ZENER DIODE
D, ZD
13
PHOTODIODE
D, PD
123
No.
Component
Symbol
Reference Variable
14
NPN TRANSISTOR
15
PNP TRANSISTOR
16
DARLINGTON TRANSISTOR
17
PHOTOTRANSISTOR
Q, PT
18
n-CHANNEL JFET
19
P-CHANNEL JFET
20
N-CHANNEL DEPLETION TYPE MOSFET
21
p-CHANNEL DEPLETION TYPE MOSFET
22
SCR
D, Q, SCR
23
TRIAC
24
n-CHANNEL UJT
25
p-CHANNEL UJT
26
SPEAKER
SPK
27
MICROPHONE
124
MIC
No.
Component
Symbol
Reference Variable
28
SPST SWITCH
SW
29
SPDT SWITCH
SW
30
PUSH BUTTON SWITCH NORMALLY OPEN
SW
31
PUSH BUTTON SWITCH NORMALLY CLOSED
SW
32
FUSE
125
4.2 Appendix B: Component Pin Configurations I. Digital Integrated Circuits 74LS00 74LS08
74LS02
74LS10
74LS04, 74HC04
74LS20
74LS07
74LS27
126
74LS32
74LS83
74LS47
74LS86
74LS74
74LS125
74LS76
74LS138
127
74LS139
74LS373
74LS153
74LS670
74LS193, 74LS192
74LS260
II. Transistors: NPN PNP
III. Diode:
128
4.3
Appendix C:
Functional Description and Electrical Specifications of Selected Devices
I Discrete Devices Maximum Rating Diodes: 1N4148 Switching Signal Diode - 200mA, 100V 1N4000 Rectifier Diode - 1A, 50V 9013 NPN General Purpose 0.625 W, 25V, 0.8A 9012 PNP General purpose 0.625 W, 25V, 0.8A SPDT, Coil-6V DC, and Contact-any rating 1/4 Watt, 5% tolerance
Transistors:
Relay: Resistors:
II. Integrated Circuits Functional Description 7407 74C04 74LS00 74LS02 74LS04 74LS08 74LS10 74LS20 74LS27 74LS32 74LS47 74LS76 74LS83 74LS86 74LS93 74LS125 74LS139 74LS153 74LS192 74LS193 74LS194 74LS373 74LS670 74LS260 - Hex Buffer/driver (open collector) - Hex Inverter (CMOS version) - Quad 2-Input NAND Gate - Quad 2-Input NOR Gate - Hex Inverter - Quad 2-Input AND Gate - Triple 3-Input NAND Gate - Dual 4-Input NAND Gate - Triple 3-Input NOR Gate - Quad 2-Input OR Gate - BCD to 7-Segment Decoder/Drivers - Dual JK Flip-Flop - 4-Bit Full Adder - Quad 2-Input XOR Gate - 4-Bit Binary Ripple Counter - Quad 3-State Buffer - Dual 1-of-4 Decoder/Demultiplexer - Dual 4-Line to 1-Line Multiplexer - Presettable BCD Decade Up/Down Counter - Presettable 4-Bit Binary Up/Down Counter - 4-Bit Bidirectional Universal Shift Register - Octal Transparent Latch with 3-State Outputs - 4x4 Register File (3-State) - Dual 5-Input NOR Gate
129
III. Important DC Characteristics of 74LS Family Parameter Input HIGH voltage Vih = 2.0V minimum LOW voltage Vil = 0.8V maximum Input Output LOW voltage Vol = 0.5V maximum Output HIGH voltage Voh = 2.7V minimum Output HIGH current Ioh = -400mA maximum Input HIGH current Iih = 20uA maximum Input LOW current Iil = -0.4mA maximum Output LOW current Iol = -8.0mA maximum Output short circuit current Ios = -100mA maximum IV. Important DC Characteristics of 74HC04 Parameter Input HIGH voltage Vih = 70 Vdd minimum Input LOW voltage Vil = 30 Vdd Output LOW voltage Vol = 0.1V maximum Output HIGH voltage Voh = 97 Vdd minimum Input HIGH current Iih = 0.1uA maximum Input LOW current Iil = -0.1uA maximum Output HIGH current Ioh = -200uA maximum Output LOW current Iol = 4mA maximum
130
4.4
Appendix D: Steps in Troubleshooting Electrical/Electronic Equipment
Troubleshooting is the process of narrowing down the possible reasons for a failure until you pinpoint the cause. Effective troubleshooting follows a systematic approach in solving a problem. Troubleshooting any electrical/electronic circuit or equipment requires that you: 1. KNOW THE SYSTEM. This means understanding the detailed operation of the system by knowing: - The supposed sequence of events. - What components cause each event. Knowing the system's detailed operation may require studying its block-schematic- and even wiring-diagram. A block diagram shows the different sections that compromise the whole system. A schematic diagram shows the electrical/electronic circuits used in each block/section of the whole system. A wiring diagram is like a simple road map that shows where the components are, and where the wires go between them. INVESTIGATE THE SYMPTOMS OF FAILURE. The symptoms of failure will often indicate which section of the machine is in real trouble. This step usually provides you with important clue in fixing the defective machine. LIST PROBABLE CAUSES OF TROUBLE. Based on what you know and the clues uncovered, list the probable or likely causes of trouble. Usually, this can be done in your head. But if a machine is complicated, it helps to write it down. ELIMINATE POSSIBILITIES SYSTEMATICALLY. This means performing tests on the machine in logical order. Usually, you are trying to eliminate a whole group of possibilities with one test, narrowing down the choices as quickly as possible until you are left with actual cause of trouble. DETERMINE THE ROOT CAUSE OF TROUBLE. Getting the equipment running again is often not the end of the troubleshooting procedure. You may be able to discover why the trouble happened, and do something to keep it from happening again.
2.
3.
4.
5.
131
4.5
Appendix E: Application Circuits
TTL COMPATIBLE LOGIC PROBE
132
SHORT CIRCUIT PROTECTION In this circuit the diodes D1, D2 and D3 are configure as an AND gate. When any of the three voltage regulator's output goes LOW, due to a short circuit from any of the regulator's positive terminal and the ground, the diode-AND-gate's output goes LOW and turn the transistors Q1 and Q2 off, thus cutting the power applied to the three voltage regulators
LIGHT ACTIVATED TOGGLE SWITCH The circuit can be used to practically turn on/off any electrical device by just triggering the phototransistor (FPT-100) with a visible light. It can be used as an on/off remote control or in an alarm circuit. Trimmer resistor VR is used to adjust the circuit's sensitivity to light intensity.
133
TRANSISTOR SWITCH/DRIVER The circuit is very useful in multiplexing LED 7-Segment or Matrix display
LED SEQUENTIAL
134
4.6
Appendix F: Suggested Laboratory Grading System LABORATORY GRADE Attendance Attitude Projects Expt. Average Total 40% 10% 15% 35% 40% 100%
DETAILS OF LABORATORY GRADE: EXPERIMENTAL GRADE Group Preliminary Report Grading System: 50% Group Performance 20% Accuracy of Data 35% Speed of Performance 20% Circuit Construction 25% Total 100% Individual Report Grading System: Individual Performance Attitude Punctuality Observation Analysis Conclusion Total Experiment Grade: 50% 15% 15% 20% 25% 25% 100% 100%
EXPERIMENT AVERAGE = Sum of Experiment Grade divided by the number of experiments performed PROJECT GRADE Presentation Overall Appearance Functionality Oral Defense Documentation Total:
15% 15% 20% 30% 10% 100%
135
4.7
Appendix G: Summary of Experiment Grades
EXPT.NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 AVERAGE
GRADE
136
4.8
Appendix H: Students Accountability Record
Students Name: _______________________________________________________________ Item No.
Particulars
Qty.
Date
Remarks
Verified by: Cleared by:
137
4.9
Appendix I: Resistor Color Coding
138

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PART 1

1.1 1.2 1.3 1.4 1.5

1.1 DOs AND DONTs Inside the Laboratory Room

Guidelines in Performing an Experiment

Applying Up/Down Thinking

This means that if V is constant, and R increases ( I increases ( ).

Titles of Experiment and their Objectives

EXPT. NO. 1: OBJECTIVE: EXPT. NO. 2: OBJECTIVE: EXPT. NO. 3: OBJECTIVES:

EXPT. NO. 4: OBJECTIVES:

EXPT. NO. 5: OBJECTIVES:

EXPT. NO. 6: OBJECTIVES:

EXPT. NO. 7: OBJECTIVE:

EXPT. NO. 8: OBJECTIVE: EXPT. NO. 9: OBJECTIVE:

EXPT. NO. 10: OBJECTIVES:

EXPT. NO. 11: OBJECTIVES:

EXPT. NO. 12: OBJECTIVES:

EXPT. NO. 13: OBJECTIVE:

EXPT. NO. 14: OBJECTIVE: EXPT. NO. 15: OBJECTIVES:

EXPT. NO. 16: OBJECTIVES:

EXPT. NO. 17: OBJECTIVE:

EXPT. NO. 18: OBJECTIVES:

Summary List of Required Materials

DTL-05 Digital Trainer Functional Features

Definition of Terms and Variables Used in the Experimental Circuits

Table 1-1: Table for step #2

7- SEGMENT DISPLAY PATTERN

7- SEGMENT DISPLAY PATTERN

Table 1-2: for step #5 LOGIC INDICATORS L3 L2 L1 L0 7- SEGMENT DISPLAY PATTERN

Table 1-3: Table for step #7

7- SEGMENT DISPLAY PATTERN

7- SEGMENT DISPLAY PATTERN

OBSERVATION AND ANALYSIS:

a)binary b)BCD c) Hexadecimal How do you describe the function of 74LS193?

d) none of the above

Fig. 2-1: Gray code-to-binary converter

Table 2-2: Truth table for BCD-to-excess three code converter

Fig. 2-2: BCD-to-excess three code converter

OBSERVATION AND ANALYSIS:

OBSERVATION AND ANALYSIS:

LOGIC INDICATORS 1.3 1.2 1.1 1.0

Table 5-3: Table for Step #6 DATA SWITCHES D1 D0 LO LO LO HI HI LO HI HI OUTPUT (ON/OFF)

per gate = _________________ per gate = _________________

Table 8-1: X 0 0 0 0 1 1 1 1 INPUT Y Z 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 OUTPUT F1 L0

Fig. 8-1: Logic Diagram to be simplified.

where 0 = LO, and 1 = HI

Fig. 10-1: 4-line to 1-line multiplexer experiment circuit

OUTPUT DATA LOGIC INDICATOR Y LO HI-Z 0 1 0 1 0 1 0 1

Fig. 10-3: Block diagram for MUX expansion.

Fig. 10-4: Experimental circuit for MUX expansion.

Note: For the select line K2, 1 = +5V and 0 = GND.

OUTPUTS SELECT LINES LOGIC INDICATORS ENABLE

OUTPUT LOGIC INDICATOR

INPUT DATA OUTPUT LOGIC INDICATOR

Fig. 12-1 Logic Diagram of a half-adder circuit

INPUT DATA OUTPUTS MINUEND SUBTRAHEND

DATA GROUP B CARRY - IN

Table 12-4: 4-bit parallel adder using a 74LS83

Fig. 13-1: NAND RS Latch

Fig. 13-5: 74LS76 IC type Dual JK flip-flop

per gate = _ per gate = _