Customer Specific Device from ON Semiconductor DAP011/DAP011C PWM CurrentMode Controller for HighPower Universal OffLine Supplies

5.0 V 5.0 mA Reference Voltage Internal Temperature Shutdown Direct Optocoupler Connection Extremely Low NoLoad Standby Power Adjustable SoftStart This is a PbFree Device*

Housed in an SO14 package, the DAP011/DAP011C represents an enhanced version of the Maximus, DAP008, controller. Due to its high drive capability, SpeedKing drives large gatecharge MOSFETs which, together with internal ramp compensation and a user selectable frequency jittering, ease the design of modern AC/DC adapters. With an internal structure operating at a fixed 65/100 kHz frequency, the controller directly connects to the highvoltage rail for a loss less and clean startup sequence. Currentmode control also provides an excellent input audiosusceptibility and inherent pulsebypulse control. Internal ramp compensation easily prevents subharmonic oscillations from taking place in continuous conduction mode designs. When the current setpoint falls below a given value, e.g. the output power demand diminishes, the IC automatically enters the socalled skip cycle mode and provides excellent efficiency at light loads. Because this occurs at a user adjustable low peak current, no acoustic noise takes place. Due to a proprietary SoftSkip technique, the absence of sharp transitions during skip mode significantly reduces acoustical noise. The DAP011/DAP011C features an efficient protective circuitry which, in presence of an overcurrent condition, disables the output pulses while the device enters a safe burst mode, trying to restart. Once the default has gone, the device autorecovers. By implementing a timer to acknowledge a fault condition, independently from the auxiliary supply, the designers task is eased when stringent fault mode conditions need to be met. A dedicated input helps triggering a latchoff circuitry which permanently disables output pulses.
Features

Typical Applications

High Power AC/DC Converters for TVs, SetTop

Boxes, etc.

Offline Adapters for Notebooks All Power Supplies

MARKING DIAGRAM
14 14 1 A WL Y WW G SOIC14 D SUFFIX CASE 751A DAP011/DAP011C AWLYWWG

1 = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package

PIN CONNECTIONS
1

NC LATCH CTIMER JITTER SKIP FB CS

2 3 4 5 6 7

14 13 12 11 10 9 8

HV NC NC REF VCC DRV GND

CurrentMode Control with Adjustable SkipCycle

Capability Internal Ramp Compensation Adjustable Frequency Jittering for Better EMI Signature AutoRecovery Internal Output ShortCircuit Protection Adjustable Timer for Improved ShortCircuit Protection Dedicated Latch Input +500 mA/800 mA Peak Current Capability Fixed Frequency Versions at 65/100 kHz
1

(Top View)

ORDERING INFORMATION
Device DAP011 DAP011C fosc (65 kHz) (100 kHz) Package SO14 (PbFree) Shipping 2500 / Tape & Reel

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2005

November, 2005 Rev. 2

Publication Order Number: DAP011/D

DAP011/DAP011C
HVBulk OVP

DAP011/DAP011C
1 2 3 4 14 13 12

*See Note + Vout

11 5 V Ref. 10 9 8

Gnd

5 6 7

Ramp Skip Adj. Freq. Jitter +

Gnd Timer Delay *This resistor prevents from negatively biasing the HV pin (14) at poweroff. Typical value is 4.7 kW.

Figure 1. Typical Application Example

PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name NC Function Description Latch CTimer Jitter Skip FB CS GND DRV VCC Ref. NC NC HV Driver output Supplies the controller Reference voltage Highvoltage input Input voltage to latch comparator Timer/softstart delay Frequency jittering speed Skip cycle adjustment Feedback pin Current sense + ramp compensation By bringing this pin above 3.0 V, e.g. via a Zener or an NTC, the circuit permanently latchesoff. Wiring a capacitor to ground helps selecting the timer duration. 10% of this duration fixes the softstart period. This pin offers a way to adjust the frequency modulation pace. By connecting a resistor to ground, it becomes possible to alter the default skip cycle level. Hooking an optocoupler collector to this pin will allow regulation. This pin monitors the primary peak current but also offers a mean to introduce ramp compensation. The controller ground. The drivers output to an external MOSFET. This pin is connected to an external auxiliary voltage. This pin delivers 5.0 V and sources up to 5.0 mA. Nonconnected for improved creepage. Nonconnected for improved creepage. Connected to the bulk capacitor, this pin powers the internal current source to deliver a startup current.

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DAP011/DAP011C
1

Latch

2 20 ms Time Constant

Timer 3

+ + Vlatch

S Q Q R

IpFlag

Fault

VtimSS +

4 V Reset + + SoftStart Ended Fault 4V Reset Skip, SoftStart IpFlag Power On Reset

VCC and Logic Management

14 HV 13 IC1

+ Vtimfault VDD Itim Jitter 4 VDD iCjit

Power Reset VCCON VCC(min) VCClatch

+ +

12 UVLO

Frequency Modulation

VDD

65/100 kHz Clock S Q Q R

11 Ref.

+ 2.iCjit VDD Iskip Skip 5 Rskip Fault/Startup Ramp VDD RFB FB 6 /3 Skip + Vskip +

10 VCC

9 Drv

Skip + SS IpFlag Iclamp

CS

LEB

8 GND

Figure 2. Internal Circuit Architecture

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DAP011/DAP011C
MAXIMUM RATINGS
Rating Power Supply Voltage, VCC Pin, Continuous Voltage Transient Power Supply Voltage, Duration < 10 ms, IVCC < 20 mA Maximum Voltage on Low Power Pins (Except Pin 9, Pin 10, Pin 5 and Pin 14) Maximum Voltage on Pin 5 Thermal Resistance, JunctiontoAir Thermal Reference JunctiontoLead (Note 3) Maximum Junction Temperature Storage Temperature Range ESD Capability, HBM Model (All Pins Except HV) ESD Capability, Machine Model Maximum Voltage on Pin 14 (HV) Symbol VCC RqJA Psi JL TJMAX Value 20 25 0.3 to 10 5.0 120 40 150 60 to +150 2.0 200 0.3 to 500 Unit V V V V C/W C/W C C kV V V

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MilStd883, Method 3015. Machine Model Method 200 V 2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78. 3. Minimum Pad FR4 Board 1 oz Copper.

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DAP011/DAP011C
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = 5C to +125C, Max TJ = 150C,
VCC = 12 V unless otherwise noted.) Characteristic SUPPLY SECTION VCC Increasing Level at which the Current Source TurnsOff VCC Level at which Output Pulses are Stopped VCC Decreasing Level at which the LatchOff Phase Ends Internal Latch Reset Level Minimum Voltage Difference between VCClatch and VCCReset Internal IC Consumption, No Output Load on Pin 9 Internal IC Consumption, 1.0 nF Output Load on Pin 9 Internal IC Consumption, LatchOff Phase Reference Voltage, Iout = 1.0 mA, TJ = 25C Reference Voltage, Iout = 5.0 mA Maximum Output Current Capability Decoupling Capacitor Connected to Pin 11 DAP011 DAP011C DAP011 DAP011C VCCON VCC(min) VCClatch VCCreset resetHyst ICC1 ICC2 ICC3 Vref1 Vref2 IrefOut Cref 10 10 10 10 10 10 10 11 11 11 11 4.9 4.8 5.0 100 11.8 8.0 1.0 12.8 9.0 6.5 5.0 1.2 1.3 1.9 2.5 5.0 13.8 10 0.6 5.1 5.13 V V V V V mA mA mA V V mA nF Symbol Pin Min Typ Max Unit

INTERNAL STARTUP CURRENT SOURCE (TJ > 5C) Highvoltage pin biased to 60 V DC. HighVoltage Current Source, VCC = 10 V (Note 4) HighVoltage Current Source, VCC = 0 VCC Transition Level for IC1 to IC2 Toggling Point Leakage Current for the High Voltage Source, Vpin 14 = 250 Vdc DRIVE OUTPUT (Lothar like) Output Voltage RiseTime @ CL = 1.0 nF, 1090% of a 12 V Output Signal Output Voltage FallTime @ CL = 1.0 nF, 1090% of a 12 V Output Signal Source Resistance Sink Resistance CURRENT COMPARATOR Input Bias Current @ 1.0 V Input Level on Pin 7 Maximum Internal Current Setpoint TJ = 25C Maximum Internal Current Setpoint TJ from 5 to 125C Default Internal Voltage Setpoint for Skip Cycle Operation Propagation Delay from Current Detection to Gate OFF State Leading Edge Blanking Duration SoftStart Duration, Ctimer = 0.22 mF INTERNAL OSCILLATOR Oscillation Frequency Maximum DutyCycle Frequency Jittering in Percentage of fOSC Swing Frequency with a 22 nF Capacitor to Pin 4 Jittering Modulator Charging Current Jittering Capacitor Peak Voltage Jittering Capacitor Valley Voltage 4. Min. value for TJ = 125C (See Figure 10). DAP011 DAP011C DAP011 DAP011C fOSC Dmax fjitter fswing ICjit VCjitP VCjitV 4 4 4 4 60 92 76 65 100 80 "5.0 "6.0 300 20 2.15 0.75 70 108 84 kHz % % Hz mA V V IIB ILimit1 ILimit2 VLskip TDEL TLEB TSS 7 7 7 7 7 7 0.95 0.93 0.02 1.0 1.0 350 100 200 10 1.05 1.07 150 mA V V mV ns ns ms Tr Tf ROH ROL 9 9 9 9 40 15 12 7.0 ns ns W W IC2 IC1 VTh Ileak 14 14 14 14 2.0 200 4.0 500 1.8 35 650 mA mA V mA

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DAP011/DAP011C
ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25C, for min/max values TJ = 5C to +125C,
Max TJ = 150C, VCC = 12 V unless otherwise noted.) Characteristic FEEDBACK SECTION Internal Pullup Resistor Pin 6 to Current Setpoint Division Ratio SKIP CYCLE GENERATION Internal Skip Reference Current Pin 5 Internal Output Impedance (Note 5) Default Skip Mode Level INTERNAL RAMP COMPENSATION Internal Ramp Level @ 25C (Note 6) Internal Ramp Resistance to CS Pin PROTECTIONS Latching Level Input Delay before Latch Confirmation Timer Level Completion Timer Capacitor Charging Current Timer Length, Ctimer = 0.22 F Typical Temperature Shutdown Temperature Shutdown Hysteresis Vlatch Tlatchdel VtimFault Itim TimerL TSD TSD_hys 2 3 3 3 2.85 140 3.05 20 4.3 10 100 40 3.25 V ms V mA ms C C Vramp Rramp 7 7 1.8 20 V kW Iskip Zout Vskip 5 5 5 40 25 1.0 mA kW V Rup Iratio 6 20 3.0 kW Symbol Pin Min Typ Max Unit

5. Maximum voltage on Pin 5 is 5.0 V. 6. A 15 kW resistor is connected from Pin 7 to the ground for the measurement.

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DAP011/DAP011C
13 9.1

12.9 VOLTAGE (V) VOLTAGE (V) 25 0 25 50 75 100 125

9.05

12.8

12.7

8.95

12.6 TEMPERATURE (C)

8.9 25 0 25 50 75 100 125 TEMPERATURE (C)

Figure 3. VCCon Voltage versus Temperature

Figure 4. VCCmin Voltage versus Temperature

1.5

2.75

1.4 CURRENT (mA) CURRENT (mA) DAP011C 1.3

2.55

DAP011C

2.35

1.2 DAP011 1.1

2.15

1.95

DAP011

1 25 0 25 50 75 100 125 TEMPERATURE (C)

1.75 25 0 25 50 75 100 125 TEMPERATURE (C)

Figure 5. Current Consumption ICC1 versus Temperature (Driver Unloaded)

Figure 6. Current Consumption ICC2 versus Temperature (Driver Loaded with 1 nF)

0.42

5.2

0.39 CURRENT (mA) VOLTAGE (V) 25 0 25 50 75 100 125

5.1

0.36

0.33

4.9

0.3 TEMPERATURE (C)

4.8 25 0 25 50 75 100 125 TEMPERATURE (C)

Figure 7. Current Consumption in Latchoff Phase versus Temperature

Figure 8. 5 mA Loaded Reference Voltage Evolution versus Temperature

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DAP011/DAP011C
550 5

500 CURRENT (mA) CURRENT (mA)

4.5

450

400

3.5

350

300 25 0 25 50 75 100 125 TEMPERATURE (C)

2.5 25 0 25 50 75 100 125 TEMPERATURE (C)

Figure 9. High Voltage Current Source Level Evolution versus Temperature when VCC = 0 V

Figure 10. High Voltage Current Source Level Evolution versus Temperature when VCC = 10 V

50

20

40 IMPEDANCE (W) 0 25 50 75 100 125 CURRENT (mA)

18

30

16

20

14

10

12

0 25

10 25 0 25 50 75 100 125 TEMPERATURE (C) TEMPERATURE (C)

Figure 11. High Voltage Current Source Leakage versus Temperature

15 1.022

Figure 12. Driver Source Output Impedance Evolution versus Temperature

13 IMPEDANCE (W) VOLTAGE (V)

1.021

11

1.02

1.019 7

5 25

1.018 0 25 50 75 100 125 25 0 25 50 75 100 125 TEMPERATURE (C) TEMPERATURE (C)

Figure 13. Driver Sink Impedance Evolution versus Temperature

Figure 14. Maximum Peak Current Limit Evolution with Temperature

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DAP011/DAP011C
66 105

103 FREQUENCY (kHz) FREQUENCY (kHz) 0 25 50 75 100 125 65

101

64

99

63

97

62 25

95 25

25

50

75

100

125

TEMPERATURE (C)

TEMPERATURE (C)

Figure 15. DAP011 Oscillator Frequency with Temperature

1.82 21.5

Figure 16. DAP011C Oscillator Frequency with Temperature

1.8 RESISTANCE (kW) 25 0 25 50 75 100 125 VOLTAGE (V)

21

1.78

20.5

1.76

20

1.74

19.5

1.72 TEMPERATURE (C)

19 25 0 25 50 75 100 125 TEMPERATURE (C)

Figure 17. Ramp Compensation Voltage Evolution with Temperature

Figure 18. Ramp Compensation Resistor Value Evolution with Temperature

3.07

3.06 VOLTAGE (V)

3.05

3.04

3.03

3.02 25 0 25 50 75 100 125 TEMPERATURE (C)

Figure 19. Latch Level Evolution with Temperature

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DAP011/DAP011C

APPLICATION INFORMATION
Introduction

SpeedKing implements a standard current mode architecture where the switchoff event is dictated by the peak current setpoint. This component represents the ideal candidate where low partcount is the key parameter, particularly in lowcost AC/DC adapters, openframe power supplies etc. Due to its high voltage technology, the DAP011/DAP011C incorporates all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as an adjustable EMI jittering and a fault timer. Currentmode operation with internal ramp compensation: implementing peak current mode control, the DAP011/DAP011C offers an internal ramp compensation signal that can easily by summed up to the sensed current. Subharmonic oscillations can thus be fought via the inclusion of a simple resistor. Internal highvoltage startup switch: reaching a low noload standby power represents a difficult exercise when the controller requires an external, lossy, resistor connected to the bulk capacitor. Thanks to an internal logic, the controller disables the highvoltage current source after startup which no longer hampers the consumption in noload situations. EMI jittering: a dedicated pin offers the ability to vary the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. Skipcycle capability: a continuous flow of pulses in not compatible with noload standby power requirements. Slicing the switching pattern in bunch of pulses drastically reduces overall losses but can, in certain cases, bring acoustic noise in the transformer. Thanks to a skip operation taking place at low peak

currents only, no mechanical noise appears in the transformer. Also, activating the softstart during skip cycle brings socalled SoftSkip benefits, greatly reducing acoustical noise in the transformer. Internal softstart: a softstart precludes the main power switch from being stressed upon startup. Its duration is equal to 10% of the fault timer, e.g. 10ms for a 100 ms timer duration. Latch input: by monitoring pin 2, the controller detects when it is brought above a latching level via a zener (OVP) or a NTC (OTP), or both. When the latch is detected, all pulses are permanently disabled and VCC goes up and down, maintaining the latch condition. When the user cycles VCC below 5.0 V, the controller gets reset and attempts to restart. Shortcircuit protection: shortcircuit and especially overload protection are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the auxiliary winding level does not properly collapse in presence of an output short). Here, every time the internal 1.0 V maximum peak current limit is activated, an error flag, Ip Flag, is asserted and a time period starts, thanks to an adjustable timer. If the timer reaches completion while the error flag is still present, the controller stops the pulses and goes into a latchoff phase, operating in a lowfrequency burstmode. To limit the fault output power, a dividebytwo circuitry is installed on the VCC pin and requires twice a startup sequence before another attempt to restart is. As soon as the fault disappears, the SMPS resumes operation. The latchoff phase can also be initiated, more classically, when VCC drops below VCC(min) (9.0 V typical).

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DAP011/DAP011C
Startup Sequence

When the power supply is first connected to the mains outlet, the internal current source is biased and charges up the VCC capacitor. When the voltage on this VCC capacitor reaches the VCCON level (typically 12.8 V), the current source turns off, reducing the amount of power being dissipated. At this time, the VCC capacitor only supplies the controller, and the auxiliary supply should take over before VCC collapses below VCC(min). Figure 20 shows the internal arrangement of this structure:
14 + IC1 or 0 10 + VCC ON VCC latch HV

and IC2. At powerup, as long as VCC is below a certain level (1.8 V typical), the source delivers IC1 (around 500 mA typical), then, when VCC reaches 1.8 V, the source smoothly transitions to IC2 and delivers its nominal value. As a result, in case of shortcircuit between VCC and GND, the power dissipation will drop to 370 x 500 m = 185 mW. Figure 21 portrays this particular behavior:
VCC

VCCON IC2 min CVCC = 22 mF IC1 min Vth

t1

t2

Figure 20. The Current Source brings VCC above 15 V and then turns off

Figure 21. The Startup Source Now Features a Dual Level Startup Current

In some fault situations, a shortcircuit can purposely occur between VCC and GND. In high line conditions (VHV = 370 VDC) the current delivered by the startup device will seriously increase the junction temperature. For instance, since IC1 equals 2 mA (the minimum corresponds to the highest Tj), the device would dissipate 370 x 2 m = 740 mW. To avoid this situation, the controller includes a novel circuitry made of two startup levels, IC1

The first startup period is calculated by the formula C x V = I x t, which implies a 22 m x 1.5 / 350 m = 94ms startup time for the first sequence. The second sequence is obtained by changing to 2 mA with a DV of VCCON VCCth = 12.8 1.5 = 11.3 V, which finally leads to a second startup time of 12.8 x 22 m / 2 m = 140 ms. The total startup time becomes 94 m + 140 m = 235 ms. Please note that this calculation is approximated by the presence of the knee in the vicinity of the transition.

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DAP011/DAP011C
As soon as VCC reaches VCCON, drive pulses are delivered on Pin 9 and the auxiliary winding increases the voltage on the VCC pin. Because the output voltage is below the target (the SMPS is starting up), the controller smoothly rampsup the peak current to Imax (1.0 V / Rsense) which is reached after a typical softstart period. This softstart period lasts typically 10% of what has been selected for the fault timer via Pin 3. As soon as the peak current setpoint reaches its maximum (during the startup period but also anytime an overload occurs), an internal error flag is asserted, Ip flag, indicating that the system has reached its maximum current limit set point (Ip = Ip maximum). As soon as the error flag gets asserted, the current source on Pin 3 is activated and charges up the capacitor connected to this pin. If the error flag is still asserted when the timer capacitor has reached the threshold level Vtim Fault, (which is about 100 ms with a 0.22 mF typically), then the controller assumes that the power supply has really undergone a fault condition and immediately stops all pulses to enter a safe burst operation. Figure 22 depicts the VCC evolution during a proper startup sequence, showing the state of the error flag:

Figure 22. An Error Flag Gets Asserted as soon as the Current Setpoint Reaches its Upper limit (1.0 V/Rsense) Here the Timer Lasts 100 ms, a 0.22 mF Capacitor being Connected to Pin 3

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DAP011/DAP011C
ShortCircuit or Overload Mode

There can be various events that force a fault on the primary side controller. We can split them in different situation, each having a particular configuration: 1. the converter regulates but the auxiliary winding collapses: this is a typical situation linked to the usage of a constantcurrent / constantvoltage (CCCV) type of controller. If the output current increases, the voltage feedback loop gives up and the current loop takes over. It means that Vout goes low but the feedback loop is still closed because of the output current monitoring. Therefore, seen

from the primary side, there is no fault. However, there are numerous charger applications where the output voltage shall not go below a certain limit, even if the current is controlled. To cope with this situation, the controller features a precise undervoltage lockout comparator biased to a VCC(min) level. When this level is crossed, whatever the other pin conditions, pulses are stopped and the controller enters the safe hiccup mode, trying to restart. Figure 23 shows how the converter will behave in this situation. If the fault goes away, the SMPS resumes operation.

Figure 23. First Fault Mode Case, the Auxiliary Winding Collapses but Feedback is Still There

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DAP011/DAP011C
2. In the second case, the converter operates in regulation, but the output is severely overloaded. However, due to the bad coupling between the power and the auxiliary windings, the controller VCC does not go low. The peak current is pushed to the maximum and the timer starts to count. Upon completion, all pulses are stopped and dual startup hiccup mode is entered. If the fault goes away, the SMPS resumes operation.

Figure 24. This Case is Similar to a Shortcircuit Where VAUX Does Not Collapse

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DAP011/DAP011C
3. A second case exists where the shortcircuit makes the auxiliary level go below VCC(min). In that case, the timer length is truncated and all pulses are stopped. The double hiccup fault mode is entered and the SMPS tries to restart. When the fault is removed, the SMPS resumes operation.

Figure 25. This Case is Similar to a Shortcircuit Where VAUX Does Collapse

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DAP011/DAP011C
The recurrence in hiccup mode can easily be adjusted by either reducing the timer or increasing the VCC capacitor.
VCC UVLOhigh t3 UVLOlow t1 Latchoff phase level Logic reset level Drv t2

Figure 26 details the various time portion a hiccup is made of:

t1

t2

100 ms

100 ms

Figure 26. The Burst Period is Ensured by the VCC Capacitor Charge/Discharge Cycle

If by design we have selected a 22 mF VCC capacitor, it becomes easy to evaluate the burst period and its dutycycle. This can be done by properly identifying all time events on Figure 26 and applying the classical formula:
t+ DV @ C i
(eq. 1)

VCC aux + Rupper aux

t1: I = ICC3 = 600 mA, DV = 9 6.5 = 2.5 V t1 =

91 ms t2: I = 3 mA, DV = 12.8 6.5 = 6.3 t1 = 46 ms t3: I = 600 mA, DV= 12.8 6.5 = 6.3 V t1 = 231ms t1 = t1 = 91 ms t2 = t2 = 46 ms The total period duration is thus the sum of all these events which leads to Tfault = 505 ms. If Tpulse = 100 ms, then our burst dutycycle equals 100/(505+100) 16.5%, which is good. Should the user like to further decrease or, to the contrary, increase this dutycycle, changing the VCC capacitor is an easy job.
Latchoff and Overvoltage Protection

20 ms time constant

C1 10 nF

Rlower

+ Vlatch

S Q Q R

latched fault

5 V reset

Figure 27. A Comparator Monitors Pin 2 and Latches Off the Part in Case the Threshold is Reached

Speedking features a fast comparator that permanently monitors Pin 2 level. Figure 27 details how it is internally arranged:

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DAP011/DAP011C

Figure 28. The Part is Reset when VCC Reaches 5.0 V

If for any reason Pin 2 level grows above 3.0 V, the part immediately stops pulsing and stays latched in this position until the user cycles down the power supply. The reset actually occurs if VCC drops below 5.0 V. Figure 28 details the operating diagrams in case of a fault. Please note the presence of RC time constant on the comparator output, aimed to filtering any spurious oscillations linked to an eventual noise presence. The typical value of this time constant is 20 ms.
Internal Reference Voltage

11 + Vref T UVLO Fault + C1 10 nF Rlower + Vlatch S Q Q R latched fault 20 ms time constant

A 5.0 V reference voltage is pinned out on Pin 11 and can source up to 5.0 mA. Figure 29 details how the reference voltage can be externally used, for instance to build a precise Over Temperature Protection (OTP) circuitry. This 5.0 V source is shut down during the startup phase and goes low as soon as VCC crosses VCC(min). It stays low during the double hiccup mode to keep the consumption to the lowest. We recommend to wire a 100 nF from this pin to ground in order to improve the noise immunity.

5 V reset

Figure 29. The Reference Voltage is used with the Latchoff Input to Trigger the Circuit in Presence of an OTP

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DAP011/DAP011C
Softstart and Fault Timer

The Speedking features an internal softstart circuit activated during the power on sequence (PON) but also during skip cycle to reduce the acoustical noise (see skip cycle section). As soon as VCC reaches VCCON, the peak

current is gradually increased from nearly zero up to the maximum clamping level (e.g. 1.0 V / Rsense). The peak current is clamped at 1.0 V / Rsense through the entire softstart period until the supply enters regulation. Figure 30 shows a typical startup shot.
VCCON 12 V

6.9V

10% of Timer or 500 ms at Skip Mode

Figure 30. Softstart is Activated During a Startup Sequence an OCP Condition (or During SkipCycle 500 ms Skip Ramp)
VtimSS +

+ softstart ended

Vtimfault +

+ fault

VDD Itim timer 3 skip, softstart IpFlag power on reset

Figure 31. Softstart is Activated During a Startup Sequence, an OCP Condition (or During SkipCycle 500 ms Skip Ramp)

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DAP011/DAP011C
To simplify the circuit architecture, the timer pin also shares the softstart comparator, as Figure 31 details. That means that the softstart is linked to the timer duration by a ratio of 0.1 or 10% roughly. If we select a 100 ms timer period, then the softstart duration will be 10 ms. Figure 32 details Pin 3 voltages during a softstart sequence or a skipcycle activity. The softstart capacitor is reset by either the softstart completion within the burst or by the skip comparator (500 ms Soft Skip Ramp) if the burst length is shorter than the softstart duration.

Figure 32. Softstart is Also Activated During Skip Cycle to Offer a Smooth Current Ramping Wave Shape

How to calculate the timer capacitor value? By simply apply V x C = I x t relationship. If we look at Figure 31, we can see that the timer is completed when Vpin3 reaches 4.0 V. If we have a 20 mA charging current and we want 90 ms of timer duration, then C is obtained by: C = I x t / V = 20 m x 100m / 4 = 500 nF. If we select a 0.47 mF, we endup with a final duration of 94 ms. The softstart being 10% of this value, we will see a softstart sequence of 9.4 ms.

Internal Ramp compensation

Ramp compensation is a known mean to cure subharmonic oscillations. These oscillations take place at half the switching frequency and occur only during Continuous Conduction Mode (CCM) with a dutycycle greater than 50%. To lower the current loop gain, one usually injects between 50 and 100% of the inductor downslope. Figure 33 depicts how internally the ramp is generated. Please note that the ramp signal will be disconnected from the CS pin, during the OFF time.

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DAP011/DAP011C
2V iCjit Jitter ON latch reset LEB CS Rsense + 4 Ctimer 20k Rcomp 2.iCjit + VCjitP VCjitV from FB setpoint + VDD Frequency modulation

0V

to clock circuit

Figure 34. An Internal Ramp is used to introduce Frequency Jittering on the Oscillator Sawtooth
Jitter ramp

Figure 33. Inserting a resistor in series with the current sense information brings ramp compensation and stabilizes the converter in CCM operation

In the Speedking, the oscillator ramp features a 2.0 V swing. If our clock operates at a 65 kHz pace, then the oscillator slope corresponds to a 130 mV/ms ramp. In our FLYBACK design, lets assume that our primary inductance Lp is 350 mH, and the SMPS delivers 12 V with a Np:Ns ratio of 1:0.1. The OFF time primary current slope is thus given by:
(Vout ) Vf) @ Np Lp
Ns

68.9 kHz

65kHz

+ 371 mAms or 37 mVms

(eq. 2) 61.1 kHz Adjustable Internal sawtooth

When projected over an Rsense of 0.1 W, for instance. If we select 75% of the downslope as the required amount of ramp compensation, then we shall inject 27 mV/ms. Our internal compensation being of 130 mV, the divider ratio (divratio) between Rcomp and the 20 kW is 0.207. A few lines of algebra to determine Rcomp:
20 k @ divratio (1 * divratio) + 5.2 kW
(eq. 3)

Figure 35. Modulation Effects on the Clock Signal by the Jittering Sawtooth Skipping Cycle Mode

Frequency Jittering

Frequency jittering is a method used to soften the EMI signature by spreading the energy in the vicinity of the main switching component. Speedking offers a 5% (6% for DAP011C) deviation of the nominal switching frequency. The sweep sawtooth is internally generated and modulates the clock up and down with an adjustable period. Figure 34 displays the internal arrangement around Pin 4. It is actually a I 2I generator, producing a clean 50% dutycycle sawtooth. If we take a 1.4 V swing on the jitter capacitor, then we calculate the needed value for a 3 ms period, or a 330 Hz modulation speed, again applying the V x C = I x t relationship. We need 1.5 ms to rampup and 1.5 ms to ramp down, therefore: C = 20u x 1.5m / 1.4 = 21 nF. If we select a 22 nF, then our modulation frequency will be around 325 Hz. Figure 35 shows the relationship between the jitter ramp and the frequency deviation.

Speedking automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, Pin 5 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a fixed determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses. The IC enters the socalled skip cycle mode, also named controlled burst operation. The default skip cycle current is internally frozen to 30% of the maximum peak current which is 350 mV/Rsense The power transfer now depends upon the width of the pulse bunches (Figure 38). Suppose we have the following component values: Primary Inductance (Lp) = 350 mH Switching Frequency (Fsw) = 65 kHz Ip skip = 600 mA (or 350 mV / Rsense) The theoretical power transfer is therefore:

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DAP011/DAP011C
1 @ Lp @ Ip 2Fsw + 4 W 2
(eq. 4)

If this IC enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power

transfer is: 4. 0.1 = 400 mW. To better understand how this skip cycle mode takes place, a look at the operation mode versus the FB level immediately gives the necessary insight:

FB Pin Voltage 5.0 V, FB Pin open 3.0 V upper dynamic range Normal Current Mode Operation

1.0 V Skipcycle Operation Ip min = 350 mV/Rsense

Figure 36.

When FB is above the skip cycle threshold (1.0 V by default), the peak current cannot exceed 1.0 V / Rsense. When the IC enters the skip cycle mode, the peak current cannot go below 1.0 V / 3 or around 350 mV / Rsense.

Figure 38 shows different values of pulse widths when the SMPS startstoskip cycles at different power levels:

Power P1

Power P2

Power P3

Figure 37. Output Pulses at Various Power Levels (X = 5 ms/div) P1 < P2 < P3

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DAP011/DAP011C
Max peak current

300.0M

200.0M 25% of max Ip 100.0M

315.4U

882.7U

1.450M

2.017M

2.585M

The skipcycle takes place at low peak currents which guaranties noise free operation Figure 38.

Figure 39. A Smooth Ramping Current in SkipCycle

As we have stated several times, the peak current in skipcycle will not immediately rampup to its default value. To limit the discontinuities in the transformer mechanical structure, and thus reduce the acoustic noise, the 500 ms softskip ramp will be activated in skip cycle. Figure 39 shows a typical shot, showing the peak current rampup. Since Pin 5 features an internal voltage source whose output impedance is 25 kW, it is possible to alter the default skip value. A simple arrangement consists in connecting a

resistor to ground in order to lower the setpoint. On the other hand, the setpoint can be increased, if necessary, by wiring a resistor to the reference voltage. Figure 40 portrays these options. Since Pin 5 internal impedance is 25 kW, it is simple to calculate the value of the resistor to decrease the Vskip level (1.0 V typically). Suppose we want to decrease it down to 800 mV. Then, the resistor to connect to Pin 5 is 0.8 / 40 m = 20 kW. To obtain a 20 kW from an original 25 kW value, we need to parallel a (20 k x 25 k) / (25 k20 k) = 100 kW.

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DAP011/DAP011C
Vref 11 to increase Vskip UVLO Fault VDD Iskip skip 5 to decrease Vskip Rskip Vskip + latch reset + Vref

VDD

RFB

FB 6

/3

peak setpoint

Figure 40. Due to Pin 4, it is Easy to Alter the Default Skip Level

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DAP011/DAP011C
PACKAGE DIMENSIONS

SOIC14 D SUFFIX CASE 751A03 ISSUE G

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019

A
14 8

P 7 PL 0.25 (0.010)
M

G C

R X 45 _

T
SEATING PLANE

D 14 PL 0.25 (0.010)

K
M

M
S

T B

DIM A B C D F G J K M P R

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DAP011/D