IJECT Vol. 2, SP-1, Dec.

2011

ISSN : 2230-7109(Online) | ISSN : 2230-9543(Print)

Carbon Nanotubes Field Effect Transistors: A Review

Dept. of Electronics and Instrumentation Engineering, Sir.C.R.R.College of Engineering, Eluru, India 2,3 Dept. of Instrument Technology, Andhra University, India 4 Dept. of Electronics and Communication Engineering, GITAM University, Vizag, India
The nanotube conducts essentially on its surface where all the chemical bonds are saturated and stable. In other words, there are no dangling bonds which form interface states. Therefore, there is no need for careful passivation of the interface between the nanotube channel and the gate dielectric, i.e. there is no equivalent of the silicon/silicon dioxide interface. The Schottkey barrier at the metal-nanotube contact is the active switching element in an intrinsic nanotube device. II. Type of CNTFET The field effect transistors made of carbon nanotubes so far can be classified into: A. Back-gated CNTFETs The earliest techniques for fabricating carbon nanotube (CNT) field-effect transistors involved pre-patterning parallel strips of metal across a silicon dioxide substrate, and then depositing the CNTs on top in a random pattern [1]. The semiconducting CNTs that happened to fall across two metal strips meet all the requirements necessary for a rudimentary field-effect transistor. One metal strip is the source contact while the other is the drain contact. The silicon oxide substrate can be used as the gate oxide and adding a metal contact on the back makes the semiconducting CNT gateable.

RamBabu.Busi, 2Swapna.P, 3Kalyan Babu.K, 4Y.Srinivasa Rao

Abstract Carbon Nanotube Field Effect Transistors (CNTFET) are promising nano-scaled devices for implementing high performance very dense and low power circuits. A Carbon Nanotube Field Effect Transistor refers to a FET that utilizes a single CNT or an array of CNTs as the channel material instead of bulk silicon in the traditional MOSFET structure. The core of a CNTFET is a carbon nanotube. In this paper, the review of CNTFETs is presented. The structure, operation and the characteristics of different types of CNTFETs have been discussed. The operation, dc characteristics of CNTFETs have been presented and analysis of the performance of various characteristics. Keywords CNTFET, Carbon nanotubes, Field effect transistors, Nanoelectronics, characteristics I. Introduction The first carbon nanotube field-effect transistors were reported in 1998. These were simple devices fabricated by depositing single-wall CNTs (synthesized by laser ablation) from solution onto oxidized Si wafers which had been prepattemed with gold or platinum electrodes. The electrodes served as source and drain, connected via the nanotube channel, and the doped Si substrate served as the gate. A schematic of such a device is shown in Fig.1. Clear p-type transistor action was observed, with gate voltage modulation of the drain current over several orders of magnitude. The devices displayed high on-state resistance of several MQ, low transconductance (-Ins) and no current saturation, and they required high gate voltages (several volts) to turn them on.

Fig. 2: Top and side view of carbon nanotubes deposited on a silicon oxide substrate pre-patterned with source and drain contacts. The types of back gate CNTFETs discussed so far have high contact resistances (1 M), which led to a low transconductance gm (=dI/dVG) of about 10 -9A/V. This large contact resistance results from the weak van der Waals coupling of the devices to the noble metal electrodes in the side-bonding configuration used. Here the SWNT is dispersed on top of the SiO2 film, and then source and drain electrodes made of transition metals compatible with silicon technology, such as Ti or Co, are fabricated on SWNT. Subsequent anneals at 400 C (Co) and, or at 820 C (Ti) in an inert ambient, form low resistance Co contacts or TiC contacts at the source and drain electrodes. Fig shows I-V characteristics of p-type CNTFET employing metallic Co or TiC contacts. B. Top-gated CNTFETs Eventually, researchers migrated from the back-gate approach to a more advanced top-gate fabrication process [2]. In the first step, single-walled carbon nanotubes are solution deposited onto a silicon oxide substrate. Individual nanotubes are then located via atomic force microscope or scanning electron microscope. After an individual tube is isolated, source and
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Fig. 1: Early CNTFET structure. Carbon nanotube field effect transistor (CNTFETs) uses semi conducting carbon nanotube as the channel. Both p-channel and n-channel devices can be made from nanotubes. The physical structure of CNTFETs is very similar to that of MOSFETs and their I-V characteristics and transfer characteristics are also very promising and they suggest that CNTFETs have the potential to be a successful replacement of MOSFETs in nanoscale electronics. Of course, there are some distinct properties of CNTFETs, such as: The carbon nanotube is one-dimensional, which greatly reduces the scattering probability. As a result the device may operate in ballistic regime.

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drain contacts are defined and patterned using high resolution electron beam lithography. A high temperature anneal step reduces the contact resistance by improving adhesion between the contacts and CNT. A thin top-gate dielectric is then deposited on top of the nanotube, either via evaporation or atomic layer deposition. Finally, the top gate contact is deposited on the gate dielectric, completing the process. Arrays of top-gated CNTFETs can be fabricated on the same wafer, since the gate contacts are electrically isolated from each other, unlike in the back-gated case. Also, due to the thinness of the gate dielectric, a larger electric field can be generated with respect to the nanotube using a lower gate voltage. These advantages mean top-gated devices are generally preferred over back-gated CNTFETs, despite their more complex fabrication process. C. Wrap-around gate CNTFETs Wrap-around gate CNTFETs, also known as gate-all-around CNTFETs were developed in 2008 [3], and are a further improvement upon the top-gate device geometry. In this device, instead of gating just the part of the CNT that is closer to the metal gate contact, the entire circumference of the nanotube is gated. This should ideally improve the electrical performance of the CNTFET, reducing leakage current and improving the device on/off ratio.

unexplored. So, other the most popular Back Gate and Top Gate structures, some of the researcher also proposed their own structure such as N-Type, AMBIPOLAR CNTFET, Vertical Gate, and etc. to prove the performance of the transistor is better after the channel of the transistor replaced by CNT. Below are several examples of the differences structure of CNTFET. A. N-Type and AMBIPOLAR CNTFET The capability to produce n-type transistors is important technologically, as it allows the fabrication of CNT-based complementary logic devices and circuits. A back gated n-type nanotube transistor can be obtained by doping the nanotube with potassium vapor. The mechanism is that electron transfer from adsorbed potassium atoms to the nanotube can shift the Fermi level of the tube from the valence-band edge to the conduction band edge, thus reverting the doping from p- to n-type. [8] Fig.5 shows the schematic of setup for doping and the resulting I-V characteristics.

Fig. 5: Schematic diagram of the potassium doping setup. An n-type top gate device as shown in Fig 3.9 (a) can be obtained by an in situ annealing step prior to the deposition of the gate dielectric film. Thermal treatment in an inert atmosphere drive off the adsorbed oxygen from the source and drain contact regions, shifts the Fermi level at the contacts and effectively lowers the barrier for electron injection, which results in an n-type behaviour. The oxide film protects the nanotube from the ambient gases and keeps the n-type devices stable. If a CNTFET with SiO2 protective film is annealed in vacuum or in inert atmosphere, the initial p-type device is gradually transformed into an ambipolar FET, i.e., the device, depending on the sign of the gate voltage VG, can operate as switches for electrons and holes. These ambipolar transistors are stable in air and show ohmic I-VDS curves in both the strong hole accumulation and inversion (electron accumulation) regimes. This behaviour suggests that the effective contact barriers for both electron and hole transport are very small. B. Multi-Wall CNTFET The complexity of structure of multi wall nanotube (MWNT) has discouraged their detailed study and use. In principle, each of its carbon shells can be metallic or semiconducting with different chiralities. Also, these shells can interact. It has been found that in MWNTs side-bonded to metal electrodes, effectively only the outer shell contributes to electrical transport. However, since the bandgap in semiconducting CNTs is inversely proportional to the tube diameter, only small diameters MWNTs are expected to exemplify FET characteristics at room temperature [9]. C. Vertical CNTFET This vertical CNTFET has been proposed by the researcher in Infineon Technology. The concept is totally difference compared to traditional MOSFET vertical gate configuration. Fig.6 showed the first draft of the Vertical CNTFET proposed by Infineon in year 2003 [10].

Fig. 3: Sheathed CNT Device fabrication begins by first wrapping CNTs in a gate dielectric and gate contact via atomic layer deposition [4]. These wrapped nanotubes are then solution-deposited on an insulating substrate, where the wrappings are partially etched off, exposing the ends of the nanotube. The source, drain, and gate contacts are then deposited onto the CNT ends and the metallic outer gate wrapping. D. Suspended CNTFETs CNTFET device geometry involves suspending the nanotube over a trench to reduce contact with the substrate and gate oxide [5]. This technique has the advantage of reduced scattering at the CNT-substrate interface, improving device performance [5] [6,7]. There are many methods used to fabricate suspended CNTFETs, ranging from growing them over trenches using catalyst particles [5], transferring them onto a substrate and then under-etching the dielectric beneath [7], and transferprinting onto a trenched substrate [6].

Fig. 4: Suspended CNTFET device. III. Other CNTFET The CNTFET technology is at an early stage; devices structures are still primitive and the devices physic still relatively
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Fig. 6: Vertical CNTFET IV. CHARCTERISTICS OF CNTFETs The drain I-V characteristics in 2D are shown in fig 7. The saturation current at VGS = 0.5 V is around 6 A, which is not inconsistent with values emerging from recent experimental work [9].

Fig. 9: Output Characteristics for a p-type top gated CNTFET As the voltage across the gate and the source of SB-CNTFET is increased from 0 volts, the Fermi level of the nanotube moves closer to the conduction band. This band lowering effect causes barriers to develop at nanotube-metal junctions. The electrons which have enough potential will cross the barrier and flow into the tube, causing leakage current. In our model, the main source of leakage is the thermionic current. When a positive voltage is applied on the drain, the barrier spike begins to progressively diminish at that end of the channel. The barrier thickness, as seen by the charge carriers, begins to reduce too. Consequently, the electrons induced on the channel can now enter the drain metal by tunnelling through the barrier while those carriers with sufficient thermal energy can jump over the barrier. The limiting value of current through the nanotube is described by the thermionic current component. See from the figure, that when no gate voltage is applied, for the case of Vgs = 0 in Fig. 8, the current increases linearly with Vds. This is attributed to the linear dependence of the thermionic current on the drain voltage. The application of a positive gate voltage induces heavy charge on the channel. It can be seen from the same figure that the current due to charge, tunnelling through the barrier at the drain end, is significantly greater than the thermionic current component. The transfer characteristics in Fig. 9 reflect a similar scenario. For an applied drain voltage, the current increases almost quadratically as soon as a gate voltage is applied. The two drain and transfer characteristics show that the current .owing through the device is very sensitive to the drain voltage and is largely controlled by manipulating the barrier height at the contacts.

Fig. 7: Drain current-voltage characteristics of planar CNTFET. Drain I-V characteristics exhibited dependence of saturation drain current on temperature. When CNTFET is cooled, drain saturation currents were lightly decreased. The current voltage curve can be divided into two regions: linear and saturation. Drain current in the linear region of CNTFET can be described as follows:

Or

Where Kn is conductance of CNTFET, W is the width of CNTFET, L is the length of CNTFET, is mobility of carriers, Cox is gate capacitance. We can also obtain saturation current of CNTFET by replacing Vds(sat) = Vgs VT. Then the expression of saturation current of CNTFET can be written:

Fig. 10: CNTFET sub threshold Drain characteristics

A. I-V characteristics

Fig. 11: CNTFET sub threshold Transfer characteristics We can see from Fig. 10 that for a given Vgs, the current saturates at the region, i.e., when the applied Vds generate the transistor I-V characteristics and their dependence on the gate dielectric thickness and nature of the insulator barrier height. At this point the barrier is entirely suppressed and there is maximum current flow through the channel. Fig. 11 shows an almost linear increase in the current as a function of the gate voltage. The onset of current saturation as a function of drain voltage is expressed very clearly here. The plot consists of 5
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Fig. 8: Output characteristics of n-type CNTFET

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curves for Vds ranging from 0 1 V. However, while there is a marked increase in the current for an increase of Vds from 0.1V to 0.3V, beyond this limit, all the other curves representing the higher values of Vds are almost merged. The electron current beyond this point is independent of Vds. V. Conclusion Carbon Nanotubes are considered as the most promising carbon nanostructure material is realizing the nano-electronic transistors back in year 1991. The understanding of carbon nanotube transistor is evolving and the performance of the transistor is improving very rapidly. CNTFET devices present a bright future and promise to sustain FET scaling and Moores Law should their practical and manufacturing problems be overcome.The I-V characteristics of top gated CNTFET are also described. The main analysis is studies on the I-V characteristics of the CNTFET. These top gated CNTFET devices exhibit excellent electrical characteristics. However, as was mentioned above, the control parameter of the properties of the carbon nanotube will change the drain current directly and the channel length does not impacting the performance much. A multitude of oxide can be placed on the nanotube and thus, many high-k dielectrics can be incorporated into CNTFET to reduce the tunneling current. The large potential of CNTFET transistor to semiconductor industry and microelectronic system due the large Ion: Ioff , high current drive and other special properties of carbon nanotube. However, the carbon nanotube field still in the early stage and the technology for reducing the process variation should be focused for this moment. References [1] Martel, R.; Schmidt, T.; Shea, H. R.; Hertel, T.; Avouris, Ph., "Single- and multi-wall carbon nanotube field-effect transistors". Applied Physics Letters 73, 1998. [2] Wind, S. J.; Appenzeller, J.; Martel, R.; Derycke, V.; Avouris, Ph., "Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes". Applied Physics Letters 80: 3817, 2002. [3] Chen, Zhihong; Farmer, Damon; Xu, Sheng; Gordon, Roy; Avouris, Phaedon; Appenzeller, Joerg., "Externally Assembled Gate-All-Around Carbon Nanotube Field-Effect Transistor". IEEE Electron Device Letters 29: 183, 2008. [4] Farmer, DB; Gordon, RG., "Atomic layer deposition on suspended single-walled carbon nanotubes via gasphase noncovalent fictionalization". Nano letters 6 (4): 699703M, 2006. [5] Cao, J; Wang, Q; Dai, H., "Electron transport in very clean, as-grown suspended carbon nanotubes". Nature materials 4 (10): 7459, 2005 [6] Sangwan, V. K.; Ballarotto, V. W.; Fuhrer, M. S.; Williams, E. D., "Facile fabrication of suspended as-grown carbon nanotube devices". Applied Physics Letters 93: 113112. FLEXChip Signal Processor (MC68175/D), Motorola, 1996, 2008. [7] Lin, Yu-Ming; Tsang, James C; Freitag, Marcus; Avouris, Phaedon, "Impact of oxide substrate on electrical and optical properties of carbon nanotube devices". Nanotechnology 18: 295202, 2007. [8] R. Martel et al., Ambipolar Electrical Transport in Semiconducting Single-Wall Carbon Nanotubes, Phys. Rev. Lett. (2001). [9] R. Martel, T. Schmidt, H.R. Shea, T. Hertel, Ph. Avouris,
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Single and Multi-wall Carbon Nanotube Field-effect Transistors, Applied Physics Letters, October 1998. [10] S. J. Wind et al., Vertical scaling of carbon Nanotube Field-effect transistors using top gate electrodes, Applied Physics Letters, May 2002.

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Dr. Y.Srinivasa Rao received his Ph.D in Electrical Communication Engineering from Indian Institute of Science, Bangalore in 1998. At present, he is an Senior Associate Professor and BOS Member in Instrument Technology Department, AU College of Engineering (A), Andhra University, Visakhapatnam, AP, India. He is having 15+years of teaching and research experience and published more than 65 research papers in the International journals and presented few of them in the International Conferences. He was in Eritrea, N.E Africa for one year on academic assignment. He had given several Invited Talks and Guest Lectures at several International and National Conferences for the last few years. He will be an Visiting Researcher, EEE Department, Nanyang Technological University, Singapore in 2012. He had received Emerald Literati Network 2008 Outstanding Paper Award (UK), three Best Paper Awards (one in 2011 and twice in 2007), Vignan Pratibha Award 2006 from Andhra University and selected as Science Researcher for Asia Pacific region in 2005 by UNESCO and Australian Expert group in Industry Studies (AEGIS) at the University of Western Sydney (UWS) and received Young Scientist Award from Department of Science and Technology, Govt. of India in 2002. He is acting as Reviewer for several International and National Journals. His present research focuses on Carbon Nanotube Electronics including Modeling, Design and Simulation, Fabrication of Ambipolar Carbon Nanotube Transistors including Ambipolar electronic devices and also on Fabrication, Characterization, Modeling, Trimming and reliability studies of polymer Thick Film Resistors, Nanobiosensors and Flexible Electronics using Carbon Nanotubes. He is a life member of IEEE, IETE, LISTE and member of IMAPS (USA and India).

Ram Babu. Busi received his M.Tech in Electrical and Instrumentation Engineering from Punjab Technical University in 2007. At present, he is an Assistant Professor in Electronics and Instrumentation Department, Sir.C.R.Reddy.College of Engineering, Eluru, Andhra University, India. He is having 4+years of teaching and research experience and presented four research papers in the National Conferences. His present research focuses on Carbon Nanotube Electronics including modelling, Simulation Design and Fabrication of Carbon Nanotube on flexible Electronic devices. He is a life member of ISTE. Swapna Peravali received her B.Tech degree in Electronics and Instrumentation Engineering from Nagarjuna University, Guntur, Andhra Pradesh in 2000 and M.Tech degree in Instrumentation and Control from National Institute of Technology, Calicut Kerala in 2002. She is currently working with A.U. College of Engineering (A), Andhra University, Visakhapatnam, Andhra Pradesh. Her research interest includes the design, simulation, fabrication and characterization of Ambipolar CNTFET based devices and circuits. K. Kalyan Babu received his M.Tech degree in Electronics and Instuentation from Andhra University. His research interests are nano electronics and nano bio-sensors.

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