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    Parul Institute of Engineering and Technology, Limda Electronics & Communication Engineering Department

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    Hardiik Patel
    The document describes the design and simulation of a 4x1 multiplexer using different modeling styles in VHDL, including behavioral modeling using case, if-else, and select statements, as well as data flow modeling using logic expressions. Five different VHDL code examples are provided to demonstrate multiplexing 4 input lines based on the values of 2 select lines using various language constructs.

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    Parul Institute of Engineering and Technology, Limda Electronics & Communication Engineering Department

    Uploaded by

    Hardiik Patel
    25 views5 pages
    The document describes the design and simulation of a 4x1 multiplexer using different modeling styles in VHDL, including behavioral modeling using case, if-else, and select statements, as well as data flow modeling using logic expressions. Five different VHDL code examples are provided to demonstrate multiplexing 4 input lines based on the values of 2 select lines using various language constructs.

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    The document describes the design and simulation of a 4x1 multiplexer using different modeling styles in VHDL, including behavioral modeling using case, if-else, and select statements, as well as data flow modeling using logic expressions. Five different VHDL code examples are provided to demonstrate multiplexing 4 input lines based on the values of 2 select lines using various language constructs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    25 views5 pages

    Parul Institute of Engineering and Technology, Limda Electronics & Communication Engineering Department

    Uploaded by

    Hardiik Patel
    The document describes the design and simulation of a 4x1 multiplexer using different modeling styles in VHDL, including behavioral modeling using case, if-else, and select statements, as well as data flow modeling using logic expressions. Five different VHDL code examples are provided to demonstrate multiplexing 4 input lines based on the values of 2 select lines using various language constructs.

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    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 5

    PARUL INSTITUTE OF ENGINEERING AND TECHNOLOGY, LIMDA ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

    Class : 6th Sem Practical No. : 5 Date :

    Subject : VLSI Subject Code : EC - 605

    --Design & Simulation of Multiplexer Using various modelling styles. 1) CASE statement .(Behavioral style) -- Company: -- Engineer: -- Create Date: 22:30:44 03/11/2009 -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- Dependencies: -- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- VHDL codes for Behavioural Modelling of 4x1 Mux -- Sequencial digital circuits are normally simulated using behavioural modelling. library ieee; use ieee.std_logic_1164.all; entity mux4x1_beh is port ( i: in std_logic_vector (3 downto 0); s: in std_logic_vector (1 downto 0); -- s is array for two select lines y: out std_logic); end mux4x1_beh; architecture mux_behaviour of mux4x1_beh is begin process(i,s) begin case s is when "00"=>y<=i(0); -- selects input line 0

    when "01"=>y<=i(1); -- selects input line 1 when "10"=>y<=i(2); -- selects input line 2 when "11"=>y<=i(3); -- selects input line 3 when others => null; end case; end process; end mux_behaviour; 2) LOGIC EXPRESSION statement (Data Flow Style) -- Company: -- Engineer: --- Create Date: 22:30:44 03/11/2009 -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- VHDL codes for Behavioural Modelling of 4x1 Mux -- Sequencial digital circuits are normally simulated using behavioural modelling. library ieee; use ieee.std_logic_1164.all; entity mux4x1_beh is port ( i: in std_logic_vector (3 downto 0); s: in std_logic_vector (1 downto 0); -- s is array for two select lines y: out std_logic); end mux4x1_beh; architecture mux_behaviour of mux4x1_beh is begin y <= ((not s(1)) and (not s(0)) and i(0)) or ((not s(1)) and s(0) and i(1)) or

    ( s(1) and (not s(0)) and i(2)) or (s(1) and s(0) and i(3)); end mux_behaviour; 3) IF statement.(Behavioral style) -- Company: -- Engineer: --- Create Date: 22:30:44 03/11/2009 -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux4x1_beh is port ( i: in std_logic_vector (3 downto 0); s: in std_logic_vector (1 downto 0); -- s is array for two select lines y: out std_logic); end mux4x1_beh; architecture mux_behaviour of mux4x1_beh is begin process(i,s) begin if (s=00) then y<= i(0); elsif (s=01) then y<= i(1); elsif (s=10) then y<= i(2); elsif (s=11) then

    y<= i(3); end if; end process; end mux_behaviour; 4) With select statement. -- Company: -- Engineer: --- Create Date: 22:30:44 03/11/2009 -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux4x1_beh is port ( i: in std_logic_vector (3 downto 0); s: in std_logic_vector (1 downto 0); -- s is array for two select lines y: out std_logic); end mux4x1_beh; architecture mux_behaviour of mux4x1_beh is begin with s select y<= i(0) when 00, i(1) when 01, i(2) when 10, i(3) when 11, 0 when others; End mux_behaviour;

    5)When else statement -- Company: -- Engineer: --- Create Date: 22:30:44 03/11/2009 -- Design Name: -- Module Name: -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux4x1_beh is port ( i: in std_logic_vector (3 downto 0); s: in std_logic_vector (1 downto 0); -- s is array for two select lines y: out std_logic); end mux4x1_beh; architecture mux_behaviour of mux4x1_beh is begin y<= i(0) when s="00" else i(1) when s="01" else i(2) when s="10" else i(3) when s="11" else '0' ; End mux_behaviour;

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