International Journal of Advances in Science and Technology, Vol. 3, No.

3, 2011

Implementation of UART Using SystemC and FPGA based Co-Design Methodology

B. Murali Krishna1 and Dr. Fazal Noorbasha2
Department of ECE, KL University, Vaddeswaram, Guntur (Dist.), AP, India - 522 502 2 E-mail: [email protected] [email protected]

Abstract
In digital system design methodologies synthesis methods are important elements in platformbased design methodologies. It takes hardware/software (HW/SW) co-design and high level design reuse as keys to SoCs design. A new system-level approach is needed to incorporate reconfigurability in IP-integration design flow, in order to speed up the designers productivity. SystemC, HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. HDL is used as FPGA design and logic verification. As a case study, UART architectures are implemented in SystemC, and plugged into a Virtex-II Pro platform for co-simulation. It also presents market-oriented views and introduces synthesis tools to support the co-design methodology.

Keywords: SystemC, HDL, platform-based design, Virtex-II Pro, UART, FPGA 1. Introduction
This co-design platform enables early system functionality verification, as well as new algorithm exploration before the final implementation prototype. It can be used to validate the behavior for both the hardware and the software modules of the embedded SoC, as well as the interaction between them with timed/cycle-accuracy [1]. By having an early simulation model, it permits the evaluation of the complete system at an early stage of the design flow. This can avoid extensive redesigning, which can contribute to significantly long design time and incur high design cost, and furthermore, the result usually ends up with sub-optimal designs. The platform is independent of any vendor specific tools. This SystemC-based design framework aims to facilitate architecture exploration that assists the system designer in finding the best HW/SW dichotomy [2-3]. Another key advantage is the speed of simulation at the system level is significantly faster than RTL simulation of the whole system. A recent trend has been to take the coarse-grained architectural approach a step further by combining the logic blocks and interconnects of traditional FPGAs with embedded microprocessors and related peripherals to form a complete "system on a programmable chip. Such hybrid technologies can be found in the Xilinx Virtex-II PRO and Virtex-4 devices, which include one or more PowerPC processors embedded within the FPGA's logic fabric [4-5]. To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP suppliers. In this present work to develop UART based designs there is necessity to develop VHDL (or) Verilog code for Transmitter, Receiver, and Baud Rate Generator, in order to develop the required modules, to simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. For High end system using IP Cores selection with Xilinx Platform Studio-Embedded Development Kit. Using this method design can completed within specific time. Low end designs use VHDL using Xilinx ISE. Integrating both the designs make a single .bit file observe it on the Virtex II Pro FPGA Board [7].

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2. Requirements of System-Level Design

2.1 The PowerPC405 Block The processor block on the Virtex-II Pro contains the PowerPC405 core, logic to interface the core with its surrounding resources, and general-purpose routing resources. There is one or two processor blocks present depending on the specific FPGA used. The PowerPC405 on the Virtex-II Pro is a 0.13m implementation of IBMs PowerPC 405D4 core that is engineered for low power consumption at a clock speed of up to 300 MHz. This embedded core implements the PowerPC user instruction set architecture (UISA), user-level registers, programming model, data types and addressing modes for 32bit fixed-point operations [6]. Floating-point calculations are not supported in hardware, but can be emulated using software. The two interfaces that allow the processor block to communicate data to and from the FPGA fabric are the PLB and OCM interfaces. The PowerPC405 has separate instruction and data cache units, each 16 k bytes in size. The Figure 1 shows the block diagram of PowerPC 405 Design which is shown above. Each cache unit includes a processor local bus (PLB) master, cache arrays, and a cache controller.

Figure 1. Power PC Block Diagram

2.2 On-Chip Peripheral Bus (OPB) The PowerPC405 uses the OPB to communicate with low speed devices, such as a universal asynchronous receiver transmitter (UART), On-Chip Peripheral; GPIO It uses PLB to communicate with high speed devices such as High Speed Peripheral, Memory Controller, and PCI 64/66. The OPB is a fully synchronous 32-bit data bus that functions independently of the PLB on a different level of the bus hierarchy. The OPB does not interface directly to the PowerPC405 core. Instead an OPB to PLB Bridge provides the interface between the two levels of hierarchy. Therefore, if an OPB master needs to communicate with the processor, it must do so by using the OPB to PLB Bridge to generate the appropriate transaction on the PLB. Similarly, if the processor wants to communicate with a device on the OPB, it must do so by using the PLB to OPB Bridge to generate the appropriate transaction on the OPB. The PowerPC block includes caches for instructions (I-Cache) and data (D-Cache). Note that these caches are usable only with data transferred over the PLB, and not with data transferred from the OCM. The caches can be enabled or disabled under programming control. 2.3 Processor Local Bus (PLB) The PLB is designed to be used by the processor to service peripherals that require high performance. The PLB is a fully synchronous 64-bit data bus that supports read and write transfers

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International Journal of Advances in Science and Technology, Vol. 3, No.3, 2011 between master and slave devices. Each PLB master is attached to the PLB through separate address, read-data, and write-data buses. PLB slaves are attached to the PLB through shared but decoupled address, read-data, and write-data buses and a plurality of transfer and status control signals. Devices that wish to communicate over the PLB must first contact the PLB arbiter [8]. After considering the activity level on the bus, the PLB arbiter will either grant or deny the device access to the bus.

3. Design Methodology and Performance Analysis of System

3.1 Xilinx Platform Studio Xilinx Platform Studio is a tool integrated in Xilinx ISE 10.1 which provides user defined programming, creating the Soft IP Cores for our designs rather than Hard IP Cores which available external to the Virtex II Pro board. The Xilinx Platform Studio is included with two modules; one module is Xilinx Platform Studio -Embedded Development Kit (XPS EDK), another module is one Xilinx Platform Studio - Software Development Kit (XPS SDK). 3.2 Embedded Development Kit The Xilinx Embedded Development Kit (EDK) is a suite of tools and IP that enables you to design a complete embedded processor system for implementation in a Xilinx Field Programmable Gate Array (FPGA) device. In this EDK we can develop the software code required for our application. 3.3 Software Development Kit The Xilinx Soft Development Kit (SDK) is a suite of tools that enables you to design a software application for selected Soft IP Cores in the Xilinx Embedded Development Kit (EDK).The software application can be written in a C or C++ then the complete embedded processor system for our application will be completed, else debug & download the bit file the FPGA then FPGA behaves like processor implemented on it in a Xilinx Field Programmable Gate Array (FPGA) device.

4. Hardware/Software Co-Synthesis Platform

Hardware-Software co-simulation environment proposed in this work is categorized into Top-Down and Bottom-Up designs. We concentrated on a Top-Down design methodology.

Figure 2. Element Stages of (a) ELF File (b) Net Lists (c) Bit File generation The hardware portion of present Test Drive system uses the MHS file to describe the hardware elements in a high-level form. The XPS creates an analogous software system description in the Microprocessor Software Specification (MSS) file. The MSS file, together with our software applications, are the principal source files representing the software elements of our embedded system. This collection of files, used in conjunction with EDK installed libraries, drivers, and any custom libraries. The compiled software routines are available as Executable and Linkable Format (ELF) file. The ELF file is the binary ones and zeros that are run on the processor hardware. Figure2 (a) shows the files and flow stages that generate the ELF file.

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International Journal of Advances in Science and Technology, Vol. 3, No.3, 2011 Earlier we were prompted to select the Hardware > Generate Netlist menu item. This command causes the XPS Platform Generator (Platgen) utility to read the design platform information contained in the Microprocessor Hardware Specification (MHS) file, along with the IP attribute settings available from the respective Microprocessor Peripheral Definition (MPD) files. The output files from Platgen are Hardware Description Language (HDL) files, which can be found at <project name>\hdl\. More information about the MPD file can be found in the Platform Specification Format. When we select Hardware > Generate Netlist, the Xilinx Synthesizer Technology (XST) synthesizes these HDL design files to produce the IP Netlist (NGC) files, as shown in Figure 2(b). For our general reference, the resulting NGC files reside at <project name>\implementation. There is no need to change these files. ISE uses the NGC netlist files during design implementation, which occurs when we invoke the Generate Programming File from the ISE Project Navigator. When we double-click Generate Program File, the following flow takes place, illustrated in Figure 2(c) the NGC files and system constraints are processed through the remaining ISE tools (NGD Build, MAP, PAR, and TRACE) and BITGEN from the ISE Project Navigator GUI.

5. Embedded System Bit Stream Generation

To boot up an embedded processor system, both hardware and software system components must be downloaded to the FPGA and program memory, respectively. Figure 3 shows the elements and stages of generating the embedded system Bitstream, which is executed by selecting Configuration >Bitstream Settings in EDK. During the prototype or development phase, we have download the hardware Bitstream and software Executable and Linkable Format (ELF) file images by connecting a JTAG cable from our host computer to the JTAG port on our development board. The Device Configuration > Download Bitstream menu command in SDK programs the FPGA with the Bitstream. For software downloading, we have initialized software into the Bitstream and dumped inside FPGA internal block RAM (BRAM) memory. Also we can use the software debug tools, such as the XPS Software Development Kit (SDK), to download our program to the FPGA board.

Figure 3. Generating of Embedded System Bit Stream

6. Analysis of UART Co-Design

Serial data is transmitted via its serial port. In contrast to parallel communication, these peripheral devices communicate using a serial bit stream protocol (where data is sent one bit at a time). The serial port is usually connected to UART, an integrated circuit which handles the conversion between serial and parallel data. Figure 4 shows how the UART receives a byte of parallel data and converts it to a sequence of voltage to represent 0s and 1s on a single wire (serial). This conversion is performed by a peripheral device called a modem (modulator/demodulator).

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Figure 4. Block Diagram of Serial Data Transmitter and Receiver (UART) The high performance and low power circuit implementation is a big challenge for the system Codesign. The UART is designed in Xilinx (Spartan-3E) FPGA family. Leakage current in digital logic is now the primary challenge for FPGAs as process geometries decrease. Static power consumption rises largely because of increases in various sources of leakage current. The Xilinx (HDL) advanced synthesis report and the total device utilization for this device are shown in the Table 1. We observed the power analysis for this device, total quiescent power is 0.068W, total dynamic power is 0.000W and total power is 0.068W. The operating voltage is 1.5V at the temperature range from -20OC to 85OC. Figure 5(a) and (b) shows the RTL and Floor Plan view of UART design. Figure 6(a), (b) and (c) shows the UART Technology Schematic, UART XPS generated block diagram and UART Result observation on FPGA Kit. Table 1. Xilinx (HDL) Advanced Synthesis Report Device Name
DIFFM DIFFS SLICE RAMB PPC405 DCM BUFGMUX JTAGPPC

X0Y0
4 4 14 -

X0Y1
164 16 -

Clock Regions [GCM is 1] X0Y2 X0Y3 X1Y0 X1Y1

128 4 1 2 13 1 2 1 26 179 3 -

X1Y2
108 2 1 -

X1Y3
1 32 16 1 1

a
Figure 5. UART (a) RTL view (b) Floor Plan View

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Figure 6. (a)UART Technology Schematic (b) XPS generated block diagram (c) Result on FPGA Kit

7. Conclusions
This paper shows that the performance of an application that uses the embedded processor on the Xilinx Virtex family of chips is strongly affected by the types of interfaces that are chosen to communicate data between the processor and the fabric of the FPGA. UART is a soft IP core available in Virtex FPGA fabric connected through PowerPC processor with OPB & PLB buses. Both the OCM and the PLB interfaces can deliver better performance than using only one type of interface. The OCM and PLB are both capable of providing high performance if used appropriately. The result will be designs that make use of the embedded PowerPCs and exhibit good performance. In this paper we presented a design methodology of UART, Timers and other GPIO peripherals are used efficiently. We have developed HDL code for transmitter, receiver, and baud rate generator for UART. Then specific application can be designed through UART. Similarly Timers and other peripherals used utilized simultaneously. To develop a HDL code for the above designs is more complex and time consuming process. To simplify the design of complex systems, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process.

References
[1] Virtex-II Pro and Virtex-II Pro x FPGA User Guide, T. X. Corp., Mar.2005 [Online]. Available: http://direct.xilinx.com/bvdocs/userguides/ug012.pdf, last accessed May 2007 [2] G. Brebner, Single-chip gigabit mixed-version IP router on a Virtex-II Pro, in Proc. 10th Annu. IEEE Symp. Field-Programmable Custom Computing Machines, Apr. 2002, pp. 3544. [3] J. Ou and V. K. Prasanna, A methodology for energy efficient application synthesis using platform FPGAs, in Proc. Eng. Reconfigurable Systems and Algorithms (ERSA04), T. P. Plaks, Ed. Athens, GA: CSREA Press, 2004, pp. 280283. [4] K. Lund, PLB vs. OCM Comparison Using the Packet Processor Software. October 2004 [Online]. Available:http://direct.xilinx.com/bvdocs/appnotes/xapp644.pdf, last accessed May 2007

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International Journal of Advances in Science and Technology, Vol. 3, No.3, 2011 [5] PowerPC Block Reference Guide, T. X. Corp., Jul.2005 [Online]. Available: http: //direct.xilinx.com/ bvdocs/userguides/ug018.pdf, last accessed May 2007 [6] M. Cummings and S. Haruyama, FPGA in the software radio, IEEE Commun. Mag., vol. 37, no. 2, pp. 108112, Feb. 1999. [7] S. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, Field Programmable Gate Arrays. Boston, MA: Kluwer Academic, 1992. [8] Programmable Gate Array Data Book, Xilinx, Inc., San Jose, CA, 1991.

B.Muralikrishna was born on 31st August 1986. He received his, Diploma degree in Electronics & Communication Engineering from SIR C.R.Reddy Polytechnic, Eluru, A.P., Affiliated to the SBTE &T in 2004, B.Tech degree in Electronics & Communications Engineering from Nimra College of Engineering & Technology, Vijayawada, A.P., India, Affiliated to the JNTU Hyderabad in 2007, M.Tech degree in VLSI Design from GITAM University, Vishakhapatnam, A.P India, in 2010. Presently he is working as Assistant Professor, Department of ECE in K.L.University, Guntur, AP, India. He had one year experience in Viraj IT solutions PVT Ltd. as Software Engineer during 2007-2008. Where he has been engaged in the teaching, research and development of Low-Power VLSI, Design for Testability, CPLDs & FPGA Architectures, Embedded Systems and Fault Tolerance. He has published over 3 International and 2 National conferences. Dr. Fazal Noorbasha was born on 29th April 1982. He received his, B.Sc. degree in Electronics Sciences from BCAS College, Bapatla, Guntur, A.P., Affiliated to the Acharya Nagarjuna University, Guntur, Andhra Pradesh, India, in 2003, M.Sc. degree in Electronics Sciences from the Dr. HariSingh Gour University, Sagar, Madhya Pradesh, India, in 2006, M.Tech. Degree in VLSI Technology, from the North Maharashtra University, Jalgaon, Maharashtra, INDIA in 2008, and Ph.D. (VLSI) from Department Of Physics and Electronics, Dr. HariSingh Gour Central University, Sagar, Madhya Pradesh, India, in 2011. Presently he is working as a Assistant Professor, Department of Electronics and Communication Engineering, KL University, Guntur, Andhra Pradesh, India, where he has been engaged in the teaching, research and development of Low-power, High-speed CMOS VLSI SoC, Memory Processors LSIs, Digital Image Processing, Embedded Systems and Nanotechnology. He is a Scientific and Technical Committee & Editorial Review Board member in Engineering and Applied Sciences of World Academy of Science Engineering and Technology (WASET) and Member of International Association of Engineers (IAENG). He has published over 20 Science and Technical papers in various International and National reputed journals and conferences.

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