PARCIAL
PARCIAL
PARCIAL
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-- Company:
-- Engineer:
--
-- Design Name:
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decodificador is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
E : in STD_LOGIC;
D3 : out STD_LOGIC;
D2 : out STD_LOGIC;
D1 : out STD_LOGIC;
D0 : out STD_LOGIC);
end Decodificador;
begin
end Funcional;
Ligaduras:
Inciso b)
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-- Company:
-- Engineer:
--
-- Design Name:
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity DECODI is
Port ( a0 : in STD_LOGIC;
b0 : in STD_LOGIC;
E0 : in STD_LOGIC;
c : in STD_LOGIC;
end DECODI;
architecture fun of DECODI is
begin
port map (a => a0, b => b0, E => E0, D0 => s0(0), D1=> s1(0) , D2 => s2(0),
D3 => s3(0));
port map ( a => a0, b => b0, E => E0, D0 => s0(1), D1 => s1(1), D2 => s2(1),D3 => s3(1));
end fun;
Ligaduras:
PROBLEMA 2
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-- Company:
-- Engineer:
--
-- Design Name:
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity Codi is
-- entity Desple2 is
reset0: std_logic;
end Codi;
begin
port map (salida => sum, clk => clk0, reset => reset0);
end Func;