PARCIAL

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Primer ejercicio:

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-- Company:

-- Engineer:

--

-- Create Date: 05.09.2023 10:29:43

-- Design Name:

-- Module Name: Decodificador - Use

-- Project Name:

-- Target Devices:

-- Tool Versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Decodificador is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

E : in STD_LOGIC;

D3 : out STD_LOGIC;

D2 : out STD_LOGIC;

D1 : out STD_LOGIC;

D0 : out STD_LOGIC);

end Decodificador;

architecture Funcional of Decodificador is

begin

D3 <= (b and E) or (a and E);

D2 <= (a and E) or ((not b)and E);

D1 <= (E and (not a)) or (b and E);

D0 <= (E and(not a)) or (E and (not b));

end Funcional;

Ligaduras:

set_property PACKAGE_PIN R2 [get_ports a]

set_property PACKAGE_PIN T1 [get_ports b]

set_property PACKAGE_PIN T17 [get_ports E]


set_property PACKAGE_PIN L1 [get_ports D0]

set_property PACKAGE_PIN P1 [get_ports D1]

set_property PACKAGE_PIN N3 [get_ports D2]

set_property PACKAGE_PIN P3 [get_ports D3]

set_property IOSTANDARD LVTTL [get_ports a]

set_property IOSTANDARD LVTTL [get_ports b]

set_property IOSTANDARD LVTTL [get_ports E]

set_property IOSTANDARD LVTTL [get_ports D0]

set_property IOSTANDARD LVTTL [get_ports D1]

set_property IOSTANDARD LVTTL [get_ports D2]

set_property IOSTANDARD LVTTL [get_ports D3]

Inciso b)

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 05.09.2023 11:30:27

-- Design Name:

-- Module Name: DECODI - fun

-- Project Name:

-- Target Devices:

-- Tool Versions:

-- Description:

--

-- Dependencies:

--

-- Revision:
-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity DECODI is

Port ( a0 : in STD_LOGIC;

b0 : in STD_LOGIC;

E0 : in STD_LOGIC;

c : in STD_LOGIC;

D00 : out STD_LOGIC_VECTOR (0 TO 1);

D11 : out STD_LOGIC_VECTOR (0 TO 1);

D22 : out STD_LOGIC_VECTOR (0 TO 1);

D33 : out STD_LOGIC_VECTOR (0 TO 1));

end DECODI;
architecture fun of DECODI is

signal s0,s1,s2,s3: std_logic_vector (0 to 1);

begin

Decod_bit0_unit: entity work.Decodificador(Funcional)

port map (a => a0, b => b0, E => E0, D0 => s0(0), D1=> s1(0) , D2 => s2(0),

D3 => s3(0));

Decod_bit1_unit: entity work.Decodificador(Funcional)

port map ( a => a0, b => b0, E => E0, D0 => s0(1), D1 => s1(1), D2 => s2(1),D3 => s3(1));

D00(0) <= c and s0(0);

D00(1) <= c and s0(1);

D11(0) <= c and s1(0);

D11(1) <= c and s1(1);

D22(0) <= c and s2(0);

D22(1) <= c and s2(1);

D33(0) <= c and s3(0);

D33(1) <= c and s3(1);

end fun;

Ligaduras:

set_property PACKAGE_PIN R2 [get_ports a0]

set_property PACKAGE_PIN T17 [get_ports E0]

set_property PACKAGE_PIN T1 [get_ports b0]

set_property PACKAGE_PIN U1 [get_ports c]

set_property PACKAGE_PIN L1 [get_ports D00[0]]

set_property PACKAGE_PIN P1 [get_ports D00[1]]

set_property PACKAGE_PIN N3 [get_ports D11[0]]

set_property PACKAGE_PIN P3 [get_ports D11[1]]


set_property PACKAGE_PIN U3 [get_ports D22[0]]

set_property PACKAGE_PIN W3 [get_ports D22[1]]

set_property PACKAGE_PIN V3 [get_ports D33[0]]

set_property PACKAGE_PIN V13 [get_ports D33[1]]

set_property IOSTANDARD LVTTL [get_ports a0]

set_property IOSTANDARD LVTTL [get_ports E0]

set_property IOSTANDARD LVTTL [get_ports b0]

set_property IOSTANDARD LVTTL [get_ports c]

set_property IOSTANDARD LVTTL [get_ports D00[0]]

set_property IOSTANDARD LVTTL [get_ports D00[1]]

set_property IOSTANDARD LVTTL [get_ports D11[0]]

set_property IOSTANDARD LVTTL [get_ports D11[1]]

set_property IOSTANDARD LVTTL [get_ports D22[0]]

set_property IOSTANDARD LVTTL [get_ports D22[1]]

set_property IOSTANDARD LVTTL [get_ports D33[0]]

set_property IOSTANDARD LVTTL [get_ports D33[1]]

PROBLEMA 2

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 05.09.2023 12:50:23

-- Design Name:

-- Module Name: Codi - Func

-- Project Name:

-- Target Devices:
-- Tool Versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Codi is

-- entity Desple2 is

Port ( clk0: in std_logic;

reset0: std_logic;

hex : in STD_LOGIC_VECTOR (0 to 3);


dp : in STD_LOGIC;

sseg : out STD_LOGIC_VECTOR (0 to 7);

AN0, AN1, AN2, AN3: INOUT STD_LOGIC);

end Codi;

architecture Func of Codi is

signal sum: std_logic_vector(0 to 6);

begin

AN0 <= '0';

AN1 <= '1';

AN2 <= '1';

AN3 <= '1';

Suma_unit: entity work.CONTADOR(Behavioral)

port map (salida => sum, clk => clk0, reset => reset0);

with hex select

sseg (0 to 6) <= "0000001" when "0000",

"1001111" when "0001",

"0010010" when "0010",

"0000110" when "0011",

"1001100" when "0100",

"0100100" when "0101",

"0100000" when "0110",

"0001111" when "0111",

"0000000" when "1000",

"0000100" when "1001",

"0001000" when "1010",

"1100000" when "1011",


"0110001" when "1100",

"1000010" when "1101",

"0110000" when "1110",

"0111000" when others;

sseg(7) <= dp;

end Func;

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