Multiprocessing

Ethernet is a branching broadcast communication system for carrying digital data packets among locally distributed computing stations. The packet transport mechanism provided by Ethernet has been used to build systems which can be viewed as either local computer networks or loosely coupled multiprocessors.

Ethernet is a branching broadcast communication system for carrying digital data packets among locally distributed computing stations. The packet transport mechanism provided by Ethernet has been used to build systems which can be viewed as either local computer networks or loosely coupled multiprocessors. An Ethernet's shared communication facility, its Ether, is a passive broadcast medium with no central control. Coordination of access to the Ether for packet broadcasts is distributed among the contending transmitting stations using controlled statistical arbitration. Switching of packets to their destinations on the Ether is distributed among the receiving stations using packet address recognition. Design principles and implementation are described, based on experience with an operating Ethernet of 100 nodes along a kilometer of coaxial cable. A model for estimating performance under heavy loads and a packet protocol for error controlled communication are included for completeness.

Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadlocks, makes fine-grained synchronization difficult, hinders composition of atomic primitives, and provides no support for error recovery. Transactions avoid many of these problems, and therefore, promise to ease concurrent programming.

This paper describes a transputer system m which multipn~ccssors emulate a set of cooperative agents tracking moving objects in the scene. Agents have access to a pyramid image structure to process multi-resolution image segments containing objects of interest. At the same time, agents communicate lhrough a blackboard structure which also provides an instantaneous description of the d~namic scene.

In this paper we analyse the computational aspects of a numerical method for solving the Electric Field Integral Equation (EFIE) for the analysis of the interaction of electromagnetic signals with thinwires structures. Our interest concerns with the design of an efficient parallel implementation of this numerical method which helps physicist to solve the Electric Field Integral Equation for very complex and large thin-wires structures. The development of this parallel implementation has been carried out on distributed memory multiprocessors, with the use of the parallel programming library MPI and routines of PETSc (Portable, Extensible Toolkit for Scientific Computation). These routines can solve sparse linear systems in parallel. Appropriate data partitions have been designed in order to optimize the performance of the parallel implementation. A parameter named relative efficiency has been defined to compare two parallel executions with different number of processors. This parameter allows us to better describe the superlinear performance behavior of our parallel implementation. Evaluation of the parallel implementation is given in terms of the values of the speep-up and the relative efficiency. Moreover, a discussion about the requirements of memory versus the number of processors is included. It will be shown that memory hierarchy management plays a relevant role in the performance of this parallel implementation.

Early results of a project on compiling stylized recursion into stackless iterative code are reviewed as they apply to a target environment with multiprocessing. Parallelism is possible in executing the compiled image of argument evaluation (collateral argument evaluation of Algol 68), of data structure construction when suspensions are used, and of functional combinations. The last facility provides generally, concise expression for all operations performed in Lisp by mapping functions and in APL by typed operators; there are other uses as welL

ABSTRACT The problem to be addressed is one of scheduling multiprocessor tasks, some of which require more than one processor at a time. We extend this model by introducing a uniform k-processor system consisting of k-tuples of processors having the same speeds. A low order polynomial-time preemptive scheduling algorithms is proposed when schedule length is the performance measure.

Ο άνθρωπος που με εισήγαγε στις έννοιες Θεωρίας Συστημάτων και Επεξεργασίας Ση μάτων είναι ο Αναπληρωτής Καθηγητής κ. Σέργιος Θεοδωρίδης. Ο άνθρωπος που με εισήγαγε στην έρευνα στις περιοχές αυτές είναι ο δάσκαλος και φίλος Σέργιος Θεο δωρίδης. Εχοντας συνειδητοποιήσει πόσο πολύ με βοήθησε στη λήψη συγκεκριμένων αποφάσεων οι οποίες θα καθορίσουν σε σημαντικό βαθμό τη ζωή μου τον ευχαριστώ θερμά. Ευχαριστώ τον Καθηγητή κ. Νίκο Καλουπτσίδη για τη βοήθεια που μου προσέφερε τα δύο πρώτα χρόνια της διατριβής και για το ενδιαφέρον που έδειξε καθ' όλη τη διάρκεια της. Ο δάσκαλος και φίλος Αναπληρωτής Καθηγητής κ. Γιώργος Μουστακίδης με βοή θησε σε οποιοδήποτε πρόβλημα ζήτησα τη βοήθεια του. Τον ευχαριστώ θερμά. Ευχαριστώ τους Καθηγητές κ. Δημήτρη Μαρίτσα και κ. Κώστα Γκούτη καθώς και τους Επίκουρους Καθηγητές κ. Θάνο Στουραίτη και κ. Γιάννη Τσινιά για την πρόθυμη συμμετοχή τους στην Επταμελή Εξεταστική Επιτροπή. Ευχαριστώ, επίσης, το συνάδελφο Γιώργο Γλεντή για την εισαγωγή μου στην έννοια των Κλιμακωτών Αλγορίθμων. Αισθάνομαι τυχερός διότι δούλεψα μέσα σε ένα φιλικώτατο περιβάλλον το οποίο έχουν δημιουργήσει οι συνάδελφοι μεταπτυχιακοί φοιτητές του Τμήματος Μηχανικών Η\Υ και Πληροφορικής. Τέλος, θα ήθελα να ευχαριστήσω τους γονείς μου, διότι χωρίς τη δική τους παρό τρυνση και συμπαράσταση δεν θα είχα γνωρίσει τον "υπέροχο" κόσμο της έρευνας. Και επειδή δεν θα ήθελα να ξεχάσω κανένα Ευχαριστώ όλους όσους με βοήϋησαν

x Recent advancements in processor technology such as Symmetric Multithreading (SMT) and Chip Multiprocessors (CMP) enable parallel processing on a single chip. These processors are used as building blocks of shared-memory UMA and NUMA multiprocessor systems, or even clusters of multiprocessors. New programming languages and tools are necessary to help programmers manage the complexities introduced by systems with multigrain and multilevel execution capabilities. This paper introduces Factory, an objectoriented parallel programming substrate which allows programmers to express parallelism, but alleviates them from having to manage it. Factory is written in C++ without introducing any extensions to the language. Instead, it leverages existing constructs from C++ to express parallel computations. As a result, it is highly portable and does not require compiler support. Moreover, Factory offers programmability and performance comparable with already established multithreading substrates.

Yorktown Heights, NY. His present interests are in the fields of magnetic bubble memories, scheduling algorithms for SS/ TDMA systems, and algorithms for VLSI implementation. C. K. Wong (M'71-SM'78), for a photograph and biography, see p. 405 of the June 1981 issue of this TRANSACTIONS.

Ethernet is a branching broadcast communication system for carrying digital data packets among locally distributed computing stations. The packet transport mechanism provided by Ethernet has been used to build systems which can be viewed as either local computer networks or loosely coupled multiprocessors.

The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end computing systems and game consoles have become shared memory multiprocessors with L1 and L2 cache sharing within a chip. Mid-and large-scale systems will have multiple processing chips and hence consist of an SMP-CMP-SMT configuration with non-uniform data sharing overheads. Current operating system schedulers are not aware of these new cache organizations, and as a result, distribute threads across processors in a way that causes many unnecessary, long-latency cross-chip cache accesses.

hrge grain data flow (LGDF) programming is natural and convenient for describing digital signal processing (DSP) systems, but its runtime overhead is costly in real time or cost-sensitive applications. In some situations, designers are not willing to squander computing resources for the sake of programmer convenience. This is particularly true when the target machine is a programmable D S P chip. However, the runtime overhead inherent in most LGDF implementations is not required for most signal processing systems because such systems are mostly synchronous (in the D S P sense). Synchronous data flow (SDF) differs from traditional data flow in that the amount of data produced and consumed by a data flow node is specified a priori for each input and output. This is equivalent to specifying the relative sample rates in signal processing system. This means that the scheduling of SDF nodes need not be done at runtime, but can be done at compile time (statically), so the runtime overhead evaporates. The sample rates can all be different, which is not true of most current data-driven digital signal processing programming methodologies. Synchronous data flow is closely related to computation graphs, a special case of Petri nets. This self-contained paper develops the theory necessary to statically schedule SDF programs on single or multiple processors. A class of static (compile time) scheduling algorithms is proven valid, and specific algorithms are given for scheduling SDF systems onto single or multiple processors. I Index Terms-Block diagram, computation graphs, data flow digital signal processing, hard real-time systems, multiprocessing, Petri nets, static scheduling, synchronous data flow.

En este artículo se presenta una nueva propuesta que realiza asignación adaptativa de recursos para controlar un sistema multiproceso utilizando técnicas bio-inspiradas, basadas específicamente en algoritmos de inteligencia de enjambres (Swarm Intelligence, SI). Estos algoritmos solucionan problemas de alta complejidad demostrando características de adaptación y cooperación entre los diversos agentes individuales, a partir de reglas simples. Ello conlleva a observar con expectativa el desempeño sobre el nivel de aplicabilidad que estos algoritmos tienen en el control de sistemas complejos con múltiples entradas y salidas. En este trabajo se propone ejecutar diferentes modelos de enjambres de forma independiente recreando un sistema competitivo desde el punto de vista operacional, ya que estos se basan únicamente en propiedades asignadas a su propio modelo de enjambre. Esta propuesta fue estudiada y analizada utilizando diversas métricas de desempeño. Todos los algoritmos evaluados lograron controlar todos los procesos asignados especialmente el modelo de hormigas que mostró mayor estabilidad.

Abstract Recent design methodologies and tools aim at enhancing the design productivity by providing a software development platform before defining the final MPSoC architecture details. Motivated by the lack of MPSoC virtual platforms prototyping integrating both scalable hardware and software in order to create and evaluate new methodologies and tools, we present the MPSoCBench, a scalable set of MPSoCs including four different ISAs (PowerPC, MIPS, SPARC, and ARM) organized in platforms with up to 64 cores, cross-compilers, IPs, interconnections, 17 parallel versions of software from well-known benchmarks, and power consumption estimation for main components (processors, routers, memory, and caches), including DVFS support.

I 1 17 6a. NAME OF PERFORMING ORGANIZATION 6b. OFFICE SYMBOL 7a. NAME OF MONITORING ORGANIZATION University of Illinois (If applicable) Dire':torate of Mathematical and Information Science, AFOSR 6c. ADDRESS (City, State, and ZIP Code) 7b ADDRESS (City, State, and ZIP Code) Building 410 Bolling AFB, DC 20332-6448 8a. NAME OF FUNDINGISPONSORING 8b. OFFICE SYMBOL 9 PROCUREMENT INSTRUMENT IDENTIFICATION NUMBER ORGANIZATIONI (if applicable) AFOSR NM AFOSR-85-0211 8c. ADDRESS (City, State, and ZIP Code) 10 SOURCE OF FUNDING NUMBERS

We constructed a simulation model, using the PAWS simulation modeling tools, to predict the peflormance of a shared memory multiprocessor operating system. The operating system is divided into 5 distinct sections, called empires. We used the model to predict the efficiency of this paradigm of multiprocessing for the Hewlett-Packard HP-UX Release 8.0 operating system. The simulation results show that the empires architecture is effective in providing enough concurrency for a 4-way computer under a program development workload. We will describe the model and its parameters, present and discuss the results, provide a statistical analysis of the data, and analyze the results.

One of critical issues affecting parallel system performance is the scheduling of parallel tasks onto available target processors. A number of algorithms and software tools have been presented to deal with the task scheduling problem in parallel processing. This paper studies the static scheduling of general types of applications. We focus on "conditional task scheduling", in which the task model may vary between each program execution, due to conditional branching within tasks. A parallel programming environment, called ATME, is presented to practically tackle this complicated conditional scheduling problem. Keywords: static scheduling, conditional task scheduling, task model, model estimation, multiprocessing, parallel programming environment. 1 Introduction Parallel programming is more complex than its sequential programming counterpart. Issues to be considered include task partition, task communication and synchronization, task scheduling and tuning. The performance of...

En este articulo se presenta una nueva propuesta que realiza asignacion adaptativa de recursos para controlar un sistema multiproceso utilizando tecnicas bio-inspiradas, basadas especificamente en algoritmos de inteligencia de enjambres (SwarmIntelligence, SI). Estos algoritmos solucionan problemas de alta complejidad demostrando caracteristicas de adaptacion y cooperacion entre los diversos agentes individuales, a partir de reglas simples. Ello conlleva a observar con expectativa el desempeno sobre el nivel de aplicabilidad que estos algoritmos tienen en el control de sistemas complejos con multiples entradas y salidas. En este trabajo se propone ejecutar diferentes modelos de enjambres de forma independiente recreando un sistema competitivo desde el punto de vista operacional, ya que estos se basan unicamente en propiedades asignadas a su propio modelo de enjambre. Esta propuesta fue estudiada y analizada utilizando diversas metricas de desempeno. Todos los algoritmos evaluados lo...

Scheduling competing jobs on multiprocessors has always been an important issue for parallel and distributed systems. The challenge is to ensure global, system-wide efficiency while offering a level of fairness to user jobs. Various degrees of successes have been achieved over the years. However, few existing schemes address both efficiency and fairness over a wide range of work loads. Moreover, in order to obtain analytical results, most of them require prior information about jobs, which may be difficult to obtain in real ...

The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end computing systems and game consoles have become shared memory multiprocessors with L1 and L2 cache sharing within a chip. Mid-and large-scale systems will have multiple processing chips and hence consist of an SMP-CMP-SMT configuration with non-uniform data sharing overheads. Current operating system schedulers are not aware of these new cache organizations, and as a result, distribute threads across processors in a way that causes many unnecessary, long-latency cross-chip cache accesses. In this paper we describe the design and implementation of a scheme to schedule threads based on sharing patterns detected online using features of standard performance monitoring units (PMUs) available in today's processing units. The primary advantage of using the PMU infrastructure is that it is fine-grained (down to the cache line) and has relatively low overhead. We have implemented our scheme in Linux running on an 8-way Power5 SMP-CMP-SMT multiprocessor. For commercial multithreaded server workloads (VolanoMark, SPECjbb, and RUBiS), we are able to demonstrate reductions in cross-chip cache accesses of up to 70%. These reductions lead to application-reported performance improvements of up to 7%.

Software Transactional Memory (STM) ensures synchronization in parallel programs without suffering from the drawbacks of locks. Fault tolerance is an important issue in STM. In this paper we ensure fault tolerance in STM by using replication. Whenever any transaction suddenly aborts another transaction starts which performs the same operations as the transaction which has aborted. Thus even if any transaction fails or is aborted due to some reason then the result is not affected. We have also seen that there is no performance degradation if this approach is used. We have replicated only the important transactions so that redundancy is kept to the bare minimum. Thus we can say that we have developed an approach using replication which has made STM fault-tolerant without any performance degradation keeping redundancy to the bare minimum.

Transactional memory (TM) promises to simplify concurrent programming while providing scalability competitive to fine-grained locking. Language-based constructs allow programmers to denote atomic regions declaratively and to rely on the underlying system to provide transactional guarantees along with concurrency. In contrast with fine-grained locking, TM allows programmers to write simpler programs that are composable and deadlock-free. TM implementations operate by tracking loads and stores to memory and by detecting concurrent conflicting accesses by different transactions. By automating this process, they greatly reduce the programmer's burden, but they also are forced to be conservative. In certain cases, conflicting memory accesses may not actually violate the higher-level semantics of a program, and a programmer may wish to allow seemingly conflicting transactions to execute concurrently. Open nested transactions enable expert programmers to differentiate between physical conflicts, at the level of memory, and logical conflicts that actually violate application semantics. A TM system with open nesting can permit physical conflicts that are not logical conflicts, and thus increase concurrency among application threads. Here we present an implementation of open nested transactions in a Java-based software transactional memory (STM) system. We describe new language constructs to support open nesting in Java, and we discuss new abstract locking mechanisms that a programmer can use to prevent logical conflicts. We demonstrate how these constructs can be mapped efficiently to existing STM data structures. Finally, we evaluate our system on a set of Java applications and data structures, demonstrating how open nesting can enhance application scalability.