FPGA Architectures

Today's world demand for faster, accurate and power efficient embedded devices. These devices are not only used for controlling applications, but are also expected to perform advanced applications like image processing, audio/video encoding/decoding, etc, which need more computational speed with low power. The multiprocessor systems on a chip (MPSoC) are an option to deal with these increasing computational needs. The proposed research work is based on development of the Multi-processors environment on a FPGA chip using Microblaze soft-core processor (from Xilinx Co.). Advances in FPGA technology led the implementation of such architectures in a single chip feasible and very appealing. This MPSoC environment will be used to reduce the overhead on central processor (Master). Later an Image processing application is developed to run on a Multi-processor environment and improvement in the speed of operation is observed.

Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors that contribute to the reconfiguration speed. Then, we study an FPGA-based system architecture and with real experiments we produce a cost model of Partial Reconfiguration (PR). This model is introduced to calculate the expected reconfiguration time and throughput. In order to develop a realistic model we take into account all the physical components that participate in the reconfiguration process. We analyze the parameters that affect the generality of the model and the adjustments needed per system for error-free evaluation. We verify it with real measurements, and then we employ it to evaluate existing systems presented in previous publications. The percentage error of the cost model when comparing its results with the actual values of those publications varies from 36% to 63%, whereas existing works report differences up to two orders of magnitude. Present work enables a user to evaluate PR and decide whether it is suitable for a certain application prior entering the complex PR design flow.

One of the most active research areas in the field of robotics is robot manipulators control, because these systems are
multi-input multi-output (MIMO), nonlinear, and uncertainty. At present, robot manipulators are used in unknown and
unstructured situation and caused to provide complicated systems, consequently strong mathematical tools are used in
new control methodologies to design nonlinear robust controller with satisfactory performance (e.g., minimum error,
good trajectory, disturbance rejection). Robotic systems controlling is vital due to the wide range of application.
Obviously stability and robustness are the most minimum requirements in control systems; even though the proof of
stability and robustness is more important especially in the case of nonlinear systems. The strategies of robotic
manipulators control are classified into two main groups: classical and non-classical methods, where the conventional
control theory uses the classical method and the artificial intelligence theory (e.g., fuzzy logic, neural network, and neuro
fuzzy) uses the non-classical methods. However both of classical and non-classical theories have applied successfully in
many applications, but they also have some limitations. One of the best nonlinear robust controllers which can be used in
uncertainty nonlinear systems is sliding mode controller (SMC). Sliding mode controller has two most important
challenges: chattering phenomenon and nonlinear dynamic equivalent part. This paper is focused on the applied nonclassical
method (e.g., Fuzzy Logic) in robust classical method (e.g., Sliding Mode Controller) in the presence of
uncertainties and external disturbance to reduce the limitations. Applying the Mamdani’s error based fuzzy logic
controller with 7 rules is the main goal that causes the elimination chattering phenomenon with regard to the variety of
uncertainty and external disturbance; as a result this paper focuses on the sliding mode controller with artificial tuneable
gain (SMCAT) to adjusting the sliding surface slope coefficient depends on applying fuzzy method.

With the advent of the new and continuously improving technologies , in a couple of years DNA sequencing can be as commonplace as a simple blood test. The growth of sequencing efficiency has a larger exponent than the Moore's law of standard processors, hence alignment and further processing of sequenced data is the bottleneck. The usage of FPGA (Field Programmable Gate Arrays) technology may provide an efficient alternative. We propose a simple algorithm for DNA sequence alignment, which can be realized efficiently by nucleotic principal agents of Non.Neumann nature. The prototype FPGA implementation runs on a small Terasic DE1-SoC demo board with a Cyclone V chip. We present test results and furthermore analyse the theoretical scalability of this

Overlay architectures implemented on FPGA devices have been proposed as a means to increase FPGA adoption in general-purpose computing. They provide the benefits of software such as flexibility and programmability, thus making it easier to build dedicated compilers. However, existing overlays are generic, resource and power hungry with performance usually an order of magnitude lower than bare metal implementations. As a result, FPGA overlays have been confined to research and some niche applications. In this paper, we introduce Application-Specific FPGA Overlays (AS-Overlays), which can provide bare-metal performance to FPGA overlays, thus opening doors for broader adoption. Our approach is based on the automatic extraction of hardware kernels from data flow applications. Extracted kernels are then leveraged for application-specific generation of hardware accelerators. Reconfiguration of the overlay is done with RapidWright which allows to bypass the HDL design flow. Through prototyping, we demonstrated the viability and relevance of our approach. Experiments show a productivity improvement up to 20× compared to the state of the art FPGA overlays, while achieving over 1.33× higher Fmax than direct FPGA implementation and the possibility of lower resource and power consumption compared to bare metal.

Field Programmable Gate Array (FPGA) technology has gained vital importance mainly because of its
parallel processing hardware which makes it ideal for image and video processing. In this paper, a step by
step approach to apply a linear spatial filter on real time video frame sent by Omnivision OV7670 camera
using Zynq Evaluation and Development board based on Xilinx XC7Z020 has been discussed. Face
detection application was chosen to explain above procedure. This procedure is applicable to most of the
complex image processing algorithms which needs to be implemented using FPGA.