Boolean Functions

Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolving state coding conflicts. The refinement process is generally done automatically using heuristics and often produces sub-optimal solutions, which have to be corrected manually. This paper presents a framework for an interactive refinement process aimed to help the designer. It is based on the visualization of conflict cores, i.e., sets of transitions causing coding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings.

We determine an explicit procedure for representing any Boolean expression in a recursive form which can be realized using memristive devices, and demonstrate how the truth value of any Boolean expression can be determined using no more than two computing memristive devices. We present an algorithm which can be used to significantly reduce the number of implications required for representing a specific Boolean expression, and consider device-specific benefits in terms of reducing the lengths of computational sequences.

In this paper, the complexity of applying a guess and determine attack to so-called Linear Feedback Shift register (LFSR)-based stream ciphers is analyzed. This family of stream ciphers uses a single or several LFSR and a filtering function F : GF (2) n ! GF (2) m to generate the blocks of m 1 keystream bits at the time. In difference to a classical guess and determine attack, a method based on guessing certain bits in order to determine the remaining secret key/state bits, our approach efficiently takes advantage of the reduced preimage space for relatively large m and at the same time employing the design structure of the cipher. Several variations of the algorithm are derived to circumvent the sensitivity of attack to the input data, n; m and the key length. In certain cases, our attack outperforms classical algebraic attacks [10]; these being considered as one of the most efficient cryptanalyst tools for this type of ciphers.

A method for computing the Disjoint-Sum-Of-Products (DSOP) form of Boolean functions is described. The algorithm exploits the property of the most binate variable in a set of cubes to compute a DSOP form. The technique uses a minimized Sum-Of-Products (SOP) cube list as input. Experimental results comparing the size of the DSOP cube list produced by this algorithm and those produced by other methods demonstrate the efficiency of this technique and show that superior results occur in many cases for a set of benchmark functions.

Fomin and Thilikos in conjectured that there is a constant c such that, for every 2connected planar graph G, pw(G * ) ≤ 2pw(G)+c (the same question was asked simutaneously by Coudert, Huc and Sereni in [4]). By the results of Boedlander and Fomin [2] this holds for every outerplanar graph and actually is tight by Coudert, Huc and Sereni [4]. In , Fomin and Thilikos proved that there is a constant c such that the pathwidth of every 3-connected graph G satisfies: pw(G * ) ≤ 6pw(G) + c. In this paper we improve this result by showing that the dual a 3-connected planar graph has pathwidth at most 3 times the pathwidth of the primal plus two. We prove also that the question can be answered positively for 4-connected planar graphs.

This paper presents a Matlab based Scheduling toolbox TORSCHE (Time Optimization of Resources, SCHEduling). The toolbox offers a collection of data structures that allow the user to formalize various off-line and online scheduling problems. Algorithms are simply implemented as Matlab functions with fixed structure allowing users to implement new algorithms. A more complex problem can be formulated as an Integer Linear Programming problem or satisfiability of boolean expression problem. The toolbox is intended mainly as a research tool to handle control and scheduling co-design problems. Therefore, we provide an interfaces to a real-time Matlab/Simulik based simulator TrueTime and a code generator allowing to generate parallel code for FPGA.

The concept of binary decision trees is extended to include multiple output Boolean functions. A systematic and programmable method is then developed for the minimization of trees realizing multiple output incompletely specified functions. Further simplification of minimal trees can be achieved through state reduction methods to obtain subminimal decision algorithms. Possible physical realizations of decision trees and algorithms as well as their applications are discussed.

In conventional equalizers, the facts of bulky size and high cost are widespread. Particularly, the zero switching loss and zero-voltage gap (ZVG) between cells are difficult to implement due to the high-frequency hard switching and the voltage drop across power devices. To overcome these difficulties, a direct cell-to-cell battery equalizer based on quasi-resonant LC converter (QRLCC) and boost DC-DC converter (BDDC) is proposed. The QRLCC is employed to gain zero-current switching (ZCS), leading to a reduction of power losses. The BDDC is employed to enhance the equalization voltage gap for large balancing current and ZVG between cells. Moreover, through controlling the duty cycle of the BDDC, the topology can online adaptively regulate the equalization current according to the voltage difference, which not only effectively prevents over-equalization but also abridges the overall balancing time. Instead of a dedicated equalizer for each cell, only one balancing converter is employed and shared by all cells, reducing the size and implementation cost. Simulation and experimental results show the proposed scheme exhibits outstanding balancing performance, and the energy conversion efficiency is higher than 98%. The validity of the proposed equalizer is further verified by a quantitative and systematic comparison with the existing active balancing methods.

In today's fast paced world of increasing and innovative new technology, fuzzy logic is a practical mathematical addition to classic Boolean logic. We can see its applications in many fields of science and engineering. This paper gives a general overview with a large bibliography, on many such applications to target tracking, pattern recognition, robotics, power systems, controller design, chemical engineering, biomedical engineering, vehicular technology, economy management as well as decision making, communications and networking, electronic engineering, civil engineering, sensor technology, and industry

The pressure of fundamental limits on classical computation and the promise of exponential speedups from quantum effects have recently brought quantum circuits [10] to the attention of the Electronic Design Automation community . We discuss efficient quantum logic circuits which perform two tasks: (i) implementing generic quantum computations and (ii) initializing quantum registers. In contrast to conventional computing, the latter task is nontrivial because the state-space of an n-qubit register is not finite and contains exponential superpositions of classical bit strings. Our proposed circuits are asymptotically optimal for respective tasks and improve earlier published results by at least a factor of two.

In this paper an advanced genetic algorithm is used to find the maximum nonlinearity of n-argument Boolean homogenous functions. The best nonlinearity for Boolean functions number of arguments n was searched, where n= 8, 10, 12, 14 and for the degree k of homogeneity such that 1<k<n. The experimental results that were reached prove that our genetic algorithm is a powerful tool to search for high nonlinearity. Results are presented in diagrams and tables.

in this paper, we present the design of an efficient multiplication unit. This multiplier architecture is based on Radix 4 Booth multiplier. In order to improve his architecture, we have made 2 enhancements. The first is to modify the Wen-Chang's Modified Booth Encoder (MBE) since it is the fastest scheme to generate a partial product. However, when implementing this MBE with the Simplified Sign Extension (SSE) method, the multiplication's output is incorrect. The 2 nd part is to improve the delay in the 4:2 compressor circuit. The redesigned 4:2 compressor reduced the delay of the Carry signal. This modification has been made by rearranging the Boolean equation of the Carry signal. This architecture has been designed using Quartus II. The Gajski rule has been adopted in order to estimate the delay and size of the circuit. The total transistor count for this new multiplier is being a slightly bigger. This is due to the new MBE which is uses more transistor. However in performance speed, this efficiency multiplier is quite good. The propagation delay is reduced by about 2% -7% from other designers.

A Boolean relation can specify some types of flexibility of a combinational circuit that cannot be expressed with don't cares. Several problems in logic synthesis, such as Boolean decomposition or multilevel minimization, can be modeled with Boolean relations. However, solving Boolean relations is a computationally expensive task. This paper presents a novel recursive algorithm for solving Boolean relations. The algorithm has several features: efficiency, wide exploration of solutions, and customizable cost function. The experimental results show the applicability of the method in logic minimization problems and tangible improvements with regard to previous heuristic approaches.

Nested words are a structured model of execution paths in procedural programs, reflecting their call and return nesting structure. Finite nested words also capture the structure of parse trees and other tree-structured data, such as XML. We provide new temporal logics for finite and infinite nested words, which are natural extensions of LTL, and prove that these logics are first-order expressively-complete. One of them is based on adding a "within" modality, evaluating a formula on a subword, to a logic CaRet previously studied in the context of verifying properties of recursive state machines (RSMs). The other logic, NWTL, is based on the notion of a summary path that uses both the linear and nesting structures. For NWTL we show that satisfiability is EXPTIME-complete, and that model-checking can be done in time polynomial in the size of the RSM model and exponential in the size of the NWTL formula (and is also EXPTIME-complete). Finally, we prove that first-order logic over nested words has the three-variable property, and we present a temporal logic for nested words which is complete for the two-variable fragment of first-order.

An algorithm for compact neural-network hardware implementation is presented, which exploits the special properties of the Boolean functions describing the operation of artificial neurons with step activation function. The algorithm contains three steps: artificial-neural-network (ANN) mathematical model digitization, conversion of the digitized model into a logic-gate structure, and hardware optimization by elimination of redundant logic gates. A set of C++ programs automates algorithm implementation, generating an optimized very high speed integrated circuit hardware description language code. This strategy bridges the gap between ANN design software and hardware design packages (Xilinx). Although the method is directly applicable only to neurons with step activation functions, it can be extended to sigmoidal functions.

A method for performing Boolean division and factorization using a new cofactor operation, the interval cofactor, is proposed. This method is efficiently implemented using BDD's and allows for the use of external and internal don't care sets. As well as generating a normal factored form, the method also generates an extended factored form that allows for the use of the exclusive-OR function in the expression. Using this extended form, much better factorizations may sometimes be found. The method was implemented in Catamount, a logic synthesis system currently under development. The method compares favorably to existing algebraic methods.

Theoretical computer scientists have been debating the role of oracles since the 1970&#x27;s. This paper illustrates both that oracles can give us nontrivial insights about the barrier problems in circuit complexity, and that they need not prevent us from trying to solve those problems. First, we give an oracle relative to which PP has linear-sized circuits, by proving a new

In this paper, a C++ class for analising Vector Boolean Functions from a cryptographic perspective is presented. This implementation uses the NTL library from Victor Shoup, replacing some of the general purpose modules of this library by some more specialized and better suited to cryptography, and adding new modules that complement the existing ones. With this class, we can obtain

We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentioned vectors (registered vectors) has been developed. In this method logic functions are implemented using both embedded memory blocks

We propose a novel preprocessing technique that helps to significantly simplify a CNF instance, such that the resulting formula is easier for any SAT-solver to solve. The core of this simplification centers on a suite of lemmas and theorems derived from nontrivial Boolean reasoning. These theorems help us to deduce powerful unary and binary clauses which aid in the identification of necessary assignments, equivalent signals, complementary signals and other implication relationships among the CNF variables. The nontrivial clauses, when added to the original CNF database, subsequently simplify the CNF formula. We illustrate through experimental results that the CNF formula simplification obtained using our tool outperforms the simplification obtained using the recent preprocessors namely Hypre [F. Bacchus et al., (2003)] and NIVER [S. Subbarayan et al. (2004)]. Also, considerable savings in computation time are obtained when the simplified CNF formula is given to the SAT-solver for processing.

As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. Software checking approaches are attractive because they require little hardware modification and can be easily adjusted to fit different reliability and performance requirements. Unfortunately, software checking adds a significant performance overhead.

Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-power design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this paper, we propose a synthesis approach, that can cope with Boolean functions containing more than a hundred of variables. We present a technique to derive reversible circuits for a function given by a Binary Decision Diagram (BDD). The circuit is obtained using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, the size of the resulting circuit is bounded by the BDD size. This allows to transfer theoretical results known from BDDs to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.

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In this paper a new fast simplification method is presented. Such method realizes karnough map with large number of variables. In order to accelerate the operation of the proposed method, a new approach for fast detection of group of ones is presented. Such approach implemented in the frequency domain. The search operation relies on performing cross correlation in the frequency domain rather than time one. It is proved mathematically and practically that the number of computation steps required for the presented method is less than that needed by conventional cross correlation. Simulation results using MATLAB confirm the theoretical computations.

In this paper, a C++ class for analising Vector Boolean Functions from a cryptographic perspective is presented. This implementation uses the NTL library from Victor Shoup, replacing some of the general purpose modules of this library by some more specialized and better suited to cryptography, and adding new modules that complement the existing ones. With this class, we can obtain the classical representation of Vector Boolean Function such as its Truth Table and Algebraic Normal Form (ANF). It is possible to calculate mathematical structures such as the Walsh Spectrum, Linear Profile, Differential Profile and Autocorrelation Spectrum. Cryptographic criteria such as nonlinearity, linearity distance, order of correlation immunity, bal-ancedness, algebraic degree and propagation criterion can be obtained with this class. It permits to find out some interesting cryptologic parameters such as linear structures, linear potential, differential potential and the maximum possible nonlineari...

While monadic second-order logic is a prominent logic for specifying languages of finite words, it lacks the power to compute quantitative properties, e.g. to count. An automata model capable of computing such properties are weighted automata, but logics equivalent to these automata have only recently emerged. We propose a new framework for adding quantitative properties to logics specifying Boolean properties of words. We use this to define Quantitative Monadic Second-Order Logic (QMSO). In this way we obtain a simple logic which is equally expressive to weighted automata. We analyse its evaluation complexity, both data and combined complexity, and show completeness results for combined complexity. We further refine the analysis of this logic and obtain fragments that characterise exactly subclasses of weighted automata defined by the level of ambiguity allowed in the automata. In this way, we define a quantitative logic which has good decidability properties while being resonably expressive and enjoying a simple syntactical definition. I. INTRODUCTION Using logics as specification languages for properties of finite and infinite words or trees has a long history in computer science. Of particular importance in this context is Monadic Second-Order Logic (MSO), the extension of first-order logic by quantification over sets of positions in the input word (see e.g. [23], [10]). The prominence of MSO as logic over words has many causes: It is a very expressive and yet simple logic in which many properties can be expressed very naturally. In fact, Büchi's classical theorem [6] states that a language is recognisable by a finite state automaton if, and only if, it is definable in MSO. Hence, MSO can define precisely the regular languages and provides an elegant specification mechanism for regular properties. Furthermore , the proof of the theorem is algorithmic which implies that MSO formulas can effectively be compiled into finite automata which can then be run in linear time on any input word. Finally, MSO has very good decidability properties and standard problems such as satisfiability and therefore equivalence and containment of formulas are decidable over finite words. While MSO is an elegant and highly successful mechanism for specifying word languages, there are many ap

In recent years, reversible logic has emerged as a promising computing paradigm having application in low-power CMOS, quantum computing, nanotechnology and optical computing. Optical logic gates have the potential to work at macroscopic (light pulses carry information), or quantum (single photons carry information) levels with great efficiency. However, relatively little has been published on designing reversible logic circuits in all-optical domain. In this paper, we propose and design a novel scheme of Toffoli and Feynman gates in all-optical domain. We have described their principle of operations and used a theoretical model to assist this task, finally confirming through numerical simulations. Semiconductor optical amplifier (SOA)-based Mach–Zehnder interferometer (MZI) can play a significant role in this field of ultra-fast all-optical signal processing. The all-optical reversible circuits presented in this paper will be useful to perform different arithmetic (full adder, BCD adder) and logical (realization of Boolean function) operations in the domain of reversible logic-based information processing.

We present a new algorithm, EST, that accelerates any combinatorial circuit Automatic Test-Pattern Generation algorithm. EST detects equivalent search states, which are saved for all faults during ATPG. The search space is reduced by using Binary Decision Diagram fragments to detect previously-encountered search states (possibly from prior faults). Search terminates earlier than before. Redundant fault analysis further accelerates ATPG. ATPG is accelerated 1347 times for hardto-test faults in the ISCAS '85 benchmarks.

Analog and mixed signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time. In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches.

Analog and mixed signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time. In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches.

Recently, Shparlinski proved several results on the interpolation of the discrete logarithm in ÿnite prime ÿelds by Boolean functions. In the ÿrst part of the paper, these results are extended to arbitrary ÿnite ÿelds of odd characteristic. More precisely, we prove some complexity lower bounds for Boolean functions representing the least signiÿcant bit of the discrete logarithm in a ÿnite ÿeld.

Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique computational technique for calculations based on 16 Sutras (Formulae). Novel divider architecture for high speed VLSI application using such ancient methodology is presented in this paper. Propagation delay and dynamic power consumption of a divider circuitry were minimized significantly by removing unnecessary recursion through Vedic division methodology. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90nm CMOS technology. The propagation delay of the resulting 16-bit binary dividend by an 8-bit divisor circuitry was only ~10.5ns and consumed ~24μW power for a layout area of ~10.25 mm 2. By combining Boolean logic with ancient Vedic mathematics, substantial amount of iteration were eliminated that resulted in ~45% reduction in delay and ~30% reduction in power compared with the mostly used (Digit Recurrence, Convergence & Series Expansion) architectures.

This paper introduces an incremental algorithm for learning a Boolean function from examples. The functions are constructed in the disjunctive normal form (DNF) or the conjunctive normal form (CNF) and emphasis is placed in inferring functions with as few clauses as possible. This incremental algorithm can be combined with any existing algorithm that infers a Boolean function from examples. In this paper it is combined with the one clause at a time (OCAT) approach (Comput. Oper. Res. 21(2) (1994) 185) and (J. Global Optim. 5(1) (1994) 64) which is a non-incremental learning approach. An extensive computational study was undertaken to assess the performance characteristics of the new approach. As examples, we used binary vectors that represent text documents from di erent categories from the TIPSTER collection. The computational results indicate that the new algorithm is considerably more e cient and it derives more accurate Boolean functions. As it was anticipated, the Boolean functions (in DNF or CNF form) derived by the new algorithm are comprised by more clauses than the functions derived by the non-incremental approach.

In ant societies, and, more in general, in insect societies, the activities of the individuals, as well as of the society as a whole, are not regulated by any explicit form of centralized control. On the other hand, adaptive and robust behaviors transcending the behavioral repertoire of the single individual can be easily observed at society level. These complex global behaviors are the result of self-organizing dynamics driven by local interactions and communications among a number of relatively simple individuals. The simultaneous presence of these and other fascinating and unique characteristics have made ant societies an attractive and inspiring model for building new algorithms and new multi-agent systems. In the last decade, ant societies have been taken as a reference for an ever growing body of scientific work, mostly in the fields of robotics, operations research, and telecommunications.

This paper presents a new concurrent method for the decomposition and factorization of Boolean expressions. The method uses only two-literal single-cube divisors and double-cube divisors considered concurrently with their complements. We demonstrate that these objects, despite their simplicity, provide a very good framework on which to reason about common algebraic divisors and the duality relations between expressions. The simplicity of these objects makes it possible to compute the cost function associated with them accurately and dynamically. Hence, the method is entirely greedy, and in each iteration it extracts the best expression along with its complement. The decomposition is based on testability-preserving transformations, and the synthesized multilevel network is fully tested by a complete test set derived for the original circuit. The algorithm has been implemented and excellent results on several benchmark circuits illustrate its efficiency and effectiveness.

A new design methodology for mapping circuits is discussed in this paper. It proposes two new techniques for mapping circuits. The rst method, known as the odd-level transistor replacement OTR method, has a goal that is similar to that of technology mapping, but without the restriction of a xed library size. The second technique, the Static PTL method, uses a mix of static CMOS and pass transistor logic PTL to realize the circuit, using the relation between PTL and binary decision diagrams. The methods are very efcient and can handle all of the ISCAS85 benchmark circuits in minutes. A comparison of the results with traditional technology mapping using SIS on di erent libraries shows an average delay reduction about 40 for OTR, and an average delay reduction above 50 for the Static PTL method.

This paper presents rough sets generating prediction rules scheme for stock price movement. The scheme was able to extract knowledge in the form of rules from daily stock movements. These rules then could be used to guide investors whether to buy, sell or hold a stock. To increase the efficiency of the prediction process, rough sets with Boolean reasoning discretization algorithm is used to discretize the data. Rough set reduction technique is applied to find all the reducts of the data. Finally, rough sets dependency rules are generated directly from all generated reducts. Rough confusion matrix is used to evaluate the performance of the predicted reducts and classes. A comparison between the obtained results using rough sets with decision tree and neural networks algorithms have been made. Rough sets show a higher overall accuracy rates reaching over 97%and generate more compact rules.

A theory has been developed to calculate the Rademacher-Walsh transform from a cube a r r a y specification of incompletely specified Boolean functions. T h e importance of representing Boolean functions a s a r r a y s of disjoint ON-a n d Ix-cubes has been pointed out, a n d a n efficient new algorithm to generate disjoint cubes f r o m nondisjoint ones has been designed. The t r a n s f o r m algorithm makes use of the properties of a n a r r a y of disjoint cubes a n d allows the determination of the spectral coefficients in a n independent way. The programs for both algorithms use advantages of C language to speed u p the execution. The comparison of different versions of the algorithm has been carried out. T h e presented algorithm a n d its implementation is the fastest a n d most comprehensive program (having many options) known t o us for the calculation of R ademacher-Walsh transform. It successfully overcomes all drawbacks in the calculation of the t r a n s f o r m f r o m the design automation system based on spectral methods-the SPECSYS system from Drexel University that uses Fast Walsh T r a n sform.