Static Nonlinearity in Graphene Field Effect Transistors

Ana Rusu

Static Nonlinearity in Graphene Field Effect Transistors

Ana Rusu

2014, IEEE Transactions on Electron Devices

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The static linearity performance metrics of the GFET transconductor are studied and modeled. Closed expressions are proposed for second and third order harmonic distortion (HD2, HD3), second and third order intermodulation distortion (∆IM2, ∆IM3), and second and third order intercept points (AIIP 2, AIIP 3). The expressions are validated through large-signal simulations using a GFET VerilogA analytical model and a commercial circuit simulator. The proposed expressions can be used during circuit design in order to predict the GFET biasing conditions at which linearity requirements are met.

This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be available. Static Non-linearity in Graphene Field Effect Transistors arXiv:1405.2142v1 [cond-mat.mes-hall] 9 May 2014 Saul Rodriguez, Member, IEEE, Anderson Smith, Student Member, IEEE, Sam Vaziri, Student Member, IEEE, Mikael Ostling, Fellow, IEEE, Max C. Lemme, Senior Member, IEEE, and Ana Rusu, Member, IEEE Abstract—The static linearity performance metrics of the GFET transconductor are studied and modeled. Closed expressions are proposed for second and third order harmonic distortion (HD2 , HD3 ), second and third order intermodulation distortion (∆IM2 , ∆IM3 ), and second and third order intercept points (AIIP 2 , AIIP 3 ). The expressions are validated through large-signal simulations using a GFET VerilogA analytical model and a commercial circuit simulator. The proposed expressions can be used during circuit design in order to predict the GFET biasing conditions at which linearity requirements are met. Index Terms—GFET, non-linearity, RF circuit. I. I NTRODUCTION RAPHENE based field effect transistors (GFETs) are nowadays considered as a technology option for future high-speed RF circuits and systems. Performance metrics such as high intrinsic transit frequency fT and transconductance gain gm have shown very competitive performance when compared to similarly sized devices of other technologies [1], [2], [3]. Another key performance metric that is important in RF systems and that must be carefully characterized in GFETs is the linearity. RF circuits must process weak signals in the presence of strong interference; therefore, they must exhibit high linearity performance. Non-linearities in the RF circuits are the source of several undesirable effects such as harmonic distortion, gain compression, intermodulation, cross-modulation, AM/PM conversion, DC offsets, etc [4]. Therefore, it is of paramount importance to study and characterize the intrinsic non-linearities of the GFET devices. Initial measurements of linearity of GFETs have shown that is possible to achieve good linearity performance [5]. However, an analytic study that allows to identify the GFET linearity under different design parameters and biasing conditions is required. Fig. 1 shows the small-signal representation of the GFET. The small-signal representation assumes that the components are linear. However, the capacitances Cgs , Cgd , transconductance gm , and output resistance ro are in fact non-linear G Manuscript received March 12, 2014. Support from the European Commission through a STREP project (GRADE, No. 317839), an ERC Advanced Investigator Grant (OSIRIS, No. 228229), and an ERC Starting Grant (InteGraDe, No. 307311) as well as the German Research Foundation (DFG, LE 2440/1-1) is gratefully acknowledged. S. Rodriguez, A. Smith, S. Vaziri, M. Ostling, and A. Rusu are with the KTH Royal Institute of Technology, School of ICT, Kista, Sweden (email: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]) M. C. Lemme is with the University of Siegen, Graphene-based Nanotechnology, Germany (email: [email protected]) 1 D G + G Cgd D gmV 1 V1 Cgs - S ro S Fig. 1. Non-linear small-signal representation of GFET devices. components. The capacitors are storage elements which exhibit memory effects. Their non-linearity is dynamic and as can be expected, its effect is more visible at high frequencies. The parameters gm and ro have a memoryless behavior and therefore their non-linearities are static. The effect of the nonlinearity of ro depends mainly on the loading conditions at the drain of the device. In most common cases, there are impedances smaller than ro loading the drain. Therefore, the impact of the non-linearities of ro is generally reduced. The non-linearity of gm , on the other hand, can not be reduced unless negative feedback is intentionally applied at the expense of noise and gain degradation. The non-linearity of gm , in fact, places a fundamental limit on the total non-linearity of the device. This paper introduces closed expressions for the second and third order static non-linearity of gm which are the main concerns in RF applications. II. T RANSCONDUCTANCE N ON - LINEARITY The static non-linearity at the drain current can be approximated by using a Taylor expansion polynomial: 2 3 n ID = a1 vin (t) + a2 vin (t) + a3 vin (t) + ... + an vin (t) (1) where ID is the drain current, and vin is a input voltage signal at the gate. The first three coefficients (a1 , a2 , a3 ) generally dominate the non-linearities for small signals. Higher order terms appear when the input signals are large enough so that the device leaves the saturation region and stops acting as an amplifier. This condition is known as clipping and can be avoided by ensuring proper signal levels at the input. The first terms can be found by differentiating (1) and solving for the unknown coefficients: 1 δ 2 ID 1 δ 3 ID δID a2 = a = (2) a1 = 3 2 3 δvin v=0 2 δvin 6 δvin v=0 v=0 The drain current in GFETs can be expressed as [6] : ID = µW CT OP (Vef f − VDSi /2) p p µ πCT OP /e Vef f − VDSi /2 ω L/VDSi + (3) 2 where µ is the mobility, W the transistor width, L the transistor length, CT OP is the top oxide capacitance density, e the elementary charge, ω is obtained from the surface phonon energy of the substrate h̄ω, and Vef f = VGSi + VT H,0 . The zero bias threshold voltage VT H,0 = eNf /CT OP accounts for the shift in the Dirac point due to the doping level Nf . Equation (3) is valid for the first triode and saturation/negative resistance regions when Vef f > VDSi /2 and ∆2 /πh̄2 vf 2 ≪ π|QN ET,AV |/e. By performing several substitutions, (3) can be expressed as: ID = Ax √ L/VDSi + B x (4) p where A = µW CT OP , B = ωµ πCT OP /e, and x = Vef f − VDSi /2. The coefficients a1 − a3 are found by taking derivatives of (4) with respect to the variable x (δx = δVef f = δVGSi ), and replacing the results in (2). Accordingly, the polynomial coefficients are: √ AVDSi (2L + BVDSi x) (5) a1 = √ 2 2 (L + BVDSi x) √ AVDSi B + 3BLVDSi x a2 = − √ 3 8x (L + BVDSi x) 2 a3 = 2 VDSi x √ 2 2 L2 + B 2 VDSi x + 4BLVDSi x ABVDSi √ 4 16x3/2 (L + BVDSi x) ∆IM2 = (7) The second and third order harmonic distortion levels (HD2 and HD3 ) produced by a single input tone vm cos (ω1 t) are found by calculating the ratio of the output currents at the harmonics frequencies (2ω1 , 3ω1 ) to the output current at the fundamental frequency ω1. The second harmonic distortion is given by: v v L2 √m √ − m 4x 2x (L + BVDSi x) (2L + BVDSi x) 3 a3 2 v 4 a1 m (14) C. Second and Third Order Intercept Points While the HD2 , HD3 , ∆IM2 , and ∆IM3 allow quick estimations of the distortion levels for a given input voltage vm , they are not suitable as figures of merit for comparing the linearity performance. These comparisons are normally done using the so-called second and third order intercept points (AIIP 2 , AIIP 3 ). The IIP2 is defined as: AIIP 2 = a1 a2 √ 8L2 x √ BVDSi (3L + BVDSi x) (16) (17) The AIIP 3 is defined as: The third harmonic distortion is: 1 a3 2 v (10) 4 a1 m ! 2 2 BVDSi xB 2 VDSi + L2 B 2 LVDSi + HD3 = 8x 32x3/2 (11) h √ i √ 2 2 2L + BVDSi x × vm L + BVDSi x (13) ! 2 2 BVDSi xB 2 VDSi + L2 B 2 LVDSi + ∆IM3 = 8x 32x3/2 (15) h √ 2 √ i 2 L + BVDSi x 2L + BVDSi x × 3vm AIIP 2 = 4x + HD3 = (12) The third order intermodulation distortion (∆IM3 ) produced by two input tones vm cos (ω1 t) and vm cos (ω2 t) is found by calculating the ratio of the output intermodulation product at (2ω1 − ω2 , 2ω2 − ω1 ) to the output at any of the fundamental frequencies (ω1 ,ω2 ): (8) v L2 v √m √ − m (9) HD2 = 8x 4x (L + BVDSi x) (2L + BVDSi x) a2 vm a1 ∆IM2 = (6) A. Second and Third Harmonic Distortion 1 a2 vm 2 a1 The second order intermodulation distortion (∆IM2 ) produced by two input tones vm cos (ω1 t) and vm cos (ω2 t) is found by calculating the ratio of the output intermodulation product at ω1 ± ω2 to the output at any of the fundamental frequencies (ω1 ,ω2 ): ∆IM3 = Once (5), (6), and (7) are substituted in (1), the resulting polynomial depends only on technology parameters and biasing voltages, and can be used to calculate the harmonic and intermodulation distortion of GFET devices. HD2 = B. Intermodulation Distortion AIIP 3 = s 4 a1 3 a3 AIIP 3 = s √ 2 √ 32x3/2 (L + BVDSi x) (2L + BVDSi x) √ 2 x + 4BLV 3BVDSi (L2 + B 2 VDSi DSi x) (18) (19) 3 TABLE I S IMULATED AND C ALCULATED L INEARITY 0 Simulated Calculated -100 I (dB) HD2 -57 dB -55.6 dB D HD3 -108 dB -105 dB -200 1st -300 Name 0 2nd 1 3rd 2 3 4 Frequency (kHz) 5 Fig. 2. Single-tone harmonic distortion test. -50 Simulated Calculated 1st ΔIM2 -49.6 dB 2nd -200 -250 -51 dB ΔIM3 -95.5 dB -150 D I (dB) -100 0 -96.1 dB 3rd 3rd 5 2nd 10 15 Frequency (kHz) 20 25 Fig. 3. Two-tone intermodulation test. D. Validation of Linearity Expressions The best way to validate the proposed linearity expressions is to compare the linearity metrics calculated by using these expressions with linearity measurements on GFET devices. When such measurements are unavailable, an alternative approach is to estimate these linearity metrics by performing large-signal time-domain transient simulations using transistor models. A caveat of this approach is that the accuracy of these estimations depends on how accurate the transistor model is. In this work, linearity metrics are estimated by performing large-signal simulation using a commercial circuit simulator (Cadence Spectre) and the GFET Verilog-A model from [7]. This model has been successfully used and verified by using measurements of differently sized GFETs fabricated by different groups. The test device is a 440 nm length, 1 µm width GFET from [8]. The model parameters are Nf ≈ 0 (VT H,0 ≈ 0 V), εr = 3.5, TOX = 8.5 nm (CT OP = 3.6 × 10−3 F/m2 ), µ = 7000 cm2 V−1 s−1 , ∆ = 66.8 meV, and h̄ω = 56 meV. The GFET is biased at VDS = 0.4 V and VGS = 1.5 V. Single and two-tone periodic-state simulations are performed in order to obtain the harmonic content of the drain current. The amplitude of the input signals vm is set at 20 mV. The frequency of the input signal for the single-tone test is 1 kHz while the frequencies for the two-tone test are 10 kHz and 11 kHz. Fig. 2 and Fig. 3 show the simulated spectrum content of Calculated Simulated Simulated Technology GFET GFET CMOS HD2 -55.6 dB -57 dB -45.7 dB HD3 -105 dB -108 dB -96.7 dB ∆IM2 -49.6 dB -51 dB -39.7 dB ∆IM3 -95.5 dB -96.1 dB -87.2 dB AIIP 2 15.7 dBV 17 dBV 5.7 dBV AIIP 3 13.8 dBV 14 dBV 9.6 dBV the drain current for the single-tone and two-tone tests, and the simulated and calculated distortion levels. It can be seen that the calculated values of HD2 , HD3 , ∆IM2 , and ∆IM3 predict very accurately the simulated distortion levels. The simulated second and third order intercept points are found by using the expressions AIIP 2,sim (dBV ) = 20log10 (vm ) + |IM2,sim |(dB), and AIIP 3,sim (dBV ) = 20log10 (vm ) + |IM3,sim |/2(dB). Table I shows a summary of the calculated and simulated linearity metrics. In addition, the table shows simulated linearity metrics for an equally sized NMOS device (440 nm lenght, 1 µm width) which was biased at the same VDS and VGS voltages as the test GFET. The NMOS device belongs to a 0.15µm CMOS commercial process and these metrics were extracted using the same large-signal simulations in Cadence Spectre. It can be appreciated that the GFET device outperforms the MOS device under similar conditions. This is a very encouraging result that shows the potential of GFET devices for highly-linear RF circuits. III. C ONCLUSIONS This paper has presented analytical expressions for the GFET transconductance non-linearity, which is the main source of distortion. The proposed expressions can be efficiently used to predict the linearity performance metrics of GFETs under different technology parameter values and biasing conditions. These expressions enable to perform comparisons of linearity performance of GFETs with other transistor technologies. As an example, a linearity comparison between a GFET and a CMOS device was performed. The comparison shows that the GFET outperforms its similarly sized CMOS counterpart. Therefore, GFET devices can potentially be used to design highly-linear RF circuits. R EFERENCES [1] Y.-M. Lin et al., “Enhanced Performance in Epitaxial Graphene FETs With Optimized Channel Morphology,” IEEE Electron Device Lett., vol. 32, no. 10, pp. 1343–1345, 2011. [2] Y. Wu et al., “Record high RF performance for epitaxial graphene transistors,” in Proc. IEEE Electron Devices Meeting (IEDM), Sep. 2011, pp. 23.8.1–23.8.3. [3] L. Liao et al., “High-speed graphene transistors with a self-aligned nanowire gate,” Nature, vol. 467, no. 7313, pp. 305–308, Sep. 2010. [4] B. Razavi, RF Microelectronics, 2nd ed. Prentice Hall, 2012. [5] K. A. Jenkins et al., “Linearity of graphene field-effect transistors,” Appl. Phys. Lett., vol. 103, no. 17, pp. 173 115–173 115–4, 2013. 4 [6] S. Rodriguez et al., “A Comprehensive Graphene FET Model for Circuit Design,” IEEE Trans. Electron Devices, vol. 61, no. 4, pp. 1199–1206, 2014. [7] S. Fregonese et al., “Scalable Electrical Compact Modelling for Graphene FET Transistors,” IEEE Trans. on Nanotechnology, vol. 12, no. 4, pp. 539–546, 2013. [8] I. Meric, C. Dean, and A. Young, “Graphene field-effect transistors based on boron nitride gate dielectrics,” in Proc. IEEE Electron Devices Meeting (IEDM), 2010, pp. 23.2.1–23.2.4.

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