A Practical Approach to Static Signal Electromigration Analysis

A Practical Approach to Static Signal Electromigration Analysis Nagaraj NS1, Frank Cano2, Haldun Haznedar2, Duane Young2 {nsnr,f-cano,h-haznedar,d-young}@ti.com 1 2 Texas Instruments, Inc. 8505 Forest Ln, MS 8635 Dallas, TX 75251 Texas Instruments, Inc. P.O. Box 1443, MS 714 Houston, TX 77251 ABSTRACT It is commonly thought that sweep-back effects would make electromigration (EM) a non-issue in signal lines. However this is only the case when the shape of the positive and negative current pulses are closely matched. Moreover, as performance pressures increase, the peak current values are exceeding the range for which electromigration models are valid. Thus, during the design of TI’s TMS320c6201 DSP chip, it was determined that limits needed to be placed on the current densities in signal-line segments, and that every net in the design should be checked. Dynamic current density analysis on all nets of a large design is computationally very expensive. In this paper, we describe a practical CAD methodology for a static, signal electromigration analysis for large cell-based designs. We present results and some observations from application of this methodology on the TMS320c6201. 1. INTRODUCTION level integration and the associated increasing complexity of designs [8,9], a static approach to resolving the signalEM analysis problem is needed. Dynamic analysis of current densities on millions of nets in a large design is computationally very expensive and impractical. This paper presents a design methodology to validate the current density in signal-line segments and vias for all signals in a VLSI design. Moreover, a floor planner based correct by construction methodology is proposed. This paper is organized as follows: Section 2 briefly discusses EM and its impact on signal lines. Section 3 covers the proposed methodology followed by a description of the flow in section 4. Results from application of the design methodology on the design of the TMS320c6201 DSP core are presented in section 5 followed by future enhancements in section 6 and conclusions in section 7. 2. BACKGROUND For some time it has been known that signal-line electromigration (EM) effects can be significant even in the presence of reverse-recovery effects [10]. Furthermore, as chip clock periods decrease relative to the average signal transition time, the Joule heating of signal lines increases and can drastically reduce the life time. In addition, with higher performance goals designers are creating circuits that exceed the peak current limits for which existing EM models are valid [2,3]. This all leads to the need to validate the EM reliability of signal lines. With market trends indicating higher levels of system Electromigration is caused by the transport of metal ions through a conductor resulting from the passage of an electric current. Reliability of metal interconnect is commonly described by a lifetime experiment on a set of lines to obtain the median time to failure (MTF), whose general expression is given by the Black’s formula [1] as follows: MTF = AJ − n exp( E / kT ) a where A is a material constant based on the structure and geometric properties of the conductor (A ≈ wt, where w is the width of the line and t is its thickness), J is the current density, Ea is the activation energy, k is the Boltzmann constant, and T is the temperature in Kelvin. A has dependence on geometry. It has been shown experimentally that the width dependence of MTF is a function of the grain size d of the film and the width of the conductor w. As w/d decreases, the MTF will increase due to the bamboo effect. The dependence of MTF on the line-width has significant implications from a design point of view and is th 35 Design Automation Conference ® Copyright ©1998 ACM 1-58113-049-x-98/0006/$3.50 (1) DAC98 - 06/98 San Francisco, CA USA usually characterized during the development phase of any new metallization process. For signal lines, the current in the interconnect alternates as the output of the driver switches. A positive current flows into the lead, whose peak value and duration is determined by the drive strength of the pull-up transistor and impedance characteristics of the load. Similarly, for negative excursions of the output. If the current pulse through the interconnect is bi-directional (both positive and negative pulses), an annealing effect referred to as sweep back will take place. Sweep back can be modeled by a recovery term r in the equation for the average current [10]. + − + − I avg = max( I avg , I avg ) − r ⋅ min( Iavg , Iavg ) (2) The value of r must be determined from experimental analysis of a given process and is typically between 0 and 1. I+avg can differ in magnitude from I-avg , yielding Iavg that is positive. Short-time failure of metal interconnect caused by current pulses [2,3] necessitates peak current density measurements for EM analysis. In addition, the exponential dependency of MTF on temperature necessitates limiting the maximum Joule heating that may occur due to the current flowing in a signal line. The temperature rise is proportional to the RMS current, and hence by limiting the RMS current one can limit the temperature rise. Thus, the EM guidelines implemented and used in the initial version of this flow were written in terms of limits for average, RMS and peak currents. For bi-directional pulses, Jrms, Javg and Jpeak for a particular metal system must be less than their maximum permitted values Jrms,max, Javg,max and Jpeak,max respectively. 3. METHODOLOGY DEVELOPMENT This section describes the overall methodology of the proposed signal-EM analysis flow and discusses some of the observations made during its development. Electromigration of signal lines through dynamic simulation of the full design is computationally expensive since it is difficult to activate all the signals for worst-case transitions. A static approach with good heuristics is more promising to ensure compliance of all the signals in a reasonable amount of time. 3.1 Current Density Verification The first step in the development process was to create a current density verification program that implemented the EM guidelines for the fabrication process. The inputs to the verifier were the calculated current density limits of the specific technology for each layer and via type, the maximum device cycle time, the simulated current wave- form from SPICE and the simulation cycle time. The output was the required width and via count for each layer and via type in the technology. Subsequently, the verifier was upgraded to accept the actual route segment widths corresponding to each current waveform and identify cases where the width was not sufficient. The current density checks implemented were based on the effects mentioned in the introduction: 1) average current limit with recovery; 2) RMS current limit; and 3) peak current limit. 3.2 Driver Modeling: Analytical vs. Simulation The first attempt to model the driver interconnect was to extend the work described in [4]. This approach was based on modeling each CMOS cell by a linear resistance and applying a Driving Point Admittance (DPA) model of the interconnect at its output. Though this approach was performing reasonably well on average and RMS current densities, it failed to accurately model the peak current. Hence, a transistor level simulation approach was adopted. This was easily implemented by extending the existing SPICE-based cell characterization environment. The resulting system excites all possible input vectors and runs SPICE to obtain current waveforms and post-process these waveforms using the verifier described in Section 3.1. CI D riv e r D riv e r CI + CL CL (a ) (b ) Figure 1. Distributed-RC and Lumped C models 3.3 Load Model: Lumped Capacitance vs. Distributed Capacitance The next step in flow development was to choose a proper model for the interconnect load. A simulation was setup to determine how well a lumped capacitance would model the three current properties (average, RMS and peak) versus a point-to-point distributed RC network. The circuits in Figure 1 were used for this comparison. In both circuits the current supplied by the driver was monitored. Reasonable transistor parameters and parasitic parameters were selected consistent with a 1um metal pitch/.25um gate length CMOS process. Figure 2 shows the difference in the various current properties at the driver output when the load is modeled as a single lumped capacitor versus modeled as a distributed 120 Lump C, W=1.00 RC, W=1.00 Lump C, W=2.00 RC, W=2.00 100 Scaled Current (mA) RC network. (All parameters in the graphs have been scaled to protect proprietary data). Figure 2(a), as expected, shows that the average current at each simulated length for the two circuits was identical. Thus, lumped capacitance is a very accurate model for average current. Figure 2(b) shows that significant error can be introduced in the RMS current calculation if the resistance of the line is not modeled. Likewise, Figure 2(c) shows an even larger error occurs in peak current when the resistance is not modeled. From this data, it was concluded that the full RC effects of the interconnect must be modeled to get accurate RMS and peak currents. 80 60 40 20 0 0.0 0.1 0.3 0.4 0.5 0.6 0.8 0.9 1.0 Scaled Length (mm) 0.70 Fig 2(c) Scaled Current (mA) 0.60 Lump C, W=1.00 RC, W=1.00 Lump C, W=2.00 RC, W=2.00 0.50 0.40 Figure 2. Average (a), RMS (b) and peak (c) currents at the driver as a function of interconnect length for a point-topoint connection. Comparison of lump capacitance model to distributed interconnect model. Two typical route widths are shown. 0.30 0.20 0.10 Figures 3 and 4 are included here for additional insight into the behavior of RMS and peak current as a function of the end point load and route length. These plots reemphasize the effect of resistance in improving the EM performance of a design. Of particular note is that the peak and RMS currents will decrease with increase in interconnect length. This is due to the resistive shielding that the increase in length provides between the driver and the end point load. 0.00 0.0 0.1 0.3 0.4 0.5 0.6 0.8 0.9 1.0 Scaled Length (mm) Fig 2(a) 14.0 Lump C, W=1.00 RC, W=1.00 Lump C, W=2.00 RC, W=2.00 10.0 16.0 8.0 Cend=0.08 Cend=0.50 Cend=1.00 14.0 6.0 12.0 Scaled Current (mA) Scaled Current (mA) 12.0 4.0 2.0 0.0 0.0 0.1 0.3 0.4 0.5 0.6 0.8 0.9 1.0 10.0 8.0 6.0 4.0 Scaled Length (mm) 2.0 Fig 2(b) 0.0 0.0 0.1 0.3 0.4 0.5 0.6 0.8 0.9 1.0 Scaled Length (mm) Figure 3. End point load effects on RMS current at the driver as a function of point-to-point interconnect length. design, the methodology was cell based, it was straight forward to extend the cell characterization environment to generate a maximum load for each driver given a specified minimum route width and via count. The resulting table of maximum safe loads was used along with extracted total capacitance information to determine which instances needed to be fully simulated. 120 Cend=0.08 Normalized Current (mA) 100 Cend=0.50 Cend=1.00 80 60 40 20 0 0.0 0.1 0.3 0.4 0.5 0.6 0.8 0.9 1.0 Normalized Length (mm) Figure 4. End point load effects on peak current at the driver as a function of point-to-point interconnect length. 3.4 Full RC network or DPA Model The Driving Point Admittance(DPA) model [5] portrayed in Figure 5 approximates the driving point characteristics of interconnect RCs as a pi-model. Simulations have shown that the DPA model is sufficiently accurate to model average, RMS, and peak current densities for the current process technology and reasonable interconnect lengths. A capability in RICE [6] can be used to compute the DPA parameters at the driver output. This is done at no extra computational cost since RICE computes the DPA during effective-capacitance calculation phase in interconnect delay analysis. DPA-based analysis helps in accurately finding current densities at the driver output. The DPA model allows for screening of driver circuits to some minimum criteria. However, use of the DPA model does not fully validate the layout since the model does not retain any layer or width information. In order to properly validate the layout, the full RC network of the signal of interest must be simulated. Later enhancements to the extraction postprocessing tools allowed upgrading the flow so that each segment of the signal line that had varying layer or width was checked for compliance with the guidelines. 3.5 Pruning The above detailed analysis is very time consuming if tens or hundreds of thousands of nets are to be validated. Some means of reducing the set of nets for detailed analysis was needed. As can be seen in Figures 2 (b) and (c), the lumped capacitance model for the interconnect yields an upper bound on the three current characteristics. Since for this Figure 5. Illustration of DPA modeling at the driver output. For peak current pruning, the effective capacitance computed during interconnect delay analysis[6] was also investigated for use as a first pass filter. It was found to be an optimistic model for peak current. 3.6 Reducing Pessimism Even though accounting for resistance of the interconnect helps in eliminating false failures, it still may not be sufficient. It was observed that input transition times can also influence the current characteristics of the output. Assuming worst case input transition times (fastest rise/fall times) can be overly pessimistic. Hence, the actual input rise and fall times as computed during normal interconnect delay analysis can be used for more accurate results. This helped in reducing the number of false violations. 4. DESCRIPTION OF THE CAD FLOW The CAD flow used to perform the static signal-EM analysis is shown in Figure 6. Key features of this flow are: • All possible input combinations causing output transitions are exercised to determine the worst-case failures. • The complete RC network is analyzed at the driver output. Peak, average and RMS current densities are validated for each interconnect layer, via and contact inside the driver. • Bamboo and non-bamboo lines are identified based on interconnect width and separate current density thresholds are used in determining peak violations. cients are specified by the SPICE conditions file. Tightening of the tolerance values in SPICE resulted in a 10%15% increase in the peak current values. • For pre-layout analysis, the interconnect can be collapsed to its DPA model. DPA-based analysis could also be used for same-width routes. • First-pass filter based on lumped capacitance is used to reduce the number of cases that need to be analyzed. Actual input-edge rates are used to reduce the pessimism in current density computation. During pre-layout stages of the design, RC estimates from the floor planner could be used to obtain minimum widths and via count constraints. These constraints could then be forward annotated to the detail routers to minimize layout iterations. • Toggle frequency can be set on a signal-by-signal basis. • To expedite the execution, simulation and analysis is distributed across the network. • Incremental analysis can be performed when current density limits for a given technology change, without performing time-intensive simulations. Layout Timing Templates Signal-wise RC Network Generator Driver Subcircuits Parasitic Extraction Look-Up Table Signal Cycle Times SPICE Deck Parasitic Database RICE Delay Calculator Net Summary Report Driver Cmax Threshold Ctotal Filter Suspect Net List SPICE Conditions SPICE Driver Script SPICE 5. RESULTS The design flow in its final form was used to validate a high performance DSP design. The design consisted of static CMOS in two layout styles. Half of the layout area was dedicated to standard cell place and route. The other half of the layout was composed of semi-custom cell based datapath blocks. The design was targeted at a 1.0um metal pitch, 0.25um gate length CMOS process. The flow was setup to be run twice at two interconnect process corners. One corner was with thick-wide metal and the other was with thin-narrow metal. The metal interconnect sheet resistances were set consistent with the metal thickness. As well, the thickness/width assumptions were also taken into account in the calculation of the current density limits for the verification flow. The other conditions of voltage, temperature and transistor strength were chosen to be worst case for EM lifetime. Current Density Verifier Thick-Wide Metal % Signals w/ % Pass1 w/ Violations Violtions Block Type % Signals Fail Pass1 Standard Cell 24% 8% 31% Datapath 8% 3% 65% Inter-block 35% 1% 4% Current Waveforms Error Report or Required Width Report Figure 6. Design flow for signal-EM checker 4.1 Salient Aspects of the Flow In this section, salient aspects of the CAD flow are discussed. The parasitic extraction includes extraction width and layer information for each segment in the RC network. Total capacitance on the driver output and also input transition times for each instance input pin are obtained during the RC-delay calculation. The total capacitance thresholds are determined for each library cell used in the design. This is a design-independent procedure and is performed only once for a given cell library. Vectors designed to exhaust all valid combinations of driver input-output transitions are derived from the cell characterization timing templates. The simulation frequency for any signal could be specified in the signal frequency file. Design corners such as transistor models, temperature, supply voltage and metal temperature coeffi- Block Type Standard Cell Datapath Inter-block % Signals Fail Pass1 24% 8% 33% Thin-Narrow Metal % Signals w/ % Pass1 w/ Violations Violations 1% 5% 5% 40% 1% 3% Table 1 Result statistics showing effectiveness of capacitance filter Table 1 summarizes the results from running the flow on the standard cell, datapath and top level interconnect. The first column indicates the percentage of all signals that failed the total capacitance filter. The second column is the percentage of all signals that had failures on them. The third column is the percentage of signals that failed the total capacitance filter and also had violations on them. One intriguing observation is that more violations were reported for thick-wide metal than for thin-narrow metal. This was analyzed and determined to be due to the increase in RMS and peak currents when the resistance of the interconnect decreased and the capacitance increased. Similar effects can be seen in Figures 3 and 4 in that for some cases the RMS and peak currents decrease with increasing length (resistance). For the standard cell portion of the design, the detailed analysis with SPICE took an average of 4.5 min/signal. For the top level route, the average was much longer, at 24 min/signal. For the current limits selected from the target process, the design that was analyzed contained primarily peak and RMS current violations. In only one case did a circuit need to be modified for an average current violation. 6. FUTURE ENHANCEMENTS 6.1 Additional Filtering numerical solutions to obtain better accuracy vs. speed tradeoff with respect to SPICE. In order to get a first-pass clean design, it will be necessary for constraints to be placed on synthesis and physical design tools in future. 8. ACKNOWLEDGEMENTS We would like to thank Prof. Larry Pileggi for providing us with the RICE software, which has been incorporated in the TI internal parasitics analysis environment known as Parasitic Workbench (PWb). We also would like to thank Tony Leigh, Jim Gallia, Joe McPherson and Larry Ting for providing expert advice and support during this work. Special thanks also go to the key user, Steve Weigand, for detailed feedback. 9. REFERENCES Currently all signals that fail the lumped capacitance threshold are scheduled for full RC simulation. For nets with a large number of elements, the run times of the signal may approach hours. In these cases, the DPA model could be run first, and the width and layer data could be scanned to see if any nets could possibly fail. Only then, if there was an element with a maximum current limit less than the current at the driver output, would the signal be submitted for detailed analysis. [1] Black, J. R. “Electromigration Failure Modes in Aluminum Metallization for Semiconductor Devices.” Proceedings of IEEE, 57, p. 1587, 1969. 6.2 Analytical Solution [4] Nagaraj NS, “Approximate computation of signal characteristics of on-chip interconnect.” Proc. of ISCAS 1994 Now that a comprehensive SPICE based benchmark is available, analytical and/or numerical solutions will be explored. Accurate modeling of the driver is needed to address the high degree of non-linearity in peak current characteristics. 7. CONCLUSION [2] Maiz, J. A. “Characterization of Electromigration under Bidirectional (BX) and Pulsed Unidirectional (PDC) Currents,” in Proceedings of 27th Annual International Reliability Physics Symposium, IEEE, 1989, pp, 220-228. [3] Murguia, J. E., and Brenstien, J. B., “Short-Time Failure of Metal Interconnect Caused by Current Pulses,” IEEE Electron Device Letters, p. 481-483 ,1993 [5] O’Brien, P., “Modeling of Driving Point Characteristics of Resistive Interconnect for accurate delay estimation.,” Proc. of ICCAD 1991, pp 512-515 [6] Ratzlaff, C. L., and Pillage, L. "RICE: Rapid Interconnect Circuit Evaluation Using AWE,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. Vol. 13. No. 6. 1994. A methodology has been presented for static EM analysis on signal lines in deep submicron designs. Results from application of this methodology on TI’s TMS320c6201 DSP chip have been presented. The proposed methodology offers a practical solution to the EM analysis on signal-line segments. [7] Scarpulla, et al. “Reliability of Metal Interconnect After a High Current Pulse,” Electron Device Letters, 1996 Presently SPICE simulations to obtain current waveforms is distributed across the network to improve throughput. We are looking into accurate driver modeling from a current characteristics viewpoint and faster analytical and/or [10] Ting, L, May, J.S., Hunter, W.R., and McPherson, J.W., “AC Electromigration Characterization and Modeling of Multilayered Interconnections,” Proceedings of IRPS, pp. 311-316 1993. [8] The National Technology Roadmap for Semiconductors, Semiconductor Industry Association (SIA), 1997 [9] "Design Needs for the 21st Century: White Paper," Semiconductor Research Center (SRC), September, 1994