2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021
In this work we present a technology for dynamically introducing fault structures into digital tw... more In this work we present a technology for dynamically introducing fault structures into digital twins without the need to change the virtual prototype model. The injection is done at the beginning of a simulation by dynamically rewiring the involved netlists. During the simulation on a realtime platform, faults can be activated or deactivated triggered by sequences, statistical effects or by events from the real world. In some cases the fault structures can even be auto-generated directly from a formal specification, which further automates the development process for safety-relevant systems. The approach is demonstrated at a SystemC/ SystemC AMS virtual prototype of a safety-critical sub-systems which runs on a dSPACE real-time hardware.
2011 Design, Automation & Test in Europe, 2011
Layout generation remains a critical bottleneck in analog circuit design. It is especially distra... more Layout generation remains a critical bottleneck in analog circuit design. It is especially distracting when re-using an existing design for a similar specification or when transferring a working design to a new technology. This paper presents a new methodology for layout generation of analog circuits that is based on a modular circuit design and a so-called "executable design flow description". This is created once manually and allows to describe the layout in a technology independent and parameterizable manner assuring a consistent view of circuit and layout design. Complex layouts can be created in negligible time, achieving an early involvement of layout effects in the circuit design. Furthermore, the parameterization of the design description allows simplified technology transfer and seamless access to sizing tools.
2016 IEEE International Reliability Physics Symposium (IRPS), 2016
We experimentally and theoretically investigate the NBTI degradation of pMOS devices due to analo... more We experimentally and theoretically investigate the NBTI degradation of pMOS devices due to analog stress voltages and thus go beyond existing NBTI studies for digital stress. As a result, we propose a physics-based compact model for analogstress NBTI which builds upon the extensive TCAD analysis of our ultra-short-delay experimental data. The numerical efficiency of the compact model allows its direct coupling to electric circuit simulators and permits to accurately account for NBTI degradation already during circuit design. Our model enables the calculation of the time-dependent NBTI variability of single device and of circuit performance parameters. We demonstrate our NBTI model on an operational amplifier and calculate the mean drift and variability of its offset voltage.
2018 48th European Solid-State Device Research Conference (ESSDERC), 2018
On the example of a 28nm SRAM array, this work presents a novel reliability study which takes int... more On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress via the piezoresistive effect. The stability of each single SRAM cell is simulated using static noise margin. Finally, the whole array's behavior is reproduced by including device parameter variations in Monte-Carlo simulations. The results show good agreement with corresponding experiments in which mechanical stress was introduced into the SRAM array by indentation. This validates the presented simulation method for future use in the design of electronic products, especially for harsh environment applications, where high stress is expected.
2016 IEEE International Integrated Reliability Workshop (IIRW), 2016
We present a BTI compact model that is able to account for the complex BTI stress patterns encoun... more We present a BTI compact model that is able to account for the complex BTI stress patterns encountered in complex electronic circuits. Such stress patterns are composed of various blocks corresponding to different circuit operation states, protocol modes or input conditions, and the blocks repeat within a composite, hierarchical structure. The present work extends a previously introduced physics-based accurate NBTI modeling while preserving its numerical efficiency. We provide insight into some principal characteristics of BTI degradation under hierarchical stress patterns, such as a non-trivial dependence on multiple duty cycles. In particular, the NBTI degradation can sensitively depend on the temporal sequence of NBTI stress blocks, and building a model on just the average stress or on stress histograms can be misleading. An SRAM cell example demonstrates this method and compares the cell's BTI failure statistics for two different hierarchic-periods stress patterns.
2020 IEEE International Integrated Reliability Workshop (IIRW), 2020
To verify the reliability of electronic circuits and systems in automotive applications, qualific... more To verify the reliability of electronic circuits and systems in automotive applications, qualification according to the industry-standards, such as AEC-Q100, is state of the art. But will it be sufficient for future applications? Simulationbased reliability assessments in IC and system development are intended to complement qualification and allow efficient investigations of product reliability. Aging simulations for analog circuits have been available for years, but are hardly used. This article discusses degradation models as one bottleneck, outlines different requirements and approaches, and points to standards that could be a future solution.
2018 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP), 2018
In this paper a method for dynamic fault injection and fault simulation as well as its applicatio... more In this paper a method for dynamic fault injection and fault simulation as well as its application to MEMS based sensor systems is described. The prerequisite for this approach is the availability of accurate, but numerically efficient models for the MEMS element. Simulations based on SystemC and SystemC AMS are suitable to analyze the nominal behavior of complex systems including electronics and the mechanical behavior of the MEMS elements [1], [2]. They offer capabilities to represent analog and digital hardware as well as software and nonelectrical components in one simulation environment. Especially for the modelling of mechanical structures, dedicated modelling algorithms like model order reduction [3], [4] have to be applied to ensure high numerical efficiency.
Proceedings of the International Conference on Computer-Aided Design, 2018
Electromigration (EM) is becoming a progressively severe reliability challenge due to increased i... more Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM veri cation to robust (pro-active) EM-aware design-where the circuit layout is designed with individual EM-robust solutions-is urgently needed. This tutorial will give an overview of EM and its e ects on the reliability of present and future integrated circuits (ICs). We introduce the physical EM process and present its speci c characteristics that can be a ected during physical design. Examples of EM countermeasures which are applied in today's commercial design ows are presented. We show how to improve the EM-robustness of metallization patterns and we also consider mission pro les to obtain application-oriented current-density limits. The increasing interaction of EM with thermal migration is investigated as well. We conclude with a discussion of application examples to shift from the current post-layout EM veri cation towards an EM-aware physical design process. Its methodologies, such as EM-aware routing, increase the EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit's reliability.
Die zunehmende Verbreitung von Elektronik im Alltag und die weitere Verringerung der Strukturgros... more Die zunehmende Verbreitung von Elektronik im Alltag und die weitere Verringerung der Strukturgrosen stellen neue Anforderungen an die Zuverlassigkeit und Verfugbarkeit integrierter Schaltungen. Die Arbeit zeigt ein systematisches Vorgehen zur Modellierung des funktionalen Schaltungsverhaltens und erganzt es um neue Verfahren zur Berucksichtigung zuverlassigkeitsrelevanter Schaltungseigenschaften. Etablierte Verfahren aus der Mechanik zur Behandlung der Zuverlassigkeit werden auf die Degradationseffekte integrierter Halbleiterbauelemente angewandt. Entsprechende Lebensdauermodelle zu relevanten Degradationsmechanismen sind dargestellt. Ausgehend davon werden allgemeine Mase zur Zuverlassigkeitsbewertung von Bauelementen unter Anwendungsbedingungen abgeleitet. Die Diskussion von Methoden zur Analyse der Zuverlassigkeit ganzer Schaltungen im Entwurf rundet die Darstellung ab. Die entwickelten Verfahren dienen der Unterstutzung eines schnellen und fehlerfreien Entwurfs sicherer und zuve...
Integrierte Halbleiterelektronik wird zukünftig immer mehr Lebensbereiche durchdringen. Für hohe ... more Integrierte Halbleiterelektronik wird zukünftig immer mehr Lebensbereiche durchdringen. Für hohe Leistung bei geringstem Energieverbrauch und minimalen Abmessungen kommen neueste Technologie-Generationen zum Einsatz. Die Anwendungen reichen vom Consumer-Bereich bis hin zu sicherheitskritischen Bereichen wie Automotive und Industrie 4.0. Allerdings bringen neue Halbleiter-Technologien auch neue Materialien und neue physikalische Effekte mit sich, die die Zuverlässigkeit der Elektronik und des Gesamtsystems beeinträchtigen. Es wird daher immer wichtiger, die Auswirkungen von zuverlässigkeitsrelevanten Effekten einschätzen und im Entwurf integrierter Elektronik berücksichtigen zu können. Im Beitrag werden grundsätzliche Herangehensweisen zur Absicherung der ElektronikZuverlässigkeit unterschieden. Im Mittelpunkt der Betrachtungen stehen intrinsische Degradationseffekte, die zum Ausfall von Elektronik über der Zeit führen können. Es werden Verfahren vorgestellt, die es gestatten, solche...
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW), 2015
This paper presents a control-theoretic driven approach to the automatic generation of test signa... more This paper presents a control-theoretic driven approach to the automatic generation of test signals for analog circuits or systems. It is based on the adaption of a tracking control structure for the task of generating test signals aimed at manufacturing test for a finished circuit design. The approach will be derived and its functionality is demonstrated using circuit examples. The integration of the proposed approach within a more general test development procedure for improving the fault coverage is explained.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016
Process variations and atomic-level fluctuations increasingly pose challenges to the design and a... more Process variations and atomic-level fluctuations increasingly pose challenges to the design and analysis of integrated circuits by introducing variability. Although several approaches have been proposed to deal with the inherent statistical nature of circuit design, we consider them incomplete with two important aspects often being insufficiently addressed: non-Gaussian distributions and highly correlated parameters. To address these points, we propose a fully multivariate and non-Gaussian approach based on an arbitrary model. A subset of the model parameters is treated as a multi-dimensional random variable, which is represented by a combination of generalized lambda distributions and Spearman rank correlation matrices-a very general approach with nearly arbitrary freedom in distribution shapes and parameter correlations. In our application scenarios, we show that such a model is able to fully and accurately capture variability in device compact models and standard cell performance models. Finally, we present adapted analysis methods making use of these models in circuit simulations and in efficient gate level analyses of digital circuits with high accuracy.
2014 IEEE International Integrated Reliability Workshop Final Report (IIRW), 2014
We propose a circuit-level modeling approach for the threshold voltage shift in PMOS devices due ... more We propose a circuit-level modeling approach for the threshold voltage shift in PMOS devices due to the negativebias temperature instability (NBTI). The model is suitable for application in analog circuit design and reproduces the results of existing digital-stress NBTI models in the limit of two-level stress signals. It accounts for recovery effects during intervals of low stress, and it predicts a stress-pattern dependent saturation of the degradation at large operation times. Since the model can be solved numerically in an efficient way, we have direct access to the threshold voltage shift at arbitrary times, in particular to the exact solution at large operation times, without any approximation. We implement the model via the Cadence Spectre URI. Finally, we make use of the model to compare the aging properties of several analog stress patterns. We furthermore present the results of an analog circuit-level NBTI simulation of a ring oscillator.
For analog and mixed-signal circuit design a modeling methodology is needed which is well suited ... more For analog and mixed-signal circuit design a modeling methodology is needed which is well suited to the requirements of a structured synthesis flow. It ensures that the intended specification is met without over-design. Behavioral models are able to provide circuit level knowledge on higher abstraction levels by including non-idealities and parasitics from the circuit realization, which allows realistic comparison of different architectures. At the same time these models are fast enough to explore design space and optimize specification translation with respect to system performance measures. This paper shows how numerical, analytical, and symbolic methods as part of an integrated modeling methodology are used for model generation, model parameterization, and model refinement in order to improve and accelerate analog circuit synthesis
With the ever increasing integration density of electronic circuits and devices thermal issues du... more With the ever increasing integration density of electronic circuits and devices thermal issues due to the Joule-effect become more and more important because they may yield increased power consumption, performance degradation, transient or persistent malfunction and reduced device life time. However, a number of difficulties is associated with "thermal aware electronics design". During the design of electronic circuits information on power dissipation of individual electronic elements must be calculated. This information together with layout and package data must be combined to setup and simulate thermal models for the device, which in turn must be connected in a suitable way to the electric network. Transistor models with a thermal pin are necessary to vary the temperature during dynamic simulations. The simulation of this model has to cope with the existence of largely disparate time scales for electrical and thermal effects. This article shows efficient ways for the gen...
Digitale Schaltungen werden heute in weiten Teilen automatisiert entworfen. Möglich ist das durch... more Digitale Schaltungen werden heute in weiten Teilen automatisiert entworfen. Möglich ist das durch den Syntheseprozess, der eine Spezifikation "Top-Down" automatisch in eine Implementierung umsetzt. Ein verleichbarer Syntheseprozess existierte für analoge Schaltungen bislang nicht. Dieser Beitrag beschreibt überblicksartig die im Rahmen des Clusterforschungsprojekts SAMS entwickelten Methoden, die erstmals einen nachweislich gangbaren Weg zur Synthese analoger Schaltungen beschreiben. Dabei wird eine Spezifikation zunächst interaktiv zu einer Struktur aus grundlegenden Schaltungsprimitiven (z. B. Operationsverstärker, etc.) verfeinert. Für diese grundlegenden Schaltungsprimitive werden dann mögliche Topologien erzeugt und automatisch verglichen. Die Machbarkeit wurde an zwei realistischen Beispielen aus der Industrie demonstriert.
The Web-based education methodology provides new chances and challenges to adopt interdisciplinar... more The Web-based education methodology provides new chances and challenges to adopt interdisciplinary expertise needed for mastering the design processes in key technologies as electronics and mi-cro-electro-mechanical systems (MEMS). Simulation should be an integral part in teaching, under-standing and design of complex systems. In this paper four courses are presented which include Web-based simulation capabilities in different physical domains.
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021
In this work we present a technology for dynamically introducing fault structures into digital tw... more In this work we present a technology for dynamically introducing fault structures into digital twins without the need to change the virtual prototype model. The injection is done at the beginning of a simulation by dynamically rewiring the involved netlists. During the simulation on a realtime platform, faults can be activated or deactivated triggered by sequences, statistical effects or by events from the real world. In some cases the fault structures can even be auto-generated directly from a formal specification, which further automates the development process for safety-relevant systems. The approach is demonstrated at a SystemC/ SystemC AMS virtual prototype of a safety-critical sub-systems which runs on a dSPACE real-time hardware.
2011 Design, Automation & Test in Europe, 2011
Layout generation remains a critical bottleneck in analog circuit design. It is especially distra... more Layout generation remains a critical bottleneck in analog circuit design. It is especially distracting when re-using an existing design for a similar specification or when transferring a working design to a new technology. This paper presents a new methodology for layout generation of analog circuits that is based on a modular circuit design and a so-called "executable design flow description". This is created once manually and allows to describe the layout in a technology independent and parameterizable manner assuring a consistent view of circuit and layout design. Complex layouts can be created in negligible time, achieving an early involvement of layout effects in the circuit design. Furthermore, the parameterization of the design description allows simplified technology transfer and seamless access to sizing tools.
2016 IEEE International Reliability Physics Symposium (IRPS), 2016
We experimentally and theoretically investigate the NBTI degradation of pMOS devices due to analo... more We experimentally and theoretically investigate the NBTI degradation of pMOS devices due to analog stress voltages and thus go beyond existing NBTI studies for digital stress. As a result, we propose a physics-based compact model for analogstress NBTI which builds upon the extensive TCAD analysis of our ultra-short-delay experimental data. The numerical efficiency of the compact model allows its direct coupling to electric circuit simulators and permits to accurately account for NBTI degradation already during circuit design. Our model enables the calculation of the time-dependent NBTI variability of single device and of circuit performance parameters. We demonstrate our NBTI model on an operational amplifier and calculate the mean drift and variability of its offset voltage.
2018 48th European Solid-State Device Research Conference (ESSDERC), 2018
On the example of a 28nm SRAM array, this work presents a novel reliability study which takes int... more On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress via the piezoresistive effect. The stability of each single SRAM cell is simulated using static noise margin. Finally, the whole array's behavior is reproduced by including device parameter variations in Monte-Carlo simulations. The results show good agreement with corresponding experiments in which mechanical stress was introduced into the SRAM array by indentation. This validates the presented simulation method for future use in the design of electronic products, especially for harsh environment applications, where high stress is expected.
2016 IEEE International Integrated Reliability Workshop (IIRW), 2016
We present a BTI compact model that is able to account for the complex BTI stress patterns encoun... more We present a BTI compact model that is able to account for the complex BTI stress patterns encountered in complex electronic circuits. Such stress patterns are composed of various blocks corresponding to different circuit operation states, protocol modes or input conditions, and the blocks repeat within a composite, hierarchical structure. The present work extends a previously introduced physics-based accurate NBTI modeling while preserving its numerical efficiency. We provide insight into some principal characteristics of BTI degradation under hierarchical stress patterns, such as a non-trivial dependence on multiple duty cycles. In particular, the NBTI degradation can sensitively depend on the temporal sequence of NBTI stress blocks, and building a model on just the average stress or on stress histograms can be misleading. An SRAM cell example demonstrates this method and compares the cell's BTI failure statistics for two different hierarchic-periods stress patterns.
2020 IEEE International Integrated Reliability Workshop (IIRW), 2020
To verify the reliability of electronic circuits and systems in automotive applications, qualific... more To verify the reliability of electronic circuits and systems in automotive applications, qualification according to the industry-standards, such as AEC-Q100, is state of the art. But will it be sufficient for future applications? Simulationbased reliability assessments in IC and system development are intended to complement qualification and allow efficient investigations of product reliability. Aging simulations for analog circuits have been available for years, but are hardly used. This article discusses degradation models as one bottleneck, outlines different requirements and approaches, and points to standards that could be a future solution.
2018 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP), 2018
In this paper a method for dynamic fault injection and fault simulation as well as its applicatio... more In this paper a method for dynamic fault injection and fault simulation as well as its application to MEMS based sensor systems is described. The prerequisite for this approach is the availability of accurate, but numerically efficient models for the MEMS element. Simulations based on SystemC and SystemC AMS are suitable to analyze the nominal behavior of complex systems including electronics and the mechanical behavior of the MEMS elements [1], [2]. They offer capabilities to represent analog and digital hardware as well as software and nonelectrical components in one simulation environment. Especially for the modelling of mechanical structures, dedicated modelling algorithms like model order reduction [3], [4] have to be applied to ensure high numerical efficiency.
Proceedings of the International Conference on Computer-Aided Design, 2018
Electromigration (EM) is becoming a progressively severe reliability challenge due to increased i... more Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM veri cation to robust (pro-active) EM-aware design-where the circuit layout is designed with individual EM-robust solutions-is urgently needed. This tutorial will give an overview of EM and its e ects on the reliability of present and future integrated circuits (ICs). We introduce the physical EM process and present its speci c characteristics that can be a ected during physical design. Examples of EM countermeasures which are applied in today's commercial design ows are presented. We show how to improve the EM-robustness of metallization patterns and we also consider mission pro les to obtain application-oriented current-density limits. The increasing interaction of EM with thermal migration is investigated as well. We conclude with a discussion of application examples to shift from the current post-layout EM veri cation towards an EM-aware physical design process. Its methodologies, such as EM-aware routing, increase the EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit's reliability.
Die zunehmende Verbreitung von Elektronik im Alltag und die weitere Verringerung der Strukturgros... more Die zunehmende Verbreitung von Elektronik im Alltag und die weitere Verringerung der Strukturgrosen stellen neue Anforderungen an die Zuverlassigkeit und Verfugbarkeit integrierter Schaltungen. Die Arbeit zeigt ein systematisches Vorgehen zur Modellierung des funktionalen Schaltungsverhaltens und erganzt es um neue Verfahren zur Berucksichtigung zuverlassigkeitsrelevanter Schaltungseigenschaften. Etablierte Verfahren aus der Mechanik zur Behandlung der Zuverlassigkeit werden auf die Degradationseffekte integrierter Halbleiterbauelemente angewandt. Entsprechende Lebensdauermodelle zu relevanten Degradationsmechanismen sind dargestellt. Ausgehend davon werden allgemeine Mase zur Zuverlassigkeitsbewertung von Bauelementen unter Anwendungsbedingungen abgeleitet. Die Diskussion von Methoden zur Analyse der Zuverlassigkeit ganzer Schaltungen im Entwurf rundet die Darstellung ab. Die entwickelten Verfahren dienen der Unterstutzung eines schnellen und fehlerfreien Entwurfs sicherer und zuve...
Integrierte Halbleiterelektronik wird zukünftig immer mehr Lebensbereiche durchdringen. Für hohe ... more Integrierte Halbleiterelektronik wird zukünftig immer mehr Lebensbereiche durchdringen. Für hohe Leistung bei geringstem Energieverbrauch und minimalen Abmessungen kommen neueste Technologie-Generationen zum Einsatz. Die Anwendungen reichen vom Consumer-Bereich bis hin zu sicherheitskritischen Bereichen wie Automotive und Industrie 4.0. Allerdings bringen neue Halbleiter-Technologien auch neue Materialien und neue physikalische Effekte mit sich, die die Zuverlässigkeit der Elektronik und des Gesamtsystems beeinträchtigen. Es wird daher immer wichtiger, die Auswirkungen von zuverlässigkeitsrelevanten Effekten einschätzen und im Entwurf integrierter Elektronik berücksichtigen zu können. Im Beitrag werden grundsätzliche Herangehensweisen zur Absicherung der ElektronikZuverlässigkeit unterschieden. Im Mittelpunkt der Betrachtungen stehen intrinsische Degradationseffekte, die zum Ausfall von Elektronik über der Zeit führen können. Es werden Verfahren vorgestellt, die es gestatten, solche...
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW), 2015
This paper presents a control-theoretic driven approach to the automatic generation of test signa... more This paper presents a control-theoretic driven approach to the automatic generation of test signals for analog circuits or systems. It is based on the adaption of a tracking control structure for the task of generating test signals aimed at manufacturing test for a finished circuit design. The approach will be derived and its functionality is demonstrated using circuit examples. The integration of the proposed approach within a more general test development procedure for improving the fault coverage is explained.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016
Process variations and atomic-level fluctuations increasingly pose challenges to the design and a... more Process variations and atomic-level fluctuations increasingly pose challenges to the design and analysis of integrated circuits by introducing variability. Although several approaches have been proposed to deal with the inherent statistical nature of circuit design, we consider them incomplete with two important aspects often being insufficiently addressed: non-Gaussian distributions and highly correlated parameters. To address these points, we propose a fully multivariate and non-Gaussian approach based on an arbitrary model. A subset of the model parameters is treated as a multi-dimensional random variable, which is represented by a combination of generalized lambda distributions and Spearman rank correlation matrices-a very general approach with nearly arbitrary freedom in distribution shapes and parameter correlations. In our application scenarios, we show that such a model is able to fully and accurately capture variability in device compact models and standard cell performance models. Finally, we present adapted analysis methods making use of these models in circuit simulations and in efficient gate level analyses of digital circuits with high accuracy.
2014 IEEE International Integrated Reliability Workshop Final Report (IIRW), 2014
We propose a circuit-level modeling approach for the threshold voltage shift in PMOS devices due ... more We propose a circuit-level modeling approach for the threshold voltage shift in PMOS devices due to the negativebias temperature instability (NBTI). The model is suitable for application in analog circuit design and reproduces the results of existing digital-stress NBTI models in the limit of two-level stress signals. It accounts for recovery effects during intervals of low stress, and it predicts a stress-pattern dependent saturation of the degradation at large operation times. Since the model can be solved numerically in an efficient way, we have direct access to the threshold voltage shift at arbitrary times, in particular to the exact solution at large operation times, without any approximation. We implement the model via the Cadence Spectre URI. Finally, we make use of the model to compare the aging properties of several analog stress patterns. We furthermore present the results of an analog circuit-level NBTI simulation of a ring oscillator.
For analog and mixed-signal circuit design a modeling methodology is needed which is well suited ... more For analog and mixed-signal circuit design a modeling methodology is needed which is well suited to the requirements of a structured synthesis flow. It ensures that the intended specification is met without over-design. Behavioral models are able to provide circuit level knowledge on higher abstraction levels by including non-idealities and parasitics from the circuit realization, which allows realistic comparison of different architectures. At the same time these models are fast enough to explore design space and optimize specification translation with respect to system performance measures. This paper shows how numerical, analytical, and symbolic methods as part of an integrated modeling methodology are used for model generation, model parameterization, and model refinement in order to improve and accelerate analog circuit synthesis
With the ever increasing integration density of electronic circuits and devices thermal issues du... more With the ever increasing integration density of electronic circuits and devices thermal issues due to the Joule-effect become more and more important because they may yield increased power consumption, performance degradation, transient or persistent malfunction and reduced device life time. However, a number of difficulties is associated with "thermal aware electronics design". During the design of electronic circuits information on power dissipation of individual electronic elements must be calculated. This information together with layout and package data must be combined to setup and simulate thermal models for the device, which in turn must be connected in a suitable way to the electric network. Transistor models with a thermal pin are necessary to vary the temperature during dynamic simulations. The simulation of this model has to cope with the existence of largely disparate time scales for electrical and thermal effects. This article shows efficient ways for the gen...
Digitale Schaltungen werden heute in weiten Teilen automatisiert entworfen. Möglich ist das durch... more Digitale Schaltungen werden heute in weiten Teilen automatisiert entworfen. Möglich ist das durch den Syntheseprozess, der eine Spezifikation "Top-Down" automatisch in eine Implementierung umsetzt. Ein verleichbarer Syntheseprozess existierte für analoge Schaltungen bislang nicht. Dieser Beitrag beschreibt überblicksartig die im Rahmen des Clusterforschungsprojekts SAMS entwickelten Methoden, die erstmals einen nachweislich gangbaren Weg zur Synthese analoger Schaltungen beschreiben. Dabei wird eine Spezifikation zunächst interaktiv zu einer Struktur aus grundlegenden Schaltungsprimitiven (z. B. Operationsverstärker, etc.) verfeinert. Für diese grundlegenden Schaltungsprimitive werden dann mögliche Topologien erzeugt und automatisch verglichen. Die Machbarkeit wurde an zwei realistischen Beispielen aus der Industrie demonstriert.
The Web-based education methodology provides new chances and challenges to adopt interdisciplinar... more The Web-based education methodology provides new chances and challenges to adopt interdisciplinary expertise needed for mastering the design processes in key technologies as electronics and mi-cro-electro-mechanical systems (MEMS). Simulation should be an integral part in teaching, under-standing and design of complex systems. In this paper four courses are presented which include Web-based simulation capabilities in different physical domains.
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Papers by Roland Jancke