Fault simulation of linear analog circuits

JOURNAL OF ELECTRONIC TESTING: Theory and Applications, 4, 345-360 (1993) 9 1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. Fault Simulation of Linear Analog Circuits NAVEENA NAGI Computer Engineering Research Center, University of Texas at Austin, Austin, TX 78758 [email protected] ABHIJIT CHATTERJEE School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA 30332 JACOB A. ABRAHAM Computer Engineering Research Center, University of Texas at Austin, Austin, TX 78758 Received March 10, 1993; Revised May 10, 1993. Editor: M. Soma Abstract. Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to the discrete Zdomain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation. 1. Introduction Analog circuits and systems have recently enjoyed a renaissance, due to advances in communications and high-speed VLSI ASICs which demand a tightly coupled analog-digital architecture. However, the state of the art in analog automatic test generation is not as advanced as in digital automatic test pattern generation. Most previous work in test generation focuses on digital circuits using the classical stuck-at fault model since most potential physical faults can be mapped to a node stuck-at a logical 1 or 0. However, because of the complex electrical nature of analog circuits, a direct application of digital fault models proves to be inadequate in capturing the faulty behavior. Hence, analog test selection has been approached in a rather ad hoc way. Sometimes circuits tend to be overtested, while at other times, the tests may be inadequate. Traditionally, fault simulation is used to determine the effectiveness of input test sets to distinguish good chips from defective ones for digital circuits. However, for today's complex analog circuits with thousands of faults, fault simulation using conventional circuit simulators will be very inefficient. The problem is compounded by the presence of transient (ac) errors which can be detected only by an input waveform over time, unlike dc errors which require a single set of steadystate inputs. While the problem of fault simulation for analog circuits has not been directly addressed by previous researchers, there has been related work in other areas. FSPICE [1] is a SPICE based tool to introduce faults at the circuit level and simulate these faulty circuits using SPICE. Since fault simulation of large circuits at the circuit level is too time consuming to be practical, FSPICE is used for the simulation of macrocells and the results of the simulation used for the development of logical and functional fault models. Over the past few years, a number of higher level simulation tools for analog circuits have been developed including SABER [2] and iMACSIM [3], to name a few. These have alleviated the problem of large simulation times of circuit simulators. However, none of these have been applied to the problem of fault simulation and fault modeling. The lack of suitable analog fault models has been the prime reason for restricting the problem of analog test to the functional domain. Numerous authors have addressed the analog and mixed signal testing problem but all these techniques focus on functional testing of specific classes of circuits, for example, codecs [4], and do not indicate test generation methodologies nor the efficiency of the tests. Recent research [5, 6] has attempted to move away to the more quantitative faultbased approach to analog testing. However, the fault models are limited to resistive faults [5], or faults 346 Nagi, Chatterjee and Abraham in passive components [6]. None of these considers parametric faults in active components. In this work we make use of a hierarchical fault modeling approach for catastrophic as well as parametric ac and dc faults in passive and active circuits [7]. In this article, we present DRAFTS (DiscRetized Analog circuit FaulT Simulator), an efficient fault simulator for linear analog circuits. A large class of circuits used in control and signal processing applications fall into this category. Extremely efficient fault simulation is achieved by abstracting the analog circuit at the behavioral level, and then transforming it from the continuous Laplace domain to the discrete Zdomain. The discretized circuit is then simulated for the sampled test wave form. We achieve fast simulation by abstracting the analog circuit at the behavioral level and discretizing it. However, the effect of failures must be mapped on to the discretized circuit model. It is very important that the fault simulator be given a meaningful set of faults at the simulation level that is closely related to the physical defects in the analog circuits. This is a rather involved problem, as evidenced by the lack of standard analog fault models, since analog faults can manifest in different ways which affect the magnitude and phase frequency response of the circuit. One of the main contributions of DRAFTS is in developing this mapping process. This fault modeling is performed in two stages. First, faults at the circuit level are modeled at the behavioral level. In a previous work [7] we have developed a hierarchical fault modeling approach for catastrophic as well as parametric ac and dc faults. These faults can occur in both, passive and active components of the circuit. We use this approach to model faults at the behavioral level. In the second stage, these faulty circuits must be mapped to the discrete level in order to be incorporated into the discretized circuit formulation. Finally, a fault list is generated for the circuit and the faulty circuit for each fault in the list is simulated for the sine wave at the given test frequency. We begin the discussion of the fault simulator by a brief overview of the underlying theory behind the simulation of linear analog systems in the discretized Z-domain. The main focus of the fault simulator then is to map the faulty circuits at the circuit level to the Z-domain. This forms the core of the simulator and is described in Section 3. Section 4 describes the implementation of the fault simulator which is based on the basic simulation framework and the capability to represent faults within it. The results are illus- trated in Section 5 for a few example circuits. Finally conclusions and some future research directions are outlined. 2. Discretized State Variable Representation In the following, we briefly describe the theoretical framework underlying the simulation approach of DRAFTS for linear analog circuits. A large class of analog circuits [8, 9] can be expressed as linear state variable (first-order) systems. These can be represented by a system of interconnected integrators and summers (realized with op amps) [10]. The outputs of the integrators represent the state variables of the circuit. Second- and higher-order systems can be transformed to this form by introducing additional state variables [11]. For simplicity and ease of notation we consider single-output state variable circuits, where the output of each block containing a memory element (e.g., capacitor) corresponds to a state variable of the circuit. The circuit can be represented by a system of state equations given by X(t) = AX(t) + BU(t) (1) where X(t) = [xl(t), x2(O, . . . , xn(O]T which is the state vector comprising n state variables, Xl . . . . . xn, and ~7(t) = [xl(t), A2(t), . . . , An(t)]r, where Jci(t) is the derivative (with respect to time) of xi(t). U(t) is the vector of m inputs and A and B are n • n and n • m matrices, respectively. In the following discussion all matrices are indicated in boldface. The output of the circuit y(t) is given by y(t) = CX(t) + DU(t) (2) where C and D are 1 x n and 1 x m matrices, respectively. The output equation can be subsumed by the state equation by matrix manipulation so we will consider only the state equation for further analysis. The state equation is then transformed from the time domain to the complex frequency s-domain, by taking the Laplace transform, to obtain sX(s) = AX(s) + BU(s) (3) Given a network description, we can derive the above set of equations using signal flow graph (SFG) analysis [9]. A SFG is a representation of a system of equations as a directed graph with weights assigned to the edges. Fault Simulation of Linear Analog Circuits As an example, consider the biquadratic filter shown in figure 1. The three op-amp stages represent a sumruing inverter, an integrator and a lossy integrator. The outputs of the second and third stage (which contain memory elements, C) are the two state variables, xl(t) and x2(t), of the circuit. In this case, the output of the biquad filter corresponds to x2(t). The signal flow graph for the circuit is constructed with the help of the feedforward and feedback connectivity and the individual transfer functions of each block which give the weights of the arcs. The SFG for the biquad filter is given in figure 2. The weights (in boldface) have been computed by setting all resistors equal to R and capacitors equal to C. Thus, coo = 1/RC. From the SFG, the state equations can be obtained as follows: --coO - - c o O X2(S) where t, is the sampling time. Substituting (4) in the state equation (3) results in X(z) = ~ I " A~ z-iX(z) I X(Z) = ZAZ-IX(z) + Z B ( z - l u ( z ) I 'v~ I ~ 2z-1 s - t~ z + 1 / co = 2 t a n g t s t, 2 -R4/R6 -wo (7) at which the output signal has a value of - 3 0 dB. Bilinear transformation has a warping effect on higher frequencies because of the nonlinear transformation of the frequency axis to the Z-domain, given by (4) ~ u(tg)) f~>-Zfm where fm is the maximum frequency of interest of the circuit. In practice, fm can be taken to be the frequency -1 -1 -R4/R1 (6) This equation can be simulated for any given input signal, u(t). The input is sampled at the rate 1/ts. Thus, tk - tk_ 1 = ts and the simulation proceeds in time steps of ts. The value of the state variables at the current time step are obtained from the current input as well as the input and states at the previous time step. The sampling frequency, f~ = 1/ts, must satisfy the Nyquist criterion: The circuit state equation is a set of differential equations which can be solved using integration. However, if the integrals are approximated by recursive differences, we get a bilinear transformation of the sdomain equations to the Z-domain. These equations can be solved to give a discretized (i.e., a sampled) solution. The bilinear transform is given by u(t) Jr- U(Z)) Here, z -~ represents a single delay. Therefore, in the time domain, this equation is equivalent to F/g. 1, Biquadratic filter. o~. +1~>. (5) The above equation then simplifies to X(tk) = ZAX(tk-l) + ZB(u(&-I) + c~ ~ -1 ~t~ I + Let R6 R4 I~'-A~ + I~sI -- A~ -1B(z-I.(z) + u(z)) X2(S)/S u(s)/s +[O~ 347 1/s > o y(t) - _~~wo -1/R5C2 R4/R7 Fig. 2. SFG of biquadratic filter. X2 Nagi, Chatterjee and Abraham 348 where c0 is the analog frequency and fl is the transformed frequency. However, for fl < 0.3/t s, ~o -~ ft. Hence we choose a smaller sampling time for higher frequencies. For the above example of the biquad filter, let R = 10 K and C = 0.02/z. Then wo = 5000 and using the Nyquist criterion, ts = 0.0001 s. The state matrices in the Z-domain can be computed to give [x](z) x2(z)] = 0.307 0.538 ] I -0.307 0"538 I z-lxl(z)zlX2(Z) ] [ O'192](u(z) +z-lu(z)) + -0.038 These equations are simulated for a sinusoidal input given by u(O = 0.1 sin (2 ~r * 500 t) and the response is shown in figure 3. Here, u(t) is the input sine wave, Xl(t) and x2(t) are the response of the state variables which are the outputs of the two integrators of the biquad filter. 0.15 [ u(t) 0.05 //''"h / 0 .... / .... j xl (t) x2 (t) 0.I //''"\ / " ~\(' 9 ', / - / \\ {s / . . . . . . . . . . . \\\ . . . . . . . . . . / -0.05 -0.i i -0.15 Oe+O i le-3 r i i i i 2e-3 3e-3 t i m e in sec. i | small enough to be ignored are referred to as hard shorts, whereas shorts whose resistance cannot be ignored are resistive shorts. Shorts which are caused by large parasitics give rise to capacitive shorts. Circuit behavior can change drastically with small variations in the impedance of the short. Parametric faults are caused by statistical fluctuations in the manufacturing environment. Changes in process parameters (e.g., oxide thickness and substrate doping) can cause the values of components to change beyond their tolerance levels. Parametric faults are also caused by process gradients which produce device mismatch. 3.1. Circuit-Level Fault Models The key to ensuring valid fault models is that they should be derived as closely as possible from the underlying physical processing defects. A viable approach is to apply inductive fault analysis [13] to physical layouts of the circuit. Physical defects in the circuit are then abstracted to the circuit level and a fault list is formed, which consists of shorts and breaks in interconnections, new devices, and changes in the values of existing devices. Since design and process parameters can take on infinitely many values, there are infinitely many analog faults. An optimum subset must be chosen which will lead to the best possible fault list. The concept of fault equivalence as developed in [14] can be used to prune the fault list. This circuitlevel fault list is given as input to the fault simulator. 4e-3 Fig. 3. Response of biquad to 0.1 sin (2 lr * 500 t). 3. Fault Modeling In order to be able to judge the effectiveness of input test sets an accurate fault list is needed. For analog circuits, faults can be classified into two categories [12]: 9Catastrophic faults 9Parametric faults Catastrophic faults are random defects that cause structural deformations like short and open circuits which change the circuit topology, or cause large variations in design parameters (e.g., a change in the W/L ratio of a transistor caused by a dust particle on a photolithographic mask). Shorts whose resistance is 3.2. Fault Mapping The fault simulator is given a circuit description and a circuit-level fault list along with the test waveforms as input. Based on the theoretical framework described in Section 2, the fault simulator takes the network representation of the analog circuit and constructs its SFG to obtain the state equations. These are transformed from the s-domain to the Z-domain using bilinear transformation and this discretized representation of the circuit is simulated for the given input. In addition to the good circuit, faulty circuits with circuitlevel faults have to be transformed to the Z-domain too. This is by no means a trivial task, and its successful implementation forms a major contribution to a viable fault simulator. It would have been rather simple if each fault in the circuit could be mapped to a unique entry Fault Simulation of Linear Analog Circuits in the Z-domain state matrix. However, there is no such straightforward one-to-one mapping. This is what makes it a rather difficult problem as will be illustrated by the various cases discussed below. 3.2.1. Multiple Effect due to Single Fault. As in the case of digital circuits, we consider only single faults in the circuit for simplicity. Most circuit malfunctions occur in the presence of a single catastrophic or parametric fault. However, analog circuits which consist of a number of stages could display faulty behavior due to distributed fault effects. Each individual stage may differ from the nominal one within its specified tolerance, but the combined effect of multiple stages may result in the circuit malfunction (e.g., distributed phase shift errors in a feedback loop add up to cause the circuit to oscillate). The fault simulator can be extended to simulate distributed faults, but for now we consider only single faults at the circuit level. In order to simulate the faulty circuit, it must be mapped to the discrete domain. The Z-domain state equations of the circuit may be thought of as a discrete network realization of delay elements, adders, and multipliers as shown in figure 4. Here, the multiplier coefficients, zaij and zbi are the elements of the Z n and ZB matrices of equation (6). A single fault at the circuit level, however, does not map to a corresponding single fault in the discrete circuit representation. Instead, it appears as multiplefaultsin the discrete circuit. Comparing these with the corresponding fault-free equations shows that all the entries of both the matrices ZA and ZB are affected, thus affecting all the multipliers in the discrete circuit. xl E-5000.0 ooo0 -500.0 , 001 X2(S) + I Xl(Z xz(z)! = X2(S)/S [5000"Olu(s)/s 0.0 0.372 I - 00'525 .3720.860 1 + I z-lxl(z)zlX2(Z) 1 I -0.046 O'1901(u(z) +z-'u(z)) In this example the single circuit fault had a single effect on the Laplace domain representation of the circuit, but in general, it could cause a multiple effect. This multiple effect of the fault in the discrete domain precludes the possibility of directly modeling faults in the discrete circuit realization. 3.2.2. Changein the Number of States. A major cause of ac malfunction in a circuit is the occurrence of large parasitics or coupling capacitances. These can give rise to the addition of faulty states in the circuit response. For example, consider the effect of a capacitive short Cf across the output and negative terminals of OA1 in the biquad circuit of figure 1. This will introduce a faulty state Xf, in addition to the original states x~ and x2. The faulty SFG is shown in figure 5 and corresponding state equations are given below. X2(S) Xf(S) xl/z 349 1 i00 = 00o00ol -5000.0 -5000.0 5000.0 -5000.0 X2(S)/S Xf(S)/S x2 -[- 0.0 -5000.0 0.0 5000.0 R(S)/S Fig. 4. Discretenetworkrealizationof the biquad filter. For example, consider a single fault in the circuit shown in figure 1 with a faulty value of resistor R5 = 1K (instead of 10K). This affects the entry a22 of the state matrix A in the Laplace domain equation (3), whereas it affects both matrices Z A and ZB in equation (6), thereby causing a multiple-fault effect in the Z-domain. The faulty state equations are given below. 1 Io886 0075o377l Ez E0047l x2(z) = -0.377 0.452 0.584 -0.301 0.075 0.509 z_lx~(z) + -0.009 -0.188 (u(z) + z-lu(z)) xf(z) 350 Nagi, Chatterjee and Abraham -w| -1/R6Cf / u(t) -w, /~ -WO +1 1IS -WO >o 1/S >o y(t) -]/R502 -1/R7Cf Fig. 5. SFG of biquadratic filter with faulty coupling capacitor (Cf). The discrete network realization for the faulty circuit undergoes a complete topological change as shown in figure 6. Due to this effect, the fault simulator has to rebuild the state equations for the faulty circuit. Faults in circuits cannot only cause an increase in the number of states, but they can also result in a decrease in the number of original states. This can occur if a circuit fault causes a capacitor to be shorted. -tej zbl ( 1 }-- zb2 ( X ~ - - zb3 za13 This is based on the asymptotic wave form evaluation (AWE) technique [15]. This can be incorporated into the SFG and the state equations. However, op amps are rarely used in an open-loop configuration and the response of the closed-loop macrocircuit may be dominated by the poles introduced by the passive components. If even the faulty op amp poles are dominated by these, then the macrocircuit response and hence the circuit response may be fault free under such a fault. In order to avoid introducing such faults, faults are hierarchically modeled at the macrocircuit (op-amp block) level. As an example, consider a fault in OA3 of figure 1. The macrocircuit composed of this op amp is that of a lossy integrator whose transfer function can be represented as --CO 1 H(s) - - - s+co 2 where CO1 -- "V zof= and za32 Fig. 6. Discrete network with increased states. CO2 -- 3.2.3. Faults in Op Amps. Faults in op amps are the most difficult faults to handle. These faults have to be modeled at the transfer function level first before they can be incorporated into the discretized state equations. This fault modeling approach has been described in our previous work [1], but will be briefly outlined here for the sake of completeness. The transfer function of the faulty op amp is modeled by a reduced order rational function approximation in terms of its q dominant poles and their residues and is given by q ki H(s) = Z s - Pi i=l R3 x C2 (8) 1 R5 x C2 The faulty response of the macrocircuit has two dominant poles, given by pole[O] pole[l] residue[O] residue[l] = = = = (-2.107e (-3.407e (-2.237e (2.237e + + 03) + j ( - 0 . 0 0 0 e + 00) + 04) + j ( - 0 . 0 0 0 e + 00) + 03) +j(0.000e + 00) 03) +j(0.000e + 00) (9) This gives rise to a faulty transfer function of Hi(s ) _ residue[Ol + residue [11 s - pole[O] s - pole[i] Since this is a second-order function, additional states will have to be introduced in order to represent it in the state equation [11]. The SFG of the faulty Fault Simulation of Linear Analog Circuits circuit along with the additional states is shown in figure 7. The faulty state equations are given below: XI(S)1 X2(S) dl(S) dz(s) r- -5000.0 I -0.004 0.0 1.0 5000.0 -36177.48 1.0 0.0 0.0 -717.83e5 -714.89e5 0.0 0.0 0.0 +I xl(s)/s x2(s)/s ~176 1 0.0J 5000.0 ] dl(s)/s d2(s)/s 0.0 0.0 0.0 + u(s)/s xl(z) X2(Z) = dl(Z) d2(z) 0.581 -0.094 -0.000005 0.000079 0.132 -0.338 0.000033 0.000007 z-lxl(z) + z-lx2(z) z-ldl(Z) z-ld2(z) + -474.743 -2373.718 0.881 -0.023 0.197 -0.012 -0.000001 0.000010 -472.8007 -2364.003 / -0.118] 0.976J which extracts the connectivity information as well as the various component types and values into an internal graph data structure. In order to define a clean interface between the modules, various classes are defined. Element and Fault classes are derived from the Link class so that efficient linked lists can be built from them. Each of these, in turn, are used to derive classes for specific types of circuit primitives, e.g., Resistor, Capacitor, Opamp, and various fault classes, e.g., ShortFault, OpenFault, ParFault and OpampFault. The remaining information needed for simulation and display of results is built using the SimParam class. Each opamp block is isolated as a subcircuit and its transfer function, Hi(s), determined. While determining the transfer function, DRAFTS keeps a list of the subcircuits which have memory elements such that the output of these subcircuits will be the state variables of the circuit. The signal flow graph can now be constructed, since all the required information regarding the state variables, connectivity and transfer functions is available. The transfer functions are used to get the appropriate weights on the edges of the SFG. Howewer, the obtained SFG may not be in a form that would directly result in the state equations, since the state equations represent first-order differential equations, while the transfer functions could be of second or higher orders. In general, the transfer function is of the following form: Hi(s) (u(z) + z-lu(z)) 351 = ~n Sn Jr" i~n_l Sn-1 + ... OlnSn -t- Oln_ l S n - 1 "Jr" . . . -I- t~o (10) ~ Ol0 DRAFTS, a discretized analog circuit fault simulator, has been developed in C + + with certain modules implemented in C, based on the theory described in Sections 2 and 3. A flow diagram illustrating the implementation is given in figure 8. DRAFTS is organized as two modules. The first module performs a good circuit simulation while the second processes the fault list and maps each fault to the discrete domain. It then calls the core simulator of the first module to simulate the faulty circuit state equations. These are described in more detail below. It has been shown in [11] that it is possible to construct a SFG for each of the functions, Hi(s), which consists of arcs representing integrators and summers. In this transformed SFG, only the output node, xi(s) corresponds to a physical node (actual state variable) in the analog system. Dummy state variables are associated with all the other nodes. This results in a SFG which can be directly translated into the system state equations in the s-domain. The discretized state equations are then obtained in the Z-domain by applying the bilinear transformation as shown in equation (6). Finally, these equations can be simulated for any given input which is sampled at an optimum rate so as to provide the required accuracy at the maximum efficiency. 4.1. Good Circuit Simulation 4.2. Fault Simulation The circuit description given as input to DRAFTS is in SPICE format. This is parsed by the preprocessor DRAFTS is a serial fault simulator unlike concurrent or parallel digital fault simulators. It is not feasible to 4. Implementation of DRAFTS 352 Nagi, Chatterjee and Abraham -1 ao/a2 u(t) -1 > >o ~ W0 > o 1/S +1 > ~ o ~ ~_J -al/a2 Fig. 7. SFG of biquadratic filter with faulty op amp, OA3. SIMULATION OF GOOD CIRCUIT SIMULATION OF FAULTY CIRCUIT CircuitDescriptionFile (SPICEFormat) I I I I I PREPROCESSOR I Extractionofnecessarycircuitinformation intoDRAFTS'internaldatastructures ,1 \ \ Computet~nsferfunctions ofopampmacro-circuits '1 I I ! ConstructSignalFlowGraph (SFG) I i BuildStateEquations (s-domain) i 'I I ! DiscretizeState Equations (Z-domain) i T I 1 SIMULATION (for sampledinput) Fault coverage statistics Fig. 8. Flow diagram of DRAFTS. I ......i "~y(t) Fault Simulation of Linear Analog Circuits have a parallel analog fault simulator since nodes in analog circuits exhibit continuous wave forms, in contrast with a 1 or 0 state in digital circuits. However, DRAFTS does exhibit a significant speedup over circuit simulators by virtue of the fact that only forward simulations are performed, instead of having to iteratively solve the circuit node equations. This is made possible by exploiting the properties of linear circuits. Even in a linear circuit, a single op amp appears as tens or hundreds of nonlinear transistors to a circuit simulator, whereas when abstracted to the behavioral domain, the linear circuit is amenable to an efficient simulation technique. By virtue of efficient data structures, parametric faults in the passive components (which comprise a large number of physical failures) can directly be mapped to the state equations. Faults which change the connectivity of the circuit result in having to recompute the transfer functions, although only for the affected blocks. This is true even in the cases with global feedback, since the effect is percolated to the other blocks by the SFG. Op-amp faults at the circuit level are first modeled in the s-domain by the hierarchical modeling approach before mapping them to the Zdomain. Although the modeling approach is rather involved, it is not a major concern, since it involves a single op-amp block rather than the entire circuit. Moreover, it is a one time cost to be paid over the entire set of input wave forms to be simulated. For each fault simulation, the error between the good and faulty response is computed and if it is measurable, the fault is declared to be detected by the test wave form. Thus, fault coverage statistics for the given test wave forms are evaluated. 5. Circuit Examples Table 1 summarizes the fault simulation results for firstand higher-order linear analog circuits investigated during the study. We now discuss in detail selected circuits from our study. 353 5.1. Biquadratic Filter Results will be given below for the running example of the biquadratic filter shown in figure 1. To back up the results of our simulator, PSPICE simulations were performed for the fault-free circuit as well as a sample of faults covering all the cases discussed herein. The simulator results were found to match very closely with those of PSPICE with less than 1.5% error. In addition, almost two orders of magnitude speedup for as small a circuit as this (containing three op amps) was achieved. Figure 9 shows the response of the biquad filter to a sinusoidal input, u(t) = 0.1 sin(27r*500t). The response for the fault-free circuit along with the three faults considered in Section 3 (faulty R5, Cf, and OA3) are shown. The error between the good circuit response and those of the faulty circuits is shown in figure 10. Since the error is measurable for all the three responses, these faults can be detected by the given test wave form. The runtimes for PSPICE averaged 11.02 s, whereas the runtime for DRAFTS averaged 0.12 s, giving a speedup of almost 100 per simulation. Fault simulation results for the biquadratic filter are shown in table 2. A sample of faults were simulated for two test sets.1 A threshold of 0.01 V was used to measure fault detection. 5.LL Aid for Test Generation. We illustrate the advantage of the fault simulator as an aid for test generation by the following example. Figure 11 compares the ac response of the fault-free circuit with that of a circuit containing a faulty op amp OA3. As is evident from this response, the fault will be detected only if the circuit is tested at frequencies lying between 200-800 Hz. The response of the good and faulty circuit is shown for the test frequency of 100 Hz in figure 12. The error between the good and faulty response is too small to be measured, and it is clear that the fault would remain undetected at that frequency. On the other hand, a frequency of 500 Hz would be a good test for the fault, as can be observed from the difference in good and Table 1. Summaryof results. Circuit Type No. Faults No. Tests Threshold Fault Coverage Time (s) Biquadratic filter 26 26 10 21 0.1V 0.1V 6t.5% 84.6% 28.7 55.2 Girling-Good leapfrog filter 12 12 5 5 0.1V 0.05V 50% 91.7 % 11.1 11.1 Delyiannis-Friend stagger-tuned filter 13 13 5 5 0. IV 0.05V 69.2 % 92.3 % 6.9 6.9 Nagi, Chatterjee and Abraham 354 0.15 0.i good ckt faulty R5 .... | faulty Cf-;~\ 1 faulty OA3/ ...... ~ ", "\~\ 0.05 4' ,',a -:.- .................... x\ ~, 0 \ -0.05 9 .. \x I, . . . ;e / i/ ~\ -0.1 -0.15 i Oe+O0 ,." r-'.: ................. r':'- ............ ,, %: r le-03 i kX ll i/ time in sec. 4e-03 3e-03 5.4. Delyiannis-Friend Stagger Tuned Filter Fig. 9. Responseof good and faulty biquads to 0.1 sin(27r*500t). 0.06 1 / faulty ~ ..... - - I faulty/Ct ~rror ---" / /> 0.020"04 / / / / 7 ~ 0 We consider another leapfrog filter which is represented by the more compact Girling-Good form as shown in figure 17. A small sample of the faults simulated for this circuit are illustrated in table 3. The fault coverage of a given test set depends on the threshold voltage chosen, as shown in the table. i i 2e-03 5. 3. Girling-Good Leapfrog Filter f auli~i~>~7 ~............... 74 \x ", / r - "- - t ............ ~,\\~ This filter consists of a cascade of second-order bandpass stages consisting of the Delyiannis-Friend circuit (figure 18). If each stage is tuned to a different frequency, the combined circuit is said to be stagger tuned, whereas if they are tuned to the same frequency it is described as synchronously tuned. The transfer function for each of the stages is Hi(s) = -0.02 - 2QioooiS -0.04 -0.06 0e+00 i = 1, 2, 3 (11) S2 + (OOoi/Qi)s + oo2i' le-03 2e-03 3e-03 time in sec. 4e-03 Fig. 10. Error betweenthe goodand faultyresponsesof the biquad. erroneous circuit responses in figure 13. It can also be seen from these plots that the DRAFTS simulation results follow those of PSPICE very closely. Dummy state variables need to be inserted in order to represent the overall filter transfer function using state matrices. Fault simulation results for a sample of faults are shown in table 4. 6. Conclusion and Future Work 5.2. Leapfrog Filter (Type A) Figure 15 represents the signal flow graph of the leapfrog filter shown in figure 14. Fault simulation results are shown for a fault in the capacitor C2, whose value changes to 50 % of the good circuit C2 value. Both, the good and faulty circuit responses to an input of sin(27r*1000t) are illustrated in figure 16. The percentage error between the simulation results of SPICE and DRAFTS was found to be less than 2.5%. The runtimes for PSPICE averaged 45.50 s, whereas the runtime for DRAFTS averaged 0.83 s which is a speedup of 55. This speedup is less than that achieved for the biquad filter due to the fact that a higher sampling rate was required for this circuit. However, in general, speedups will increase as the circuits become larger. We have presented a new approach to ac fault simulation for linear analog circuits. The simulation is performed by discretizing the circuit in the Z-domain and applying a sampled input wave form. The sampling rate is chosen such that we get the maximum efficiency for the required accuracy. Faults are also mapped from the circuit level to the Z-domain description of the circuit. We can simulate faults in passive and active components, as well as breaks and shorts in lines. We have also illustrated how the fault simulator can be used to evaluate the quality of a test wave form for a given fault. DRAFTS can be enhanced to a distributed fault simulator to offset the serial nature and provide even greater speedups. A fault simulator is the first step in an integrated test generation system. An effective test Fault Simulation of Linear Analog Circuits 355 Table 2. Fault simulation results for the biquadratic filter. Test Set 1 Description of Fault Test Set 2 Parametric Fault Component Nominal Value Faulty Value Freq. (Hz) Error (V) Detect Freq. (Hz) Error (V) Detect R1 10K 15K 1.00e+02 1.47e-02 Y 4.37e+01 1.47e-02 Y R1 10K 5K 1.00e+02 3.57e-02 Y 3.85e+00 3.56e-02 Y R2 10K 15 1.00e+03 1.70e-03 N 2.34e+03 8.23e-03 N R2 10K 5K 1.00e+03 1.84e-04 N 3.75e+03 1.11e-02 Y R3 10K 15K 1.00e+03 1.18e-02 Y 1.56e+03 1.31e-02 Y R3 10K 5K 1.00e+03 2.02e-02 Y 2.16e+03 3.11e-02 Y R4 10K 15K 1.00e+03 3.67e-03 N 2.83e+03 9.47e-03 N R4 10K 5K 1.00e+03 1.07e-02 Y 1.99e+03 1.54e-02 Y R5 10K 15K 1.00e+03 1.17e-02 Y 1.18e+03 1.19e-02 Y R5 10K 5K 1.00e+03 1.79e-02 Y 1.06e+03 1.80e-02 Y R6 10K 15K 1.00e+02 1.42e-02 Y 4.37e+01 1.43e-02 Y R6 10K 5K 1.00e+02 2.00e-02 Y 4.37e+01 2.01e-02 Y C1 0.01 /zF 0.02 /xF 1.00e+03 4.50e-03 N 2.47e+03 1.41e-02 Y C1 0.01 /zF 0.005 /zF 1.00e+03 1.84e-04 N 3.75e+03 1.11e-02 Y C2 0.01 /zF 0.02 ~F 1.00e+03 4.50e-03 N 2.47e+03 1.41e-02 Y C2 0.01 tzF 0.005 /zF 1.00e+03 1.84-04 N 3.75e+03 1.11e-02 Y Short Value Freq. (Hz) Error (V) Detect Freq. (Hz) Error (V) Detect Y Short Fault Short Type Shorted Nodes Resistive 2,3 10 1.00e+02 4.98-02 Y 4.37e+01 4.96e-02 Resistive 2,3 1K 1.00e+03 3.88e-02 Y 1.26e+03 3.95e-02 Y Resistive 4,5 10 1.00e+02 4.99e-02 Y 4.37e+01 4.98e-02 Y Resistive 4,5 1K 7.00e+02 4.20e-02 Y 7.33e+02 4.20e-02 Y Capacitive 2,3 10 nF 1.00e+03 1.53e-02 Y 1.54e+03 2.71e-02 Y Capacitive 3,0 10 nF 1.00e+02 0.00e+00 N 3.02e+00 1.00e-08 N Node Open Value Freq. (Hz) Error (V) Detect Freq. (Hz) Error (V) Detect R7 8 1 Mf~ 1.00e+03 6.33e-02 Y 1.16e+03 6.50e-02 Y C2 7 1 /zF 9.00e+02 1.57e-03 N 4.66e+03 1.65e-02 Y Gain ( A o ) Gain-BW (B) Freq. (Hz) Error (V) Detect Freq. (Hz) Error (V) Detect X1 2500 5.00e+05 9.00e+02 1.12e-03 N 1.00e+03 1.70e-03 N X1 500 1.00e+05 4.00e+02 8.47e-01 Y 1,00e+03 9.36e-01 Y Open Fault Componem Op Amp Fault Component Fault Coverage 61.5% 84.6% Nagi, Chatterjee and Abraham 356 08[- 0.05 f ' ~ g o o d ckt - / I~f a u l t y ckt . . . . 0.7 ' '~..: 0.04 / / / / 0.03 0.6 / 0.02 0.5 0.01 0,4 0 / .... \X 0.3 -0.01 0.2i -0,02 9 good ~;gulty f{~ity ';" // t l ~ t ~~.." '-,, t ckt(sz~-ekt(SPfZC{) ckt(DR~FTS) ,/ or t j~ << /" t ! tt/ r ,/ ; \- - ........ .... '~ ~ t ,?' -0.03 0.1 -0,04 0 -- le+O0 le+01 ie+02 le+03 frequency le+04 -0,05 le+05 Fig. 11. Frequency response of good and faulty biquads. Oe+O0 le-03 2e-03 3e-03 t i m e in sec. 4e-03 Fig. 13. Fault detected at f = 500 Hz. 0.05 R3 0.04 0.03 R2 0.02 u(t) 0.01 g R5 02 I- ll o -0,01 -0.02 -0.03 -0.04 ca -0.05 0e+00 4e-03 8e-03 time 2e-02 le-02 in sec R~ 2e-02 198 Fig. 12. Fault unde~cted at f = 100 Hz. Fig. 14. Leapfrog filter. § wl=I/RC +1 1 w2=I/RC 2 Fig. 15. SFG of leapfrog filter. R11 y(t) Fault Simulation of Linear Analog Circuits 0.6 0.4 0,2 0 v -0.2 -0.4 -0.6 Oe+O0 5e-04 le-03 2e-03 t i m e in sec. 2e-03 3e-03 Fig. 16. Response of good and faulty leapfrog to sin(27r * 1000t). vi a3k 1ok ('7) 1ok \ ! 10k~R, / lO4,~ / :,, 'V~ 10k 1ok T1% \ / 13.1 @ ('~ ,ok:~'~ 8. R3 @ 'VVV R8 R9 Fig. 1Z Girling-Good leapfrog filter. R1 @ 7.4k 357 358 Nagi, Chatterjee and Abraham Table 3. Fault simulation results for the Girling-Good leapfrog filter. Parametric Fault Detect Component Nominal Value Faulty Value Freq. (Hz) Error (V) Threshold 1 (0.1 V) Threshold 2 (0.05 V) R3 R5 Rll C1 C3 10K 10K 10K 11.1 nF 17.7 nF 20K 20K 5K 20 nF 30 nF 1.00e+03 1.65e+03 9.99e-01 1.43e+03 8.39e+02 1.52e-01 7.45e-02 2.31e-01 6.19e-02 9.65e-02 Y N Y N N Y Y Y Y Y Short Fault Detect Short Type Shorted Nodes Short Value Freq. (Hz) Error (V) Threshold 1 (0.1 V) Threshold 2 (0.05 V) Resistive Resistive Capacitive 4,5 12,13 2,3 1K 5K 10 nF 1.00e+03 9.99e-01 1.43e+03 2.23e-01 4.81e-01 6.64e-02 Y Y N Y Y Y Open Fault Detect Component Node Open Value Freq. (Hz) Error (V) Threshold 1 (0.1 V) Threshold 2 (0.05 V) R1 C2 2 4 1 Mr/ 1 Mr/ 1.00e+03 8.39e+02 2.83e-01 1.32e-01 Y Y Y Y Opamp Fault Component X1 X1 Gain ( A 0 ) 2500 500 Detect Gain-BW (B) Freq. (Hz) Error (V) Threshold 1 (0.1 V) Threshold 2 (0.05 V) 5.00e+05 5.00e+05 1.75e-01 1.75e-01 1.95e-02 5.21e-02 N N N Y 50.0% 91.7% Fault Coverage C2 C4 F v Fig. 18. Delyiannis-Friend stagger tuned filter. C6 I Fault Simulation of Linear Analog Circuits 359 Table 4. Fault simulation results for the Delyiannis-Friend stagger-tuned filter. Detect Parametric Fault Component Nominal Value Faulty Value Freq. (Hz) Error (V) Threshold 1 (0.1 V) Threshold 2 (0.05V) R1 R1 R3 R3 C1 C1 42.4K 42.4K 4.48K 4.48K 0.1 /~F 0.1 ~F 30K 60K 2K 5K 0.2/zF 0.05 t~F 8.00e +02 8.00e+02 8.00e +02 5.00e +02 8.00e+02 K00e+02 2.34e-01 1.66e-01 2.97e-01 4.84e-02 1.67e-01 2.08e-01 Y Y Y N Y Y Y Y Y Y Y Y Short Fault Detect Short Type Shorted Nodes Short Value Freq. (Hz) Error (V) Threshold 1 (0.1 V) Threshold 2 (0.05 V) Resistive Resistive Capacitive 2,3 2,3 4,5 10 1K 0.01 /~F 5.00e+02 5.00e+02 8.00e +02 3.40e-01 1.16e-01 7.87e-03 Y Y N Y Y N Open Fault Detect Component Node Open Value Freq. (Hz) Error (V) Threshold 1 (0.1 V) Threshold 2 (0.05 V) R3 C2 3 4 1 Mr/ 1 Mfl 5.00e+02 2.00e+02 7.03e-01 3.59e-01 Y Y Y Y Opamp Fault Component X1 X1 Gain ( A 0 ) 2500 500 Detect Gain-BW (B) Freq. (Hz) Error (V) Threshold 1 (0.1 V) Threshold 2 (0.05 V) 5.00e +05 5.00e + 05 1.00e +03 1.00e + 03 8.46e-03 1.00e-02 N N N Y 69.2% 92.3% Fault Coverage generation strategy for analog circuits which follows an approach that is similar to simulation-based digital test generation will be developed with the help of this fault simulator. Acknowledgments This research was supported by the National Science Foundation under grant MIP-9222481. Note 1. Test set 1 = {100, 200, 300, 400, 500, 600, 700, 800, 900, moo}. Test set 2 = {1.00e+03, 3.16e+04, 1.18e+03, 1.06e+03, 1.56e+03, 1.54e+03, 1.26e+03, 1.99e+03, 2.83e+03, 7.33e+02, 2.34e+03, 3.75e+03, 4.66e+03, 3.02e+00, 3.85e+00, 3.80e+00, 4.37e+01} 1.16e+03, 2.16e+03, 2.47e+03, 3.95e+00, References 1. M. Renovell, G. Cambon, and D. Auvergne, "FSPICE: a tool for fault modeling in MOS circuits, INTEGRATION, VLSI J., Vol. 3, pp. 245-255, 1985. 2. I. Getreu, "Behavioral modeling of analog blocks using the SABER simulator," in Proc. MWCAS, pp. 977-980, 1989. 3. J. Singh and R. Saleh, "iMACSIM: a program for multi-level analog circuit simulation," in Proc. ICCAD, pp. 16-19, 1991. 4. D.K. Shirachi, "Codec testing using synchronized analog and digital signals, inproc. IEEEInt. Test Conf., pp. 447-454, 1984. 5. M.J. Marlett and J.A. Abraham, "DC-IATP: an iterative analog circuit test generation program for generating DC single pattern tests," in Proc. IEEE Int. Test Conf., pp. 839-845, 1988. 6. M. Soma, "A design-for-test methodology for active analog filters," in Proc. IEEE Int. Test Conf., pp. 183-192, 1990. 7. N. Nagi and J.A. Abraham, "Hierarchical fault modeling for analog and mixed-signal circuits," in Proc. IEEE VLS1 Test Symp. pp. 96-101, 1992. 8. M. E. Van Valkenburg, Analog, Filter Design, Holt, Rinehart and Winston: New York, 1982. 9. Seshu, Balabanian, Linear Network Analysis, Wiley: New York, 1959. 360 Nagi, Chatterjee and Abraham 10. A. Chatterjee, "Concurrent error detection in linear analog and switched-capacitor state variable systems using continuous checksums," in Proc. IEEE Int. Test Conf., pp. 582-591, 1991. 11. A. Chatterjee, "Checksum-based concurrent error detection in linear analog systems with second and higher orders, in "Proc. IEEE VLSI Test Symp., pp. 286-291, 1992. 12. L. Milor and V. Visvanathan, "Detection of catastrophic faults in analog integrated circuits," IEEE Trans. Computer-Aided Design, pp. 114-I30, 1989. 13. J.R Shen, W. Maly, and EL Ferguson, "Inductive fault analysis of MOS integrated circuits," IEEEDesign Test, Vol. 2, pp. 13-26, 1985. 14. M. Soma, "Probabilistic measures of fault equivalence in mixedsignal circuits," in Proc. IEEE VLSI TestSymp., pp. 67-70, 1991. 15. L.T. Pillage and R.A. Rohrer, 'Nsymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-AidedDesign, Vol. 9, pp. 352-366, 1990. Naveena Nagi received her B.E. in Electronics and Communication Engineering from the University of Roorkee, Roorkee, India, in 1986 and the MS degree in Computer Engineering from the University of Southern California at Los Angeles in 1989. She is currently pursuing a Ph.D. degree in Electrical Engineering from the University of Texas at Austin. Her research interests are in the fields of testing, fault modeling and fault simulation of digital, analog and mixed-signal circuits. Abhijit Chatterjee received his B.Tech in Electrical Engineering from the Indian Institute of Technology, Kanpur, India, in 1981, the MS degree in Electrical Engineering and Computer Science from the University of Illinois at Chicago in 1983 and the Ph.D. degree in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign in 1990, He is currently an Assistant Professor with the School of Electrical Engineering at the Georgia Institute of Technology, Atlanta, GA. Until December 1992 he was a research staff member at the General Electrical Research and Development Center in Schenectady, N.Y. His interests are in the fields of testing, fault-tolerance and reliable design of digital and analog signal processing circuits, low-power DSP circuits, analog electronics, computer algorithms, design automation and computer architecture. His work has been cited by the Wall Street Journal and presented on a Japanese network TV program called "'High Tech Shower International." He is the author of one U.S. patent. Dr. Chatterjee received a Best Paper Award at the ICCD'92. He is also a recipient of the National Science Foundation Research Initiation Award (1993). Jacob A. Abraham is a Professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. He is also director of the Computer Engineering Research Center and holds a Cockrell Family Regents Chair in Engineering. He received the Bachelor's degree in Electrical Engineering from the University of Kerala, India, in 1970. His M.S. degree, in Electrical Engineering, and Ph.D., in Electrical Engineering and Computer Science, were received from Stanford University, Stanford, California, in 1971 and 1974, respectively. From 1975 to 1988 he was on the faculty of the University of Illinois, Urbana, Illinois. Professor Abraham's research interests include VLSI design and test, formal verification, and fault-tolerant computing. He is the principal investigator of several contracts and grants in these areas, and a consultant to industry and government on testing and fault-tolerant computing. He has over 200 publications, and has supervised more than 30 Ph.D. dissertations. He was elected Fellow of the IEEE in 1985, and is also a member of ACM and Sigma Xi. He is an associate editor of the IEEE Transactions on VLSI Systems, and is currently the chair of the IEEE Computer Society Technical Committee on Fault-Tolerant Computing.