The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (BIST) fac... more The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (BIST) facilities is discussed. The main concern is related to the weak diagnostic capability of BIST. A BIST architecture is described which is based on multiple signature analyzers (SA) to provide better diagnostic resolution. A new conception for the diagnosis of digital circuits, which does not use fault models, and a method for calculating the diagnosibility of the given circuit are presented The results of calculation can be used for redesign of the circuit for better diagnosibility. Experimental results provide the data which characterize the diagnosibility for a family of ISCAS benchmark circuits.
The recent advancements in the implementation technologies have brought to the front a wide spect... more The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a fast simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like selecting the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The high scalability of the method is achieved by using a novel fast method for finding activated paths for many test patterns in parallel, a novel algorithm to determine only a small subset of critical paths, and a novel method for identifying the true critical paths among this subset, using branch and bound strategy. The paper demonstrates efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.
The paper presents a novel approach to high-level fault modeling and test generation for micropro... more The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general frame-work and novel techniques for automated software-based self-test program generation are discussed. On this basis new previously not published test quality improvement capabilities of the approach are high-lighted and explained. Based on the high level fault model defined for HLDDs a novel class of hard-to-test faults, called "unintended actions", is proposed. In addition, the mechanisms for reducing the risk of fault masking is explained. The experimental results show the superiority of the new method by achieving a higher quality of tests with shorter length compared to the previous results.
The importance of diagnostic test generation cannot be overemphasized as it is increasingly becom... more The importance of diagnostic test generation cannot be overemphasized as it is increasingly becoming important for diagnosing the complex circuits designed today. One approach is to use a test set that is generated originally for testing as the starting point so the diagnostic generator uses a deterministic approach to find diagnostic vectors that are then added to the original test set. But the challenge with the deterministic approach is with its high computational cost and time. We propose a novel semi-random diagnostic generator which is inspired from the simplicity and speed a random ATPG for test generation has. Two methods are presented and our investigation shows that this semi-random approach improves the diagnostic resolution and has a lesser computational cost and time.
In this paper we present a very fast fault simulation method for sequential circuits, which is ba... more In this paper we present a very fast fault simulation method for sequential circuits, which is based on accommodation of exact parallel critical path tracing in combinational circuits for using it also in case of sequential circuits. Formulas are developed for parallel on-line analysis of the faults to classify them into two classes, which are eligible for combinational simulation, and which are not. The latter class of faults has to be simulated by any conventional fault simulation method used for sequential circuits. Combining two approaches to fault simulation - the combinational and sequential ones - allows dramatic speed-up of fault simulation in sequential circuits, which is demonstrated by experimental results.
The main objective of this work is to develop a method and to create a tool for random test patte... more The main objective of this work is to develop a method and to create a tool for random test pattern generation for digital circuits, capable of achieving a high diagnostic resolution. We propose a measure for evaluating the diagnostic resolution of a given test set. Three methods were investigated using different criterions for selecting test patterns from the given packages of random vectors. The chosen criterion targets the diagnostic resolution as high as possible at the minimum test length and the maximum fault coverage. Experimental research demonstrated that the proposed tool provides the test engineer with better diagnostic resolutions compared to other comparable test generation methods.
We propose a method for synthesis of Software-Based Self-Test (SBST) for testing RISC type of mic... more We propose a method for synthesis of Software-Based Self-Test (SBST) for testing RISC type of microprocessors without needing the knowledge of implementation details. The test covers a large class of faults and a special target is to detect Transition Delay Faults (TDF). To reduce the complexity, the processor is partitioned into Modules Under Test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, whereas for the control parts a novel functional control fault model was developed. The test is regular, represented in a compact form allowing easy unrolling during test execution. Experimental results demonstrate high Stuck-At Fault (SAF) and TDF coverage, despite the lack of knowledge of implementation details
Recent safety standards set stringent requirements for the target fault coverage in embedded micr... more Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementationindependent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudoexhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor.
The conventional design techniques struggle with integration density and constantly strengthening... more The conventional design techniques struggle with integration density and constantly strengthening requirements of today's nanometer technology. Timing-critical paths analysis is one of such tasks. It has applications in critical path identification, path delay fault simulation, circuit reliability analysis e.g. Bias Temperature Instability (BTI) induced aging, and in several others. In this paper, we propose a scalable simulation based hierarchical technique for explicit identification of true timing-critical paths in sequential circuits. We explore the circuits at two levels - at the flat gate-level and at a higher level as a network of modules or sub-circuits. The result of timing analysis carried out at the gate-level is used for calculating the delays on the topological critical paths through the network of higher level modules. To speed-up the module level timing analysis, the theory of Structurally Synthesized BDDs (SSBDD) is used. Experimental results demonstrate considerable speed-up of the SSBDD based timing analysis, compared to the flat gate-level analysis.
ABSTRACT A method is proposed for embedded fault diagnosis in digital systems using built-in self... more ABSTRACT A method is proposed for embedded fault diagnosis in digital systems using built-in self-test (BIST) facilities and pseudorandom test sequences. The novelty of the diagnostic strategy is in bisectioning of detected faults instead of traditional bisectioning of patterns in the test sequences. Opposite to the classical approach of fault diagnosis in digital circuits which targets all failing patterns, in the proposed method not all failing patterns are necessarily needed to be fixed for diagnosis. A possibility is analyzed to improve the diagnostic resolution by using multiple signature analyzers. Experimental results demonstrated the feasibility and efficiency of the approach.
IFIP Advances in Information and Communication Technology, 2020
We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testin... more We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testing microprocessors with RISC architecture to cover a large class of high-level functional faults. This is comparable to that used in memory testing which also covers a large class of structural faults such as stuck-at-faults (SAF), conditional SAF, multiple SAF and bridging faults. The approach is fully high-level, the model of the microprocessor is derived from the instruction set and architecture description, and no knowledge about gate-level implementation is needed. To keep the approach scalable, the microprocessor is partitioned into modules under test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, while for the control parts, a novel generic functional control fault model was developed. A novel method for measuring high-level fault coverage for the control parts of MUTs is proposed. The measure can be interpreted as the quality of covering the high-level functional faults, which are difficult to enumerate. We apply High-Level Decision Diagrams for formalization and optimization of high-level test generation for control parts of modules and for trading off different test characteristics, such as test length, test generation time and fault coverage. The test is well-structured and can be easily unrolled online during test execution. Experimental results demonstrate high SAF coverage, achieved for a part of a RISC processor with known implementation, whereas the test was generated without knowledge of implementation details.
2021 24th Euromicro Conference on Digital System Design (DSD), 2021
In this paper, a concept for generating tests for RISC processors is proposed relying solely on f... more In this paper, a concept for generating tests for RISC processors is proposed relying solely on functional information such as the instruction set without any knowledge of the implementation details. For the first time, the effect-cause idea, instead of the traditional cause-effect fault driven approach, is applied for test generation. For implementing the effect-cause idea, a novel high-level constraint-based functional fault model is developed. This novelty made it possible to extend the classical Stuck-At Fault (SAF) model, applied so far in evaluating the quality of processor testing, not only to a large class of structural faults, such as conditional SAF, bridging faults, delay faults etc., but also to the functional faults similar to those covered by the March algorithm in memory testing. By experimental research it was demonstrated that the test quality of the proposed implementation-independent test generation method produces test sequences with comparable or better fault coverages for SAF and Transition Delay Faults (TDF) than known methods utilizing knowledge about the implementation details.
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019
We propose a generic strategy for formalized synthesis of Software-Based Self-Test (SBST) for tes... more We propose a generic strategy for formalized synthesis of Software-Based Self-Test (SBST) for testing microprocessors with RISC architecture with the goal to achieve high gate-level fault coverage without knowing the gate-level implementation detail, and to have well-structured compact test, which can be easily unrolled on-line during test execution. The high-level model of the microprocessor is derived from the instruction set and from the architectural features introduced for increasing performance, like pipelining, forwarding, hazard handling, prediction, etc. A novel high-level functional control fault model is introduced, which has the capability of covering a broad class of gate-level faults. For the functional testing of data-path, bitwise pseudo-exhaustive test method is used. A novel method for measuring the high-level fault coverage is proposed. As an added value of the method, an efficient approach for identifying low-level redundant faults is described. Experimental results demonstrate high fault coverage achieved for MiniMIPS processor without using any information about gate-level implementation details.
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017
Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the tre... more Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the Network-on-Chip (NoC) paradigm has emerged to address the scalability and performance shortcomings of bus-based interconnects. As the feature size shrinks, the system gets much more susceptible to faults caused by wear-out and environmental effects. Thus, in order to increase the reliability, creates the need for having mechanisms embedded into such a system that could detect and manage the faults in run-time. In this paper, a ground-up approach from fault detection to fault management for such a NoC-based system on chip is proposed that utilizes both local fault management for fast reaction to faults and a global fault management mechanisms for triggering a large-scale reconfiguration of the NoC. Also, detailed description of strategies for fault detection, localization, classification and propagation to a global fault management unit are provided and methods for local fault management are elaborated.
2016 17th Latin-American Test Symposium (LATS), 2016
Continuous technology scaling poses reliability concerns that directly affect the Integrated Circ... more Continuous technology scaling poses reliability concerns that directly affect the Integrated Circuit's (IC) lifespan. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). Moreover, the impact of NBTI is exacerbated by Process Variation (PV), i.e. variations on transistor attributes during the manufacturing process. In this paper, a hierarchical model to compute NBTI-induced logic path delays at gate level considering PV is proposed. The model is applied in order to identify NBTI-critical logic paths of ICs that are subject to aging mitigation techniques. The model is derived based on intensive SPICE simulations of basic logic gates at transistor level under PV. The experimental results demonstrate an accurate fitting between the analysis performed on the proposed gate-level model and the electrical simulations, while the gate-level analysis provides for several orders of magnitude speed-up in simulation.
2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017
The advent of many-core system-on-chips (SoC) will involve new scalable hardware/software mechani... more The advent of many-core system-on-chips (SoC) will involve new scalable hardware/software mechanisms that can efficiently utilize the abundance of interconnected processing elements found in these SoCs. These trends will have a great impact on the strategies for testing the systems and improving their reliability by exploiting system's re-configurability to achieve graceful degradation of system's performance. We propose a strategy of Software-Based Self-Test (SBST) to be used for testing of processing elements in many-core systems with the goal to increase fault coverage and structuring the test routines in a way which makes test-data delivery in many-core systems more efficient. A new high-level fault model is introduced, which covers a broad class of gate-level Stuck-at-Faults (SAF), conditional SAF, and bridging faults of any multiplicity in processor control paths. Two algorithms for high-level simulation-based test generation for the control path and a bit-wise pseudo-exhaustive test approach for data path are proposed. No implementation details are needed for test data generation. A novel method for proving the redundancy of high-level functional faults is presented, which allows for precise evaluation of fault coverage.
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017
The recent advancements in the implementation technologies have brought to the front a wide spect... more The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a scalable simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like deciding the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The paper demonstrates an efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.
The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (BIST) fac... more The problem of embedded fault diagnosis in digital systems based on Built-In Self-Test (BIST) facilities is discussed. The main concern is related to the weak diagnostic capability of BIST. A BIST architecture is described which is based on multiple signature analyzers (SA) to provide better diagnostic resolution. A new conception for the diagnosis of digital circuits, which does not use fault models, and a method for calculating the diagnosibility of the given circuit are presented The results of calculation can be used for redesign of the circuit for better diagnosibility. Experimental results provide the data which characterize the diagnosibility for a family of ISCAS benchmark circuits.
The recent advancements in the implementation technologies have brought to the front a wide spect... more The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a fast simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like selecting the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The high scalability of the method is achieved by using a novel fast method for finding activated paths for many test patterns in parallel, a novel algorithm to determine only a small subset of critical paths, and a novel method for identifying the true critical paths among this subset, using branch and bound strategy. The paper demonstrates efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.
The paper presents a novel approach to high-level fault modeling and test generation for micropro... more The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general frame-work and novel techniques for automated software-based self-test program generation are discussed. On this basis new previously not published test quality improvement capabilities of the approach are high-lighted and explained. Based on the high level fault model defined for HLDDs a novel class of hard-to-test faults, called "unintended actions", is proposed. In addition, the mechanisms for reducing the risk of fault masking is explained. The experimental results show the superiority of the new method by achieving a higher quality of tests with shorter length compared to the previous results.
The importance of diagnostic test generation cannot be overemphasized as it is increasingly becom... more The importance of diagnostic test generation cannot be overemphasized as it is increasingly becoming important for diagnosing the complex circuits designed today. One approach is to use a test set that is generated originally for testing as the starting point so the diagnostic generator uses a deterministic approach to find diagnostic vectors that are then added to the original test set. But the challenge with the deterministic approach is with its high computational cost and time. We propose a novel semi-random diagnostic generator which is inspired from the simplicity and speed a random ATPG for test generation has. Two methods are presented and our investigation shows that this semi-random approach improves the diagnostic resolution and has a lesser computational cost and time.
In this paper we present a very fast fault simulation method for sequential circuits, which is ba... more In this paper we present a very fast fault simulation method for sequential circuits, which is based on accommodation of exact parallel critical path tracing in combinational circuits for using it also in case of sequential circuits. Formulas are developed for parallel on-line analysis of the faults to classify them into two classes, which are eligible for combinational simulation, and which are not. The latter class of faults has to be simulated by any conventional fault simulation method used for sequential circuits. Combining two approaches to fault simulation - the combinational and sequential ones - allows dramatic speed-up of fault simulation in sequential circuits, which is demonstrated by experimental results.
The main objective of this work is to develop a method and to create a tool for random test patte... more The main objective of this work is to develop a method and to create a tool for random test pattern generation for digital circuits, capable of achieving a high diagnostic resolution. We propose a measure for evaluating the diagnostic resolution of a given test set. Three methods were investigated using different criterions for selecting test patterns from the given packages of random vectors. The chosen criterion targets the diagnostic resolution as high as possible at the minimum test length and the maximum fault coverage. Experimental research demonstrated that the proposed tool provides the test engineer with better diagnostic resolutions compared to other comparable test generation methods.
We propose a method for synthesis of Software-Based Self-Test (SBST) for testing RISC type of mic... more We propose a method for synthesis of Software-Based Self-Test (SBST) for testing RISC type of microprocessors without needing the knowledge of implementation details. The test covers a large class of faults and a special target is to detect Transition Delay Faults (TDF). To reduce the complexity, the processor is partitioned into Modules Under Test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, whereas for the control parts a novel functional control fault model was developed. The test is regular, represented in a compact form allowing easy unrolling during test execution. Experimental results demonstrate high Stuck-At Fault (SAF) and TDF coverage, despite the lack of knowledge of implementation details
Recent safety standards set stringent requirements for the target fault coverage in embedded micr... more Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementationindependent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudoexhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor.
The conventional design techniques struggle with integration density and constantly strengthening... more The conventional design techniques struggle with integration density and constantly strengthening requirements of today's nanometer technology. Timing-critical paths analysis is one of such tasks. It has applications in critical path identification, path delay fault simulation, circuit reliability analysis e.g. Bias Temperature Instability (BTI) induced aging, and in several others. In this paper, we propose a scalable simulation based hierarchical technique for explicit identification of true timing-critical paths in sequential circuits. We explore the circuits at two levels - at the flat gate-level and at a higher level as a network of modules or sub-circuits. The result of timing analysis carried out at the gate-level is used for calculating the delays on the topological critical paths through the network of higher level modules. To speed-up the module level timing analysis, the theory of Structurally Synthesized BDDs (SSBDD) is used. Experimental results demonstrate considerable speed-up of the SSBDD based timing analysis, compared to the flat gate-level analysis.
ABSTRACT A method is proposed for embedded fault diagnosis in digital systems using built-in self... more ABSTRACT A method is proposed for embedded fault diagnosis in digital systems using built-in self-test (BIST) facilities and pseudorandom test sequences. The novelty of the diagnostic strategy is in bisectioning of detected faults instead of traditional bisectioning of patterns in the test sequences. Opposite to the classical approach of fault diagnosis in digital circuits which targets all failing patterns, in the proposed method not all failing patterns are necessarily needed to be fixed for diagnosis. A possibility is analyzed to improve the diagnostic resolution by using multiple signature analyzers. Experimental results demonstrated the feasibility and efficiency of the approach.
IFIP Advances in Information and Communication Technology, 2020
We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testin... more We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testing microprocessors with RISC architecture to cover a large class of high-level functional faults. This is comparable to that used in memory testing which also covers a large class of structural faults such as stuck-at-faults (SAF), conditional SAF, multiple SAF and bridging faults. The approach is fully high-level, the model of the microprocessor is derived from the instruction set and architecture description, and no knowledge about gate-level implementation is needed. To keep the approach scalable, the microprocessor is partitioned into modules under test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, while for the control parts, a novel generic functional control fault model was developed. A novel method for measuring high-level fault coverage for the control parts of MUTs is proposed. The measure can be interpreted as the quality of covering the high-level functional faults, which are difficult to enumerate. We apply High-Level Decision Diagrams for formalization and optimization of high-level test generation for control parts of modules and for trading off different test characteristics, such as test length, test generation time and fault coverage. The test is well-structured and can be easily unrolled online during test execution. Experimental results demonstrate high SAF coverage, achieved for a part of a RISC processor with known implementation, whereas the test was generated without knowledge of implementation details.
2021 24th Euromicro Conference on Digital System Design (DSD), 2021
In this paper, a concept for generating tests for RISC processors is proposed relying solely on f... more In this paper, a concept for generating tests for RISC processors is proposed relying solely on functional information such as the instruction set without any knowledge of the implementation details. For the first time, the effect-cause idea, instead of the traditional cause-effect fault driven approach, is applied for test generation. For implementing the effect-cause idea, a novel high-level constraint-based functional fault model is developed. This novelty made it possible to extend the classical Stuck-At Fault (SAF) model, applied so far in evaluating the quality of processor testing, not only to a large class of structural faults, such as conditional SAF, bridging faults, delay faults etc., but also to the functional faults similar to those covered by the March algorithm in memory testing. By experimental research it was demonstrated that the test quality of the proposed implementation-independent test generation method produces test sequences with comparable or better fault coverages for SAF and Transition Delay Faults (TDF) than known methods utilizing knowledge about the implementation details.
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019
We propose a generic strategy for formalized synthesis of Software-Based Self-Test (SBST) for tes... more We propose a generic strategy for formalized synthesis of Software-Based Self-Test (SBST) for testing microprocessors with RISC architecture with the goal to achieve high gate-level fault coverage without knowing the gate-level implementation detail, and to have well-structured compact test, which can be easily unrolled on-line during test execution. The high-level model of the microprocessor is derived from the instruction set and from the architectural features introduced for increasing performance, like pipelining, forwarding, hazard handling, prediction, etc. A novel high-level functional control fault model is introduced, which has the capability of covering a broad class of gate-level faults. For the functional testing of data-path, bitwise pseudo-exhaustive test method is used. A novel method for measuring the high-level fault coverage is proposed. As an added value of the method, an efficient approach for identifying low-level redundant faults is described. Experimental results demonstrate high fault coverage achieved for MiniMIPS processor without using any information about gate-level implementation details.
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017
Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the tre... more Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the Network-on-Chip (NoC) paradigm has emerged to address the scalability and performance shortcomings of bus-based interconnects. As the feature size shrinks, the system gets much more susceptible to faults caused by wear-out and environmental effects. Thus, in order to increase the reliability, creates the need for having mechanisms embedded into such a system that could detect and manage the faults in run-time. In this paper, a ground-up approach from fault detection to fault management for such a NoC-based system on chip is proposed that utilizes both local fault management for fast reaction to faults and a global fault management mechanisms for triggering a large-scale reconfiguration of the NoC. Also, detailed description of strategies for fault detection, localization, classification and propagation to a global fault management unit are provided and methods for local fault management are elaborated.
2016 17th Latin-American Test Symposium (LATS), 2016
Continuous technology scaling poses reliability concerns that directly affect the Integrated Circ... more Continuous technology scaling poses reliability concerns that directly affect the Integrated Circuit's (IC) lifespan. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). Moreover, the impact of NBTI is exacerbated by Process Variation (PV), i.e. variations on transistor attributes during the manufacturing process. In this paper, a hierarchical model to compute NBTI-induced logic path delays at gate level considering PV is proposed. The model is applied in order to identify NBTI-critical logic paths of ICs that are subject to aging mitigation techniques. The model is derived based on intensive SPICE simulations of basic logic gates at transistor level under PV. The experimental results demonstrate an accurate fitting between the analysis performed on the proposed gate-level model and the electrical simulations, while the gate-level analysis provides for several orders of magnitude speed-up in simulation.
2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017
The advent of many-core system-on-chips (SoC) will involve new scalable hardware/software mechani... more The advent of many-core system-on-chips (SoC) will involve new scalable hardware/software mechanisms that can efficiently utilize the abundance of interconnected processing elements found in these SoCs. These trends will have a great impact on the strategies for testing the systems and improving their reliability by exploiting system's re-configurability to achieve graceful degradation of system's performance. We propose a strategy of Software-Based Self-Test (SBST) to be used for testing of processing elements in many-core systems with the goal to increase fault coverage and structuring the test routines in a way which makes test-data delivery in many-core systems more efficient. A new high-level fault model is introduced, which covers a broad class of gate-level Stuck-at-Faults (SAF), conditional SAF, and bridging faults of any multiplicity in processor control paths. Two algorithms for high-level simulation-based test generation for the control path and a bit-wise pseudo-exhaustive test approach for data path are proposed. No implementation details are needed for test data generation. A novel method for proving the redundancy of high-level functional faults is presented, which allows for precise evaluation of fault coverage.
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017
The recent advancements in the implementation technologies have brought to the front a wide spect... more The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a scalable simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like deciding the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The paper demonstrates an efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.
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Papers by Raimund Ubar