Papers by Abhijit Chatterjee
Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatte... more Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatterjee $ Jacob A. Abraham t ... John Wiley and Sons. [2] DK Pradhan and S. Gupta. A new framework for designing and analyzing BIST techniques and zero aliasing compression. ...
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2000
In this paper, a new methodology for generating transient tests to detect faults in analog circui... more In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits
Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatte... more Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatterjee $ Jacob A. Abraham t ... John Wiley and Sons. [2] DK Pradhan and S. Gupta. A new framework for designing and analyzing BIST techniques and zero aliasing compression. ...
Journal of Electronic Testing, 1993
Research in the areas of analog circuit fault simulation and test generation has not achieved the... more Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2000
In this paper, a new methodology for generating transient tests to detect faults in analog circui... more In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits
Journal of Electronic Testing, 1993
Research in the areas of analog circuit fault simulation and test generation has not achieved the... more Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.
Recognizing that specification testing of analog cir-cuits involves a high cost and lacks any qua... more Recognizing that specification testing of analog cir-cuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique, With the help of hierarchical fault mod-els for parametric and catastrophic faults, and a very eficient fault simulator, our ...
Recognizing that specification testing of analog cir-cuits involves a high cost and lacks any qua... more Recognizing that specification testing of analog cir-cuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique, With the help of hierarchical fault mod-els for parametric and catastrophic faults, and a very eficient fault simulator, our ...
Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatte... more Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatterjee $ Jacob A. Abraham t ... John Wiley and Sons. [2] DK Pradhan and S. Gupta. A new framework for designing and analyzing BIST techniques and zero aliasing compression. ...
Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatte... more Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatterjee $ Jacob A. Abraham t ... John Wiley and Sons. [2] DK Pradhan and S. Gupta. A new framework for designing and analyzing BIST techniques and zero aliasing compression. ...
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2000
In this paper, a new methodology for generating transient tests to detect faults in analog circui... more In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits
Page 1. DRAFTS: Discretized Analog Circuit Fault Simulator * Naveena Nagi ~ Abhijit Chatterjee $ ... more Page 1. DRAFTS: Discretized Analog Circuit Fault Simulator * Naveena Nagi ~ Abhijit Chatterjee $ Jacob A. Abraham ~ t Computer Engg. Research Center, University of Texas at Austin, Austin, TX $ School of Elec. Engg., Georgia Inst. of Tech., Atlanta, GA ...
Page 1. DRAFTS: Discretized Analog Circuit Fault Simulator * Naveena Nagi ~ Abhijit Chatterjee $ ... more Page 1. DRAFTS: Discretized Analog Circuit Fault Simulator * Naveena Nagi ~ Abhijit Chatterjee $ Jacob A. Abraham ~ t Computer Engg. Research Center, University of Texas at Austin, Austin, TX $ School of Elec. Engg., Georgia Inst. of Tech., Atlanta, GA ...
Journal of Electronic Testing, 1993
Research in the areas of analog circuit fault simulation and test generation has not achieved the... more Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2000
In this paper, a new methodology for generating transient tests to detect faults in analog circui... more In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits
Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatte... more Page 1. A Signature Analyzer for Analog and Mixed-signal Circuits * Naveena Nagi t Abhijit Chatterjee $ Jacob A. Abraham t ... John Wiley and Sons. [2] DK Pradhan and S. Gupta. A new framework for designing and analyzing BIST techniques and zero aliasing compression. ...
IEEE Design & Test of Computers, 1996
DC testing of analog circuits is cheaper than AC testing and covers many fault classes, including... more DC testing of analog circuits is cheaper than AC testing and covers many fault classes, including some that AC tests cannot detect. This efficient, low-cost, built-in self-test (BIST) methodology uses the checksum encodings of matrix representations to uncover faults that affect a circuit's DC transfer function
Recognizing that specification testing of analog cir-cuits involves a high cost and lacks any qua... more Recognizing that specification testing of analog cir-cuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique, With the help of hierarchical fault mod-els for parametric and catastrophic faults, and a very eficient fault simulator, our ...
IEEE Design & Test of Computers, 1996
DC testing of analog circuits is cheaper than AC testing and covers many fault classes, including... more DC testing of analog circuits is cheaper than AC testing and covers many fault classes, including some that AC tests cannot detect. This efficient, low-cost, built-in self-test (BIST) methodology uses the checksum encodings of matrix representations to uncover faults that affect a circuit's DC transfer function
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2000
In this paper, a new methodology for generating transient tests to detect faults in analog circui... more In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits
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Papers by Abhijit Chatterjee