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2005, Microwave and Optical Technology Letters
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5 pages
1 file
In this paper, we introduce a 5-GHz injection-locked phase-locked loop (ILPLL). A new method is presented for accurate analysis of the phase-noise performance of the proposed system. Furthermore, comparison with other phase-noise-estimation techniques demonstrates that our method provides an accurate characterization of any ILPLL topology. The theoretical and calculation results show an improved performance for phase noise, locking range, and power consumption compared to conventional phase-locked loops (PLLs) and injection-locked oscillators (ILOs). Furthermore, we demonstrate the pulling behavior of the injected oscillator and examine the obtained results. To verify the presented analysis, a 5-GHz prototype has been implemented, which achieves Ϫ119-dBc/Hz at 100-KHz frequency offset, producing ϩ4.5 dBm of output power and consuming 9 mA at 3 V.
Electronics and Communications, 2011
A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead
2011
This paper presents a simple, unified phase noise model for injection-locked oscillators (ILO). We show that an ILO is identical to a type-I first-order PLL in its noise behavior within the lock range. The model predicts the phase noise of injection-locked oscillators (ILO), injection-locked frequency dividers (ILFD), and injection-locked frequency multipliers (ILFM) as a function of the injection source phase noise and the oscillator phase noise. Measurement results from a discrete 57MHz Colpitts ILO, an integrated 6.5GHz ILFD, and an integrated 24GHz ILFM are presented to validate the theoretical predictions.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017
In this paper, we use synchronization to reduce Phase-Locked Loop (PLL) phase noise and improve its locking behavior with an attenuated reference signal injection (RI) into a voltage controlled CMOS delay-line ring-type oscillator. The transient and steady-state behavior of the PLL-RI are described by a nonlinear differential equation, which is further studied by the phase-plane method. The nonlinear equation is linearized for the small-signal condition and the s-domain noise transfer functions and noise bandwidths for different noise sources are derived. The effect of the loop parameters and the injection strength on the output phase noise, loop settling time, and lock in range is analyzed. Finally, the analysis is verified by the SPICE simulation and measurement results from an 1-GHz PLL-RI with 130nm standard RF CMOS technology. Simulation and measurement results show phase noise reduction and improved settling behavior of a PLL-RI compared to a conventional PLL.
Microwave and Optical Technology Letters, 2006
bands. The measured peak gains are better than 4.55 and 5.24 dBi in 2.4 and 5.2 GHz operation bands, respectively. 4. CONCLUSION A printed T-shaped slot antenna is proposed for the dual-band WLAN operation. By using the T-shaped slot, two resonant modes are excited where one resonant mode is controlled to operate at 2.4-GHz-band and the other is controlled to operate at 5.2-GHzband. Good agreement between the measured and simulated results verifies the design of the proposed antenna. The measured impedance bandwidths are 2.18-2.85 GHz and 4.96-5.5 GHz for VSWR Յ2 and are sufficient for the two bands of WLAN standard. The measured gains are better than 4.55 and 5.24 dBi at 2.4-GHz-and 5.2-GHz-Band, respectively.
Electronics Letters, 2010
A fully differential sub-harmonic injection-locked phase-locked loop (PLL) that achieves improved levels of phase noise performance through the incorporation of injection locking and fully differential architecture is presented. Details concerning the design of each building block are given and the corresponding simulation results are presented. The system level architecture exploration is introduced together with the phase noise analysis. A physical implementation of the proposed design using a standard 0.5 mm SiGe BiCMOS process is also presented as a case study in order to prove the functionality as well as the overall performance. Phase noise improvement is 20 dB at 1 kHz when a sub-harmonic of the free-running oscillation frequency at 2.5 GHz with a 215 dBm power level is injected.
Micromachines
Low-phase noise and wideband phased-locked loops (PLLs) are crucial for high-data rate communication and imaging systems. Sub-millimeter-wave (sub-mm-wave) PLLs typically exhibit poor performance in terms of noise and bandwidth due to higher device parasitic capacitances, among other reasons. In this regard, a low-phase-noise, wideband, integer-N, type-II phase-locked loop was implemented in the 22 nm FD-SOI CMOS process. The proposed wideband linear differential tuning I/Q voltage-controlled oscillator (VCO) achieves an overall frequency range of 157.5–167.5 GHz with 8 GHz linear tuning and a phase noise of −113 dBc/Hz @ 100 KHz. Moreover, the fabricated PLL produces a phase noise less than −103 dBc/Hz @ 1 KHz and −128 dBc/Hz @ 100 KHz, corresponding to the lowest phase noise generated by a sub-millimeter-wave PLL to date. The measured RF output saturated power and DC power consumption of the PLL are 2 dBm and 120.75 mW, respectively, whereas the fabricated chip comprising a power ...
IEEE Transactions on Circuits and Systems II: Express Briefs, 2008
This paper presents a multifunctional circuit realizing the functions of oscillation, mixing, amplification, and frequency multiplication at 5 GHz. A theoretical and experimental description of the circuit is given. The proposed circuit, which combines both the injection-locking and mixing processes, uses only one port where both the RF/intermediate frequency signal and the injection signal (IS) are applied. The IS, which is used to stabilize the oscillation, is at a subharmonic of the oscillation frequency (osc 4) having a power level as low as 50 dBm. Calculations of the phase noise and measurements of the mixing properties are reported which indicate a noise improvement, and a high up-conversion gain. The implementation of the circuit exhibits an up-conversion gain of 14 dB, a phase noise of 110 dBc/Hz at 100-kHz offset, a P 1 dB of 15 dBm, a third-order intercept point of 2 dBm, and a power consumption of 35 mW. Calculated and measured results are in good agreement for all cases, emphasizing the relevance of the proposed circuit.
International Journal of Scientific Research in Science and Technology, 2014
In the era of big data, the exponential growth of data poses significant challenges for storage, leading many entities to migrate their data to cloud storage services. While cloud storage offers numerous advantages, it also introduces substantial risks, including the potential loss or unauthorized modification of data by service providers. The extensive data gathered in the cloud, originating from various datasets and storage devices necessitates a thorough analysis of storage performance. Each data instance is defined by specific features, while devices are characterized by their hardware or software components. General restrictions for data allocation and device capacity are also considered. The computation of structural constraints is based on the interactions between cloud-based devices and data instances. In order to address these issues, we introduce a hybrid artificial intelligence approach that is lightweight and ideal for constraint optimization. It focuses on auditable secure cloud storage with dynamic data. Our approach begins with the development of the enhanced electric fish optimization (EEFO) algorithm for constraints optimization to ensure the integrity of data stored in the cloud. To accommodate dynamic data operations, including block modification, insertion, and deletion, we employ the triple tree-seed algorithm (TTSA) to record the location of each data operation within the system. The proposed model's performance is validated, and results are systematically analyzed, compared against existing approaches, demonstrating its effectiveness in appropriately managing cloud data.
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