injection locked oscillator

We present a model for injection-locked oscillator (ILO) phase shifter that includes high-frequency coupling through a Silicon substrate. In this model, we consider conductive and resistive features of the substrate and predict the locking range and phase shift in the presence of substrate coupling. The model is verified through agreement with Cadence simulations and measurements. The phase shifter measurements are verified in a 2 × 2 injection-locked oscillator array operating from 15.5 to 18.5 GHz implemented in 90-nm GlobalFoundries SiGe BiCMOS technology. A 71–86 GHz 2 × 2 phased array uses this injection-locked phase shifter where the high frequency parasitics play an important role in the circuit performance.

This paper presents a data jitter mixing forwarded-clock receiver which is robust against power supply induced jitter (PSIJ) and overcomes 1.92ns latency mismatch between data and clock. The forwarded-clock architecture has a tradeoff between the number of clock channels and the achievable data rate due to the lack of the jitter correlation between data and clock. Moreover, PSIJ due to a long clock distribution network and an injection-locked oscillator reduces the jitter correlation further. The proposed receiver eases this tradeoff, and also increases the jitter correlation reduced by PSIJ. The test chip achieves 9.6Gb/s with 1.22mW/Gb/s and occupies only 0.017mm2 in 65nm CMOS.