ECTI Transactions on Electrical Engineering, Electronics, and Communications, 2007
The Low Noise Ampli¯er (LNA) presented in this work is a 3-stage fully integrated Distributed Amp... more The Low Noise Ampli¯er (LNA) presented in this work is a 3-stage fully integrated Distributed Amplifier (DA) using a 0.35 ¹m BiCMOS SiGe process. The circuit was designed for integration and for this reason the di®erent parasitical phenomena that concern the spiral inductors and the packaging were evaluated in detail. Noise Figure (NF) and linearity were also investigated through simulations. The designed amplifier offers a gain of about 7 dB with a gain flatness of 0.6 dB over the bandwidth 0.5-5.5 GHz and an average noise ¯gure of 3.2 dB. The RF input port is matched to 50 , with worst-case return loss of 10 dB over the whole bandwidth. The input-referred P1dB point varies from 2.2 dBm at 1 GHz to 3.1 dBm at 5 GHz. Within the same bandwidth the IP3 varies from 6 dBm to 13.3 dBm. The estimated power consumption is 82.5 mW from a 3V power supply.
SUMMARY Subharmonic injection-locking and self-oscillating mixing functions of a modified Colpitt... more SUMMARY Subharmonic injection-locking and self-oscillating mixing functions of a modified Colpitts oscillator operating at 1GHz are reported. The injection-locking circuit, using a GaAs FET, is described theoretically and experimentally. Phase noise, power consumption and conversion gain measurements indicate that the proposed design is attractive for low-cost, low-power consumption front-ends. Copyright q 2008 John Wiley & Sons, Ltd.
ECTI Transactions on Electrical Engineering, Electronics, and Communications, 2007
The Low Noise Ampli¯er (LNA) presented in this work is a 3-stage fully integrated Distributed Amp... more The Low Noise Ampli¯er (LNA) presented in this work is a 3-stage fully integrated Distributed Amplifier (DA) using a 0.35 ¹m BiCMOS SiGe process. The circuit was designed for integration and for this reason the di®erent parasitical phenomena that concern the spiral inductors and the packaging were evaluated in detail. Noise Figure (NF) and linearity were also investigated through simulations. The designed amplifier offers a gain of about 7 dB with a gain flatness of 0.6 dB over the bandwidth 0.5-5.5 GHz and an average noise ¯gure of 3.2 dB. The RF input port is matched to 50 , with worst-case return loss of 10 dB over the whole bandwidth. The input-referred P1dB point varies from 2.2 dBm at 1 GHz to 3.1 dBm at 5 GHz. Within the same bandwidth the IP3 varies from 6 dBm to 13.3 dBm. The estimated power consumption is 82.5 mW from a 3V power supply.
The Low Noise Amplifier (LNA) presented in this work offers a gain of 20 dB, a noise figure of 1.... more The Low Noise Amplifier (LNA) presented in this work offers a gain of 20 dB, a noise figure of 1.6 dB, with an input referred third-order intercept point of -4.5 dBm and a 1 dB compression point of -16 dBm at 5.2 GHz, using 0.35 μm BiCMOS SiGe. It operates on 5 V and requires 10 mA. The output and the input of the amplifier are matched internally to 50 Ω. The amplifier includes an image reject filter, an adaptive bias network, an RLC tank and input/output balun transformers. The image reject filter attenuates the image signal by providing low impedance at that frequency and is tuned by voltage control. An adaptive bias network is used, which allows the user to select the bias current in an adaptive manner, depending upon the requirements of the individual system (low NF, high gain, low consumption etc.).
2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010
ABSTRACT In this work a dynamic strobe masking system (DSMS) for DDR memory interfaces is present... more ABSTRACT In this work a dynamic strobe masking system (DSMS) for DDR memory interfaces is presented which works with existing DFI signals to provide dynamic masking and produces a clean strobe suitable for data capture, making it the first dynamic DFI-compatible strobe qualification system. This DSMS scheme produces a masking signal to qualify the expected pulse stream on the DQS line, thus masking out other spurious activity. Post layout simulation results in TSMC 90 nm process validate the proposed masking system in the 200-533 MHz range, meeting the mask shut-off specification in best, typical, and worst case corners.
2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010
... REFERENCES [I] U. Karthaus, M.Fischer, "Fully integrated passive UHF RFID transp... more ... REFERENCES [I] U. Karthaus, M.Fischer, "Fully integrated passive UHF RFID transponder IC with 16.7-flW minimum RF input power," IEEE J ... 2007 [8] A Shameli, A Safarian, A. Rofougaran, M. Rofougaran, FD Flaviis, "Power Harvester Design for Passive UHF RFID Tag using a ...
2010 IEEE Computer Society Annual Symposium on VLSI, 2010
An innovative design of a 533 MHz DDR2 SDRAM PHY based on a common standard bus interface (DFI) a... more An innovative design of a 533 MHz DDR2 SDRAM PHY based on a common standard bus interface (DFI) and implemented in 90 nm standard CMOS process, is presented in this paper. Off-chip driver with calibrated strength, slew rate control, and on-die termination mechanism are utilized to provide improved signal integrity. Furthermore a DDR3-like I/O architecture and an appropriate calibration mechanism
In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator i... more In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator is designed in TSMC 0.18 mm CMOS technology as a part of a ultra wideband FM (UWBFM) transmitter. The VCO includes a current-controlled oscillator (CCO) which generates output frequencies between 1.5 and 2.8 GHz and a voltage-to-current (V-to-I) converter. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range achieving oscillation frequencies between 3 and 5.6 GHz. Thus, the well-known proportionality between the oscillation frequency and the bias tuning current in CCOs is avoided for the entire achieved tuning range, resulting in a lower power design. The employed architecture provides high suppression, over 45 dB, of the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The current consumption is 5 mA at a supply voltage of 1.8 V. The VCO exhibits a phase noise of À80.56 dBc/Hz at 1 MHz frequency offset from the carrier and a very high ratio of tuning range (60.4%) over power consumption equal to 8.26 dB which is essential for a UWBFM transmitter.
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)
ABSTRACT A bipolar low noise amplifier (LNA) is described in this work. The IC contains the LNA c... more ABSTRACT A bipolar low noise amplifier (LNA) is described in this work. The IC contains the LNA core, an externally programmed bias network, a voltage divider, an LC tank and inductors to set the input impedance. The externally programmed bias network allows the user to select the bias current in an adaptive manner, depending upon the requirements of the individual system. (Low NF, high gain, low consumption etc). The chip can be powered down by sending an appropriate bit stream to the bias network. The tuned amplifier using a parallel LC network provides selective amplification and lower power consumption. The produced gain is 15 dB while the NF is 2.1 dB for moderate power consumption. The IIP3 is -7 dB and the P1dB is -17 dB. The power consumption from a single 5-V supply is 3.4 mA for the low gain mode and 13 mA for the high gain mode.
2007 IEEE International Symposium on Circuits and Systems, 2007
A subharmonic injection-locked self-oscillating mixer (s-ILSOM) at 1 GHz is reported in this pape... more A subharmonic injection-locked self-oscillating mixer (s-ILSOM) at 1 GHz is reported in this paper. The proposed circuit which combines both injection-locking and mixing functions is described theoretically and experimentally. In contrast to previously reported works, only one input port is required for both the RF/IF signal and the injection signal. Furthermore, the injection signal which is used to stabilize the oscillation is at a subharmonic of the oscillation frequency (fLO/4), with a power level as low as -20 dBm. Phase noise calculations and mixing characteristics are reported, indicating a noise improvement, and a high up-conversion gain for both fundamental and harmonic mixing. The circuit is implemented, using a GaAs FET, exhibiting an up-conversion gain of 13 dB, a phase noise of -93 dBc/Hz at 100 KHz offset, a P1dB of -18 dBm, an IP3 of -5 dBm, and a power consumption of 24 mW.
bands. The measured peak gains are better than 4.55 and 5.24 dBi in 2.4 and 5.2 GHz operation ban... more bands. The measured peak gains are better than 4.55 and 5.24 dBi in 2.4 and 5.2 GHz operation bands, respectively. 4. CONCLUSION A printed T-shaped slot antenna is proposed for the dual-band WLAN operation. By using the T-shaped slot, two resonant modes are excited where one resonant mode is controlled to operate at 2.4-GHz-band and the other is controlled to operate at 5.2-GHzband. Good agreement between the measured and simulated results verifies the design of the proposed antenna. The measured impedance bandwidths are 2.18-2.85 GHz and 4.96-5.5 GHz for VSWR Յ2 and are sufficient for the two bands of WLAN standard. The measured gains are better than 4.55 and 5.24 dBi at 2.4-GHz-and 5.2-GHz-Band, respectively.
In this paper, we introduce a 5-GHz injection-locked phase-locked loop (ILPLL). A new method is p... more In this paper, we introduce a 5-GHz injection-locked phase-locked loop (ILPLL). A new method is presented for accurate analysis of the phase-noise performance of the proposed system. Furthermore, comparison with other phase-noise-estimation techniques demonstrates that our method provides an accurate characterization of any ILPLL topology. The theoretical and calculation results show an improved performance for phase noise, locking range, and power consumption compared to conventional phase-locked loops (PLLs) and injection-locked oscillators (ILOs). Furthermore, we demonstrate the pulling behavior of the injected oscillator and examine the obtained results. To verify the presented analysis, a 5-GHz prototype has been implemented, which achieves Ϫ119-dBc/Hz at 100-KHz frequency offset, producing ϩ4.5 dBm of output power and consuming 9 mA at 3 V.
ABSTRACT A 1V, programmable, accurate, high speed, single-ended charge pump is proposed, suitable... more ABSTRACT A 1V, programmable, accurate, high speed, single-ended charge pump is proposed, suitable for low voltage PLLs. It is designed in TSMC 90-nm digital CMOS process and it consists of four switches in a current steering configuration, a unity gain rail to rail buffer for the charge sharing effect elimination, one more rail to rail amplifier for minimizing the DC current mismatch, a programmable current bias circuitry and two drivers based on the standard cell XOR gates specific configuration for achieving good synchronization between all charge pump input pulses at the PLL lock state. Replica biasing technique is applied to all charge pump switches. Current glitches and charge mismatch are suppressed by employing a mechanism with additional switches at the output. It exhibits a maximum DC current mismatch of 1% and charge mismatch of 6% over a wide output voltage range of 0.7V for the entire range of output currents. The wide range of the output voltage remains relatively constant and independent of the selected charge pump current amplitude. This is attained by applying appropriate variation of the W/L ratios of the bias cascode current sources via the employment of additional programmable switches such that their saturation voltages remain relatively constant, something which in turn enables the output currents range to be as wide as it is required.
This paper presents the analysis and experimental evaluation of a modified dual-loop phase-locked... more This paper presents the analysis and experimental evaluation of a modified dual-loop phase-locked loop synthesizer, using the phase noise transfer functions resulting from the linear model of the synthesizer. The different arrangement in the high-frequency loop, in contrast to previous reported series-connected dual-loop topologies, offers various advantages, such as improved phase noise, finer resolution, and lower spurious levels. Discrete elements are used to implement a prototype system for testing. This adds to the flexibility of the design and allows for experimental optimization of the loop trade-offs. The synthesizer generates signals in the 4850 MHz to 5050 MHz range with a 10 MHz resolution and can match the specifications for wireless LANs operating at 5 GHz. The design resulted in a prototype with very good characteristics suitable for future integration.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2008
This paper presents a multifunctional circuit realizing the functions of oscillation, mixing, amp... more This paper presents a multifunctional circuit realizing the functions of oscillation, mixing, amplification, and frequency multiplication at 5 GHz. A theoretical and experimental description of the circuit is given. The proposed circuit, which combines both the injection-locking and mixing processes, uses only one port where both the RF/intermediate frequency signal and the injection signal (IS) are applied. The IS, which is used to stabilize the oscillation, is at a subharmonic of the oscillation frequency (osc 4) having a power level as low as 50 dBm. Calculations of the phase noise and measurements of the mixing properties are reported which indicate a noise improvement, and a high up-conversion gain. The implementation of the circuit exhibits an up-conversion gain of 14 dB, a phase noise of 110 dBc/Hz at 100-kHz offset, a P 1 dB of 15 dBm, a third-order intercept point of 2 dBm, and a power consumption of 35 mW. Calculated and measured results are in good agreement for all cases, emphasizing the relevance of the proposed circuit.
ECTI Transactions on Electrical Engineering, Electronics, and Communications, 2007
The Low Noise Ampli¯er (LNA) presented in this work is a 3-stage fully integrated Distributed Amp... more The Low Noise Ampli¯er (LNA) presented in this work is a 3-stage fully integrated Distributed Amplifier (DA) using a 0.35 ¹m BiCMOS SiGe process. The circuit was designed for integration and for this reason the di®erent parasitical phenomena that concern the spiral inductors and the packaging were evaluated in detail. Noise Figure (NF) and linearity were also investigated through simulations. The designed amplifier offers a gain of about 7 dB with a gain flatness of 0.6 dB over the bandwidth 0.5-5.5 GHz and an average noise ¯gure of 3.2 dB. The RF input port is matched to 50 , with worst-case return loss of 10 dB over the whole bandwidth. The input-referred P1dB point varies from 2.2 dBm at 1 GHz to 3.1 dBm at 5 GHz. Within the same bandwidth the IP3 varies from 6 dBm to 13.3 dBm. The estimated power consumption is 82.5 mW from a 3V power supply.
SUMMARY Subharmonic injection-locking and self-oscillating mixing functions of a modified Colpitt... more SUMMARY Subharmonic injection-locking and self-oscillating mixing functions of a modified Colpitts oscillator operating at 1GHz are reported. The injection-locking circuit, using a GaAs FET, is described theoretically and experimentally. Phase noise, power consumption and conversion gain measurements indicate that the proposed design is attractive for low-cost, low-power consumption front-ends. Copyright q 2008 John Wiley & Sons, Ltd.
ECTI Transactions on Electrical Engineering, Electronics, and Communications, 2007
The Low Noise Ampli¯er (LNA) presented in this work is a 3-stage fully integrated Distributed Amp... more The Low Noise Ampli¯er (LNA) presented in this work is a 3-stage fully integrated Distributed Amplifier (DA) using a 0.35 ¹m BiCMOS SiGe process. The circuit was designed for integration and for this reason the di®erent parasitical phenomena that concern the spiral inductors and the packaging were evaluated in detail. Noise Figure (NF) and linearity were also investigated through simulations. The designed amplifier offers a gain of about 7 dB with a gain flatness of 0.6 dB over the bandwidth 0.5-5.5 GHz and an average noise ¯gure of 3.2 dB. The RF input port is matched to 50 , with worst-case return loss of 10 dB over the whole bandwidth. The input-referred P1dB point varies from 2.2 dBm at 1 GHz to 3.1 dBm at 5 GHz. Within the same bandwidth the IP3 varies from 6 dBm to 13.3 dBm. The estimated power consumption is 82.5 mW from a 3V power supply.
The Low Noise Amplifier (LNA) presented in this work offers a gain of 20 dB, a noise figure of 1.... more The Low Noise Amplifier (LNA) presented in this work offers a gain of 20 dB, a noise figure of 1.6 dB, with an input referred third-order intercept point of -4.5 dBm and a 1 dB compression point of -16 dBm at 5.2 GHz, using 0.35 μm BiCMOS SiGe. It operates on 5 V and requires 10 mA. The output and the input of the amplifier are matched internally to 50 Ω. The amplifier includes an image reject filter, an adaptive bias network, an RLC tank and input/output balun transformers. The image reject filter attenuates the image signal by providing low impedance at that frequency and is tuned by voltage control. An adaptive bias network is used, which allows the user to select the bias current in an adaptive manner, depending upon the requirements of the individual system (low NF, high gain, low consumption etc.).
2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010
ABSTRACT In this work a dynamic strobe masking system (DSMS) for DDR memory interfaces is present... more ABSTRACT In this work a dynamic strobe masking system (DSMS) for DDR memory interfaces is presented which works with existing DFI signals to provide dynamic masking and produces a clean strobe suitable for data capture, making it the first dynamic DFI-compatible strobe qualification system. This DSMS scheme produces a masking signal to qualify the expected pulse stream on the DQS line, thus masking out other spurious activity. Post layout simulation results in TSMC 90 nm process validate the proposed masking system in the 200-533 MHz range, meeting the mask shut-off specification in best, typical, and worst case corners.
2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010
... REFERENCES [I] U. Karthaus, M.Fischer, "Fully integrated passive UHF RFID transp... more ... REFERENCES [I] U. Karthaus, M.Fischer, "Fully integrated passive UHF RFID transponder IC with 16.7-flW minimum RF input power," IEEE J ... 2007 [8] A Shameli, A Safarian, A. Rofougaran, M. Rofougaran, FD Flaviis, "Power Harvester Design for Passive UHF RFID Tag using a ...
2010 IEEE Computer Society Annual Symposium on VLSI, 2010
An innovative design of a 533 MHz DDR2 SDRAM PHY based on a common standard bus interface (DFI) a... more An innovative design of a 533 MHz DDR2 SDRAM PHY based on a common standard bus interface (DFI) and implemented in 90 nm standard CMOS process, is presented in this paper. Off-chip driver with calibrated strength, slew rate control, and on-die termination mechanism are utilized to provide improved signal integrity. Furthermore a DDR3-like I/O architecture and an appropriate calibration mechanism
In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator i... more In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator is designed in TSMC 0.18 mm CMOS technology as a part of a ultra wideband FM (UWBFM) transmitter. The VCO includes a current-controlled oscillator (CCO) which generates output frequencies between 1.5 and 2.8 GHz and a voltage-to-current (V-to-I) converter. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range achieving oscillation frequencies between 3 and 5.6 GHz. Thus, the well-known proportionality between the oscillation frequency and the bias tuning current in CCOs is avoided for the entire achieved tuning range, resulting in a lower power design. The employed architecture provides high suppression, over 45 dB, of the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The current consumption is 5 mA at a supply voltage of 1.8 V. The VCO exhibits a phase noise of À80.56 dBc/Hz at 1 MHz frequency offset from the carrier and a very high ratio of tuning range (60.4%) over power consumption equal to 8.26 dB which is essential for a UWBFM transmitter.
2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)
ABSTRACT A bipolar low noise amplifier (LNA) is described in this work. The IC contains the LNA c... more ABSTRACT A bipolar low noise amplifier (LNA) is described in this work. The IC contains the LNA core, an externally programmed bias network, a voltage divider, an LC tank and inductors to set the input impedance. The externally programmed bias network allows the user to select the bias current in an adaptive manner, depending upon the requirements of the individual system. (Low NF, high gain, low consumption etc). The chip can be powered down by sending an appropriate bit stream to the bias network. The tuned amplifier using a parallel LC network provides selective amplification and lower power consumption. The produced gain is 15 dB while the NF is 2.1 dB for moderate power consumption. The IIP3 is -7 dB and the P1dB is -17 dB. The power consumption from a single 5-V supply is 3.4 mA for the low gain mode and 13 mA for the high gain mode.
2007 IEEE International Symposium on Circuits and Systems, 2007
A subharmonic injection-locked self-oscillating mixer (s-ILSOM) at 1 GHz is reported in this pape... more A subharmonic injection-locked self-oscillating mixer (s-ILSOM) at 1 GHz is reported in this paper. The proposed circuit which combines both injection-locking and mixing functions is described theoretically and experimentally. In contrast to previously reported works, only one input port is required for both the RF/IF signal and the injection signal. Furthermore, the injection signal which is used to stabilize the oscillation is at a subharmonic of the oscillation frequency (fLO/4), with a power level as low as -20 dBm. Phase noise calculations and mixing characteristics are reported, indicating a noise improvement, and a high up-conversion gain for both fundamental and harmonic mixing. The circuit is implemented, using a GaAs FET, exhibiting an up-conversion gain of 13 dB, a phase noise of -93 dBc/Hz at 100 KHz offset, a P1dB of -18 dBm, an IP3 of -5 dBm, and a power consumption of 24 mW.
bands. The measured peak gains are better than 4.55 and 5.24 dBi in 2.4 and 5.2 GHz operation ban... more bands. The measured peak gains are better than 4.55 and 5.24 dBi in 2.4 and 5.2 GHz operation bands, respectively. 4. CONCLUSION A printed T-shaped slot antenna is proposed for the dual-band WLAN operation. By using the T-shaped slot, two resonant modes are excited where one resonant mode is controlled to operate at 2.4-GHz-band and the other is controlled to operate at 5.2-GHzband. Good agreement between the measured and simulated results verifies the design of the proposed antenna. The measured impedance bandwidths are 2.18-2.85 GHz and 4.96-5.5 GHz for VSWR Յ2 and are sufficient for the two bands of WLAN standard. The measured gains are better than 4.55 and 5.24 dBi at 2.4-GHz-and 5.2-GHz-Band, respectively.
In this paper, we introduce a 5-GHz injection-locked phase-locked loop (ILPLL). A new method is p... more In this paper, we introduce a 5-GHz injection-locked phase-locked loop (ILPLL). A new method is presented for accurate analysis of the phase-noise performance of the proposed system. Furthermore, comparison with other phase-noise-estimation techniques demonstrates that our method provides an accurate characterization of any ILPLL topology. The theoretical and calculation results show an improved performance for phase noise, locking range, and power consumption compared to conventional phase-locked loops (PLLs) and injection-locked oscillators (ILOs). Furthermore, we demonstrate the pulling behavior of the injected oscillator and examine the obtained results. To verify the presented analysis, a 5-GHz prototype has been implemented, which achieves Ϫ119-dBc/Hz at 100-KHz frequency offset, producing ϩ4.5 dBm of output power and consuming 9 mA at 3 V.
ABSTRACT A 1V, programmable, accurate, high speed, single-ended charge pump is proposed, suitable... more ABSTRACT A 1V, programmable, accurate, high speed, single-ended charge pump is proposed, suitable for low voltage PLLs. It is designed in TSMC 90-nm digital CMOS process and it consists of four switches in a current steering configuration, a unity gain rail to rail buffer for the charge sharing effect elimination, one more rail to rail amplifier for minimizing the DC current mismatch, a programmable current bias circuitry and two drivers based on the standard cell XOR gates specific configuration for achieving good synchronization between all charge pump input pulses at the PLL lock state. Replica biasing technique is applied to all charge pump switches. Current glitches and charge mismatch are suppressed by employing a mechanism with additional switches at the output. It exhibits a maximum DC current mismatch of 1% and charge mismatch of 6% over a wide output voltage range of 0.7V for the entire range of output currents. The wide range of the output voltage remains relatively constant and independent of the selected charge pump current amplitude. This is attained by applying appropriate variation of the W/L ratios of the bias cascode current sources via the employment of additional programmable switches such that their saturation voltages remain relatively constant, something which in turn enables the output currents range to be as wide as it is required.
This paper presents the analysis and experimental evaluation of a modified dual-loop phase-locked... more This paper presents the analysis and experimental evaluation of a modified dual-loop phase-locked loop synthesizer, using the phase noise transfer functions resulting from the linear model of the synthesizer. The different arrangement in the high-frequency loop, in contrast to previous reported series-connected dual-loop topologies, offers various advantages, such as improved phase noise, finer resolution, and lower spurious levels. Discrete elements are used to implement a prototype system for testing. This adds to the flexibility of the design and allows for experimental optimization of the loop trade-offs. The synthesizer generates signals in the 4850 MHz to 5050 MHz range with a 10 MHz resolution and can match the specifications for wireless LANs operating at 5 GHz. The design resulted in a prototype with very good characteristics suitable for future integration.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2008
This paper presents a multifunctional circuit realizing the functions of oscillation, mixing, amp... more This paper presents a multifunctional circuit realizing the functions of oscillation, mixing, amplification, and frequency multiplication at 5 GHz. A theoretical and experimental description of the circuit is given. The proposed circuit, which combines both the injection-locking and mixing processes, uses only one port where both the RF/intermediate frequency signal and the injection signal (IS) are applied. The IS, which is used to stabilize the oscillation, is at a subharmonic of the oscillation frequency (osc 4) having a power level as low as 50 dBm. Calculations of the phase noise and measurements of the mixing properties are reported which indicate a noise improvement, and a high up-conversion gain. The implementation of the circuit exhibits an up-conversion gain of 14 dB, a phase noise of 110 dBc/Hz at 100-kHz offset, a P 1 dB of 15 dBm, a third-order intercept point of 2 dBm, and a power consumption of 35 mW. Calculated and measured results are in good agreement for all cases, emphasizing the relevance of the proposed circuit.
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Papers by Fotis Plessas