Image Sensor Matrix High Speed Simulation

World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:6, No:11, 2012 Image Sensor Matrix High Speed Simulation Z. Feng, V. Viswanathan, D. Navarro, and I. O’Connor International Science Index, Electronics and Communication Engineering Vol:6, No:11, 2012 waset.org/Publication/6766 Abstract—This paper presents a new high speed simulation methodology to solve the long simulation time problem of CMOS image sensor matrix. Generally, for integrating the pixel matrix in SOC and simulating the system performance, designers try to model the pixel in various modeling languages such as VHDL-AMS, SystemC or Matlab. We introduce a new alternative method based on spice model in cadence design platform to achieve accuracy and reduce simulation time. The simulation results indicate that the pixel output voltage maximum error is at 0.7812% and time consumption reduces from 2.2 days to 13 minutes achieving about 240X speed-up for the 256x256 pixel matrix. solve 130K equations [10]. For solving this big time and calculation consumption problem, we propose a high level simulation in Cadence design platform to simulate the imager on matrix level and check the sensor matrix performance in early stages of design time. We introduce the image sensor pixel models and basic signal processing procedure in the section II. In section III, we will discuss the fast simulation method and present a comparison result. Finally, in section IV we conclude and provide the future perspectives. II. IMAGE SENSOR MODEL AND SIGNAL ANALYSIS Keywords—CMOS image sensor, high speed simulation, image sensor matrix simulation. I. INTRODUCTION A S reviewed by E. R. Fossum and M. Bigas in the papers [1] [2], owing to its linear output response of the incident light intensity, the 3T-APS is the popular and basic pixel architecture in image sensors. A spice model has been reported by T. Reiner [3] studied mainly on the capacitance on the sensitive node and pixel transfer function. A detailed analysis has been given by A.El Gamal [4] on sensor dynamic range, system SNR, and several methods for improving the DR. The APS and PPS pixel has been modeled in VHDLAMS in order to predict the chip behavior before the fabrication [5], but we can find that this model is not able to be as accurate as the spice model and did not take the noise and parasitic capacitor into account. Another APS VHDL model take the sense node nonlinearity into consideration and with the other functional block, but it suffers from internal errors when the imager matrix size becomes too big, the simulation time consumption is also an unavoidable problem [6]. The spice simulator based on numerical analysis, such as Spectre, Hspice, solves the circuit equation by iterative method, such as Newton’s method, Newton-Raphson method. To be specific, for the imager resolution 256x256, the tool has to solve equations with respect to 196608 mosfet transistors and 65536 photodiodes suppose that the pixel is a 3T-APS. For simulating the whole sensor matrix, the simulator has to Z. Feng is with the Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, Ecully, 69134 France, (phone: +33 0472186059; fax: +33 0478433593; e-mail: zhenfu.feng@ ec-lyon.fr). V. Viswanathan is with the Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, Ecully, 69134 France, (phone: +33 0472186059; fax: +33 0478433593; e-mail: Vijay.Viswam@ ec-lyon.fr). D. Navarro is with the Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, Ecully, 69134 France, (phone: +33 0472186398; fax: +33 0478433593; e-mail: David.Navarro@ ec-lyon.fr). I. O’Connor is with the Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, Ecully, 69134 France, (phone: +33 0472186054; fax: +33 0478433593; e-mail: Ian.Oconnor@ ec-lyon.fr). International Scholarly and Scientific Research & Innovation 6(11) 2012 As shown in Fig 1, the 3T-APS consists of three NMOS transistors and a photodiode. Typical signal readout procedure can be roughly divided into three phases, such as reset, integration and readout. During the reset operation, the sense node full well capacitor Cpd which comprise the photodiode inner capacitor, reset transistor MN1 source capacitor, and the MN2 gate parasitic capacitor will be reset to a voltage Vpd. The charges will be accumulated on the sense nodes and it can gain maximum charge Qmax which depends on the full well capacitance of the photodiode. After resetting, the capacitor Cpd will be discharged by the photocurrent (Iph) and dark current (Idark), the former is proportional to the light intensity during the integration time and Idark is the leakage current flowing through the photodiode when no photons enter the image pixel, the main part of the total dark current is coming from the depletion of the photodiode edge at the surface [7]. As shown in Fig 2, the slope of discharge curve is determined by the sum of Iph and Idark and it also determine by the Cpd. The bigger the Iph is, the faster the Cpd discharges. For example, using three different light intensities as input to the simulation produces three different Iph giving three discharge curves with different slopes, as shown in Fig 2. Meanwhile, the discharge voltage is buffered by inner source follower MN2. The access transistor MN3 passes this voltage to column bus according to the readout timing. The column voltage will be sampled twice by the Correlated Double Sampling (CDS) circuit, which is used to reduce reset noise and fixed pattern noise [8]. The first sample happens in the reset period and the second sample happens during integration. The final output voltage can be expressed by equation (1): VOS = VCDS − H − VCDS − S (1) where, VCDS_H is the output voltage in reset phase and VCDS_S is the output voltage sampled during the integration. The differential voltage Vos is the final signal passed to Analog to Digital converter (ADC) for generating the image numeric data. 1244 scholar.waset.org/1307-6892/6766 World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:6, No:11, 2012 VDD Vreset MN1 Vpd MN2 Iph00 Iph01 Iph02 Iph03 Iph0j V00 V01 V02 V03 V0j Iph10 Iph11 Iph12 Iph13 Iph1j V10 V11 V12 V13 V1j Iph20 Iph21 Iph22 Iph23 Iph2j V20 V21 V22 V23 V2j Iph30 Iph31 Iph32 Iph33 Iph3j V30 V31 V32 V33 V3j Iphi0 Iphi1 Iphi2 Iphi3 Iphij Vi0 Vi1 Vi2 Vi3 Vij Photodiode MN3 Light Vpixel Cpd Vselect APS Vbias I (i, j) Fig. 3 Mapping and generated database (m2 vm2) Pixel Output voltage (V) Fig. 1 3T-APS pixel model Pixel output voltage (Volts) International Science Index, Electronics and Communication Engineering Vol:6, No:11, 2012 waset.org/Publication/6766 APS V (i, j) Difference output Vos (m1 vm1) va vb vc (a+b)/2 Time Integration time Reset pulse … Fig. 2 Timing diagram of 3T-APS [3] c b a … Photocurrent (pA) Fig. 4 Pixel output voltage versus photocurrent III. HIGH SPEED SIMULATION METHOD AND IMPLEMENTATION The spice simulator is commonly used to simulate the circuit behavior. Imager matrix is built up from pixel blocks that are repeated thousands or millions of times. The number of the circuit element in such a matrix is too huge for the common spice simulator. The reason why the Spectre simulator suffers from memory and runtime problem for huge pixel matrix is that the nets and terminals in the matrix form a very complicated equation with lots of variables according to Kirchhoff’s Current Law (KCL) and Kirchhoff’s Voltage Law (KVL) principle. It costs lot of time to solve the equations and it consumes lot of memory to execute the calculation. Currently designers simulate pixel matrix in a very limited size, such as 10x10 or 20x20 before the fabrication owing to these difficulties. In order to give high level performance estimation, we present our high level and high speed approach. The main idea in this work is to use one pixel instead of the whole matrix in the simulation with the help of the generated database to map the input photocurrent and output voltage. We use 3T-APS as a standard cell as shown in the Fig 3, in order to obtain an correlated output voltage database V[i][j] we perform a parametric simulation with the photocurrent parameter Iph[i][j] which is the input signal of the pixel with address row i and column j in the pixel matrix. In this way, we convert the photocurrent values to its correlated output voltage database and we form a Look Up Table (LUT) by these data shown as the blocks marked Iph[i][j] and V[i][j] in Fig 3. International Scholarly and Scientific Research & Innovation 6(11) 2012 An 8 bit depth grey level image with intensity data ranging from 0 to 255 is used to represent the output voltages. So we need 256 different output voltage stages from the lowest to the highest corresponding to numeric intensity data from 0 to 255 and these voltage stages all relate to a specific photocurrent. The pixel simulation output voltage increasing linearly with the light intensity is shown in Fig 4. The output voltage curve implies that some pixel output voltage can be estimated before the simulation. Since we need 256 different output voltage stages, we divide the input photocurrents into 256 blocks and in turns we get a series of mean photocurrent of each block. We create an input table of these 256 mean values and we apply these 256 values in the simulation. Another table of 256 output voltages is generated after the simulation as shown in table I. And then, a mapping function is used to match and set each pixel in the pixel matrix output voltage directly. TABLE I THE PHOTOCURRENT AND OUTPUT VOLTAGE Photocurrent (A) Output voltage (Volts) a: [Iph_00] Va:V00 b: [Iph_01] Vb:V01 c: [Iph_02] Vc:V02 … … x y We assume that the photocurrent is a random unknown value as x and there is a threshold photocurrent in each range such as (a+b)/2 in region [a b]. As shown in Fig 4, since the 1245 scholar.waset.org/1307-6892/6766 International Science Index, Electronics and Communication Engineering Vol:6, No:11, 2012 waset.org/Publication/6766 World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:6, No:11, 2012 pooint m1 has a bigger photocurrent valuue than the thhreshold (aa+b)/2, so the correlated ouutput CDS volltage Vm1 is clloser to Va than Vb acccording to thhe circuit behhavior presennted by daashed line wh hich stands ffor the outpuut voltage inccreasing linnearly along with the phootocurrent. Every E output voltage coorresponds to an intensity data d value in the t grey level image, foor example, Va is converted to 165 in thhe numeric inntensity daata in the imag ge and Vb to 1164. Owing too the Vm1 is cllosed to Va and there is no available iinteger value between b 164 and a 165 inn the image. So the voltage Vm1 could bee evaluated to Va and V Vm2 could be Vb if the simuulation resultss is shown as an grey level image. So S in this way w as show wn in Fig 3,, every phhotocurrent I((i j) value in the scene willl be matchedd in the geenerated databbase and everry correlated output o voltagee V(i j) w be estimateed. will We have impplemented this LUT functioon in our ownn image seensor matrix simulation s toool box shownn in Fig 5. Thhis tool caan help to invvestigate how the pixel perrformance affeects the ouutput image quality q [9]. Tw wo levels sim mulation are avvailable foor checking thhe pixel perfoormance, userr can investig gate the sinngle pixel chharacter by performing thee normal sim mulation annd he can alsoo perform the matrix level simulation s whhich can bee used to innvestigate thhe high level performancce. For exxample, userr can invesstigate the affection off pixel temperature changes on the final output image i intensitty data. h been taken into Fuurther more, the column capacitance has acccount in the big matrix ssimulation. With W the help of this hiigh speed appproach, 130K equations neeeded to be sollved by sppice simulatorr for simulatinng the pixel matrix m 256x2556 have beeen reduced too 4.8K in our nnew approach h and simulation time haas been greatly saved. The time performance is shownn in Fig 6. The time consumption c of Spectre classical sim mulation nentially withh matrix row numbers, whhereas it inncreases expon inncreases slowly after the iniitialization whhich takes 12 minutes m too form the LUT T database in the new fast simulation s meethod. Fig. 6 Time consum mption versus piixel numbers Table II is ussed to show thhe time consuumption compparison. Foor the matrix in small sizze, such as 4xx4, 8x8 and 12x12 pixxels, the classsical simulatioon time consum mption is 7 minutes, m buut the simulatiion time is 8 hours h when th he matrix sizee reach 1000x100. In contrast, c the initialization time for thhe fast sim mulation is aroound 12 minuutes and the mapping m functiion can be finished verry quickly, soo this fast sim mulation metthod is m size is bigger quuite useful for the simulatioon when the matrix thaan 12x12. The mapping fuunction consum mes about 1 second to map the wholle matrix outpput of size 102 24x768. TA ABLE II TIME CONSUM MPTION COMPARIS SON Matrix size 8 12 60 x8 x12 x600 Classical (min) 3.7 7.5 179.2 23 11.57 12.01 12.2 21 Initialization(minn) Mapping(ms) 34.6 39.5 5 23.6 256 x256 3465 12.3 91.4 512 x512 error 12.31 483 As it is a higgh level estim mation methood, validation of the ressults with a reference simulation is i performedd. The vaalidation is baased on AMS 0.35um techn nology and 3T-APS med by moodel with thee fixed integration time. It is perform sim mulating 256 6x256 classiccal simulatioons. The following im mage generatioon method [99] is used to convert the output vooltage into grayy level images. Vos Vmax − Vmin V grey g _ raw = 255 × os VCC V g _ abs = 255 × os grey Vrst greyy _ relative = 255 × Fig. 5 Imagger matrix simuulation toolbox in Cadence AD DE International Scholarly and Scientific Research & Innovation 6(11) 2012 (2) (3) (4) whhere, the Vos is i the CDS ouutput voltage, Vmax and Vminn is the maaximum and minimum m valuue of the pixeel matrix Vos values, v resspectively. Thhe results of classical Speectre simulatio on and thee new approacch are shown iin Fig 7. 1246 scholar.waset.org/1307-6892/6766 World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:6, No:11, 2012 The Table IV V shows the w worst case of th he simulation results an nd correlated intensity i data. Vreset is the output o voltagee at the resset stage whiich is equal to VCDS-H. Vsample is the output vooltage after integration i w which is equ ual to VCDS-SS. The maaximum errorr of intensity data is 2 and d it comes fro om the absolute imagee generation method show wn in equatio on (4), usiing this equaation does nott correct the error in Vreseet. It is about 0.78% (2//256) of data rrange 256 in grey g level. Thee mean whole matrix simulation average a vaalue which staands for the w i about 0.168 81% of errror in intensitty data is quitte small and is thee output data range. r International Science Index, Electronics and Communication Engineering Vol:6, No:11, 2012 waset.org/Publication/6766 IV V. CONCLUSIO ON AND DISCU USSION Fig. 7 Top-leeft is the originaal input picture, Top-right is thhe grey fiile, bottom-left is the classical simulation resuult, and bottom--right is the fast siimulation resultt The originall input and output o picture have a ressolution 25 56x256 and a wider dynaamic range in n output imag ges has beeen achieved owing o to the relative r imagee generation method. m Th he histogram comparison iss shown in Taable III. TA ABLE III IMAGE HISTO OGRAM COMPARIS SON original grey classical fast mean std dian med 125.7 89.4 139.7 139.6 60.5 45.5 79.4 79.8 13 38 9 92 15 53 15 54 t the mean n value in classical c The comparrison shows that sim mulation resu ults is 139.7 and standarrd variation is i 79.4, m median value iss 153, whereaas the value is 139.6, 79.8 an nd 154, reespectively in the fast simuulation resultts. It proves that t the faast simulation results matchh the classical results. We compare eaach output vo oltage with the t fast simu ulation and find fi the m maximum erro or is about 33.647506 uV. With the help h of eq quation (5), (6 6) and (7), a ppoint to point pixel p output numeric n daata compariso on has been uused to measu ure the data in ntensity errror. errabs = p fasst − pclassical (5) errraabs × 100% 2556 (6) errrel = m n i j ∑∑ ∑ err abs e mean = err m×n × 1 × 100% 2 256 (7) where, errabs, errrrel and errmeean represent the w t absolute, relative an nd mean pixell intensity dataa error, respecctively. This paper presents p an aalternative waay of image sensor maatrix simulatio on. This method is technolo ogy independeent and thee accurate spiice model couuld be used to o simulate the image sen nsor matrix in nstead of usinng a high lev vel language model, succh as VHDL-AMS model. The result has h proved sttrongly thaat our new fast simulatiion approach h can be used for acccelerating thee CMOS imagge sensor pixeel matrix simu ulation. Duue to the timee consumptioon has been reduced r largelly, this maakes the CMO OS image sensor simulation n more efficieent and in turn it is posssible to check the system peerformance in n a very ort time. Thiss new improvement makes realizing the whole sho im mage generation and proccessing image data possiible in Caadence. More cases should be simulated to verify and d prove thiis high level and a high speedd simulation approach. a Thee future woork will be focused f on tthe aspects such s as: variaability, tecchnologies an nd pixel archiitectures. Thee pixel matrix x FPN wiill be investigaated and analyyzed. REFEERENCES [1] E. R. Fossum m, “CMOS Imagee Sensor: Electro onic Camera-on-A A-chip”, IEEE Transacttions On Electronnic Devices, vol. 44, N.10, 1997. [2] M.Bigas, “Review of CMOS image sensors” Microelectronicss journal 37(2006) 433--451. [3] T. Reiner, “C CMOS Image Seensor 3T Nwell Photodiode Pixel Spice Model” 23rd IEEE Conventionn of Electrical an nd Electronics Engineers E 61-164, 6-7 Sept.. 2004. in Israel. pp 16 [4] A. El Gamaal, “High dynam mic range imag ge sensors,” Tuttorial at International Solid-State S Circuiits Conference, February F 2002. [5] F. Dadouche, A. Pinna, P. G Garda, A. Alexan ndre. Modeling of Pixel I Systems with VHDL-AM MS. Proc. IEEE E DTIS, Sensors for Image Tunisia, Septeember 5-7, 2006. ppp. 289-293. [6] D. Navarro, D. D Ramat, F. Mieyyeville, I. O'Conn nor, F. Gaffiot, L. L Carrel, "VHDL & VH HDL-AMS modeeling and simulaation of a CMOS S imager IP", Forum on specificatioon & Design Languages, Lausanne, S 2005. Switzerland, September [7] N. V. Loukiaanova, “Leakage current modelin ng of test structtures for characterizatio on of dark currennt in CMOS imag ge sensors,” IEEE E Trans. Electron Dev.,, vol. 50, no. 1, ppp. 77 - 83, 2003 [8] M. White, D. Lampe, F. Blaha, and I. Mack, “Characterizzation of nel CCD image aarrays at low ligh ht levels” IEEE J. J Solidsurface chann State Circuits, vol. SC-9, pp. 1––13, Sept. 1974. [9] D. Navarro, Z. Z Feng, V. Visw wanathan, L. Carrrel, I. O’Connor,, “Image toolbox for CMOS C image ssensors simulatio ons in Cadencee ADE”, DeMset2011 conference, c Orlanndo, Florida, USA A, Dec 2011. [10 0] Cadence User Guide TA ABLE IV SIMULATION RESULT TS COMPARISON AND A ERROR Simulation Classical Fast Vreset 1.327557 1.327467 Vsample 0.4471916 0 0 0.440786 Raw R 6 68 6 68 Rel 161 161 Abs 169 171 International Scholarly and Scientific Research & Innovation 6(11) 2012 1247 scholar.waset.org/1307-6892/6766