This paper presents a new high speed simulation methodology to solve the long simulation time pro... more This paper presents a new high speed simulation methodology to solve the long simulation time problem of CMOS image sensor matrix. Generally, for integrating the pixel matrix in SOC and simulating the system performance, designers try to model the pixel in various modeling languages such as VHDL-AMS, SystemC or Matlab. We introduce a new alternative method based on spice model in cadence design platform to achieve accuracy and reduce simulation time. The simulation results indicate that the pixel output voltage maximum error is at 0.7812% and time consumption reduces from 2.2 days to 13 minutes achieving about 240X speed-up for the 256x256 pixel matrix.
2007 Design, Automation & Test in Europe Conference & Exhibition, 2007
This paper discusses several forms of heterogeneity in systems on chip and systems in package. A ... more This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimation of the maturity of design and modeling techniques with respect to various physical domains. Industry-level MEMS integration, and more prospective microfluidic biochip systems are considered at both technological and EDA levels. Finally, specific flows for signal abstraction heterogeneity in RF SiP and for functional co-verification are discussed.
Emerging Wireless Body Area Networks (WBANs) are receiving increasing interest from researchers a... more Emerging Wireless Body Area Networks (WBANs) are receiving increasing interest from researchers and designers. Specific requirements for small-scale dimensions, low-latency, lightweight and limited power capacity mean that the key challenge in WBANs design is in the adoption of energy-efficient strategies for better system performance, and in the efficient use of high data-rate and ultra-low-power transceivers. This paper presents a high-level energy-aware SystemC-based model and simulation of Nordic's Enhanced ShockBurst (ESB) and ShockBurst (SB) baseband protocol engine. The model includes data from Energy consumption experiments using nRF24L01+ transceiver, enabling detailed exploration of energy conversation strategies. With this model, we show that a high data-rate ESB and SB transmission at 2Mbps can save more than 60% and 80% energy respectively, and it has 3x higher lifetime expectancy than the 250Kbps low data-rate communication with a payload collecting strategy.
11th International Conference on Group IV Photonics (GFP), 2014
This work demonstrates the use of commercial EDA toolsets for the measurement and validation of t... more This work demonstrates the use of commercial EDA toolsets for the measurement and validation of the layout of waveguide interconnects and the integration into a dedicated silicon photonics physical design flow.
Electronic Communication of The European Association of Software Science and Technology, 2009
In the Model-Based Engineering (MBE) paradigm, models are the core elements in the design process... more In the Model-Based Engineering (MBE) paradigm, models are the core elements in the design process of a system from its requirements to the actual implementation of the system. By means of Supervisory Control Theory (SCT), supervisory controllers (supervi- sors) can be synthesized instead of designing them manually. In this paper, a framework based on the Compositional Interchange Format for hybrid systems (CIF) has been developed that integrates the MBE and the SCT paradigms. To illustrate the framework, an industrial-size case study has been performed: synthesis of a supervisory controller for the patient support system of an MRI scanner. In this case study, we address 1) modelling of the components and the control requirements; 2) synthesis of the supervisor; 3) simulation of the synthesized supervisor and a hybrid model of the plant; and 4) real-time, simulation based control of the supervisor and the actual patient support system of the MRI scanner. Complex manufacturing machine...
The paper addresses some of the opportunities and challenges related to test and reliability of t... more The paper addresses some of the opportunities and challenges related to test and reliability of three major emerging computing paradigms; i.e., Quantum Computing, Computing engines based on Deep Neural Networks for AI, and Approximate Computing (AxC). We present a quantum accelerator showing that it can be done even without the presence of very good qubits. Then, we present Dependability for Arti)cial Intelligence (AI) oriented Hardware. Indeed, AI applications shown relevant resilience properties to faults, meaning that the testing strongly depends on the application behavior rather than on the hardware structure. We will cover AI hardware design issues due to manufacturing defects, aging faults, and soft errors. Finally, We present the use of AxC to reduce the cost of hardening a digital circuit without impacting its reliability. In other words how to go beyond usual modular redundancy scheme.
With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile... more With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.
The authors state briefly the possibility of various simulators to handle propagation of electrom... more The authors state briefly the possibility of various simulators to handle propagation of electromagnetic waves along some interconnections, in 3D RF (Radio Frequency) circuits. The studies are first derived in the time domain: a Finite-Difference Time-Domain method is applied, taking spectra via FFTs (Fast Fourier Transform) as post-processors. Electric and magnetic field distributions, pulse propagations along stripline structures or vias are highlighted. The scattering parameters for various cases are extracted and compared. Some original issue of this work is an insight on crosstalk or shielding phenomena between lines.
Proceedings Design, Automation and Test in Europe Conference and Exhibition
For extremely Low-power Logic, three very new and promising techniques will be described. The fir... more For extremely Low-power Logic, three very new and promising techniques will be described. The first are methods on circuit and system level for reduced supply voltages. In large logic blocks, interconnect becomes a main issue, that could be solved by onchip optical interconnect. Nano-devices will also be presented, as a possibility to compute with nearly zero power, and compared to future 10 nanometers transistors.
The 20th Asia and South Pacific Design Automation Conference, 2015
The many cores design research community have shown high interest in optical crossbars on chip fo... more The many cores design research community have shown high interest in optical crossbars on chip for more than a decade. Key properties of optical crossbars, namely a) contention-free data routing b) low-latency communication and c) potential for high bandwidth through the use of WDM, motivate several implementations. These implementations demonstrate very different scalability and power efficiency ability depending on three key design factors: a) the network topology, b) the considered layout and c) the insertion losses induced by the fabrication process. The emerging design technique relying on multi-layer deposited silicon allows reducing optical losses, which may lead to significant reduction of the power consumption. In this paper, multi-layer deposited silicon based crossbars are proposed and compared. The results indicate that the proposed ring-based network exhibits, on average, 22% and 51.4% improvement for worst-case and average losses respectively compared to the most power-efficient related crossbars.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
This work is motivated by the demand of an electronic design automation (EDA) approach for the em... more This work is motivated by the demand of an electronic design automation (EDA) approach for the emerging ecosystem of the photonic integrated circuit (PIC) technology. A reliable physical verification flow cannot be achieved without the adaption of the traditional EDA tools to the photonic design verification needs. We analyze how layout versus schematic (LVS) checking is performed differently for photonic designs, and propose an LVS flow that addresses the particular need of curvilinear feature validation (curved path length and bend curvature extraction). We show that it is possible to reuse and extend the current LVS tools to perform such critical but nontraditional checks, which ensures a more reliable photonic layout implementation in term of functionality and circuit yield. Going forward, we propose possible future studies that can further improve the flows.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
In this paper we propose a methodology to simulate the optical filtering system of a camera modul... more In this paper we propose a methodology to simulate the optical filtering system of a camera module with limited access to proprietary data. The target of the simulation is the virtual prototyping of the overall camera module for a fine tuning of the auto-focus mechanism. For the optical system modeling, the methodology is based on the usage of some point spread functions (PSFs). The use of the full set of PSFs is computationally costly and memory space consuming hence compromising the usability of the optical model in the full system virtual prototyping. To improve the model execution time, PSFs interpolation and free-space propagation techniques are used: they allow reducing the sampling space with minimal impact on the accuracy of the model (sharpness error less than 2%). The total speed-up gain with respect to the standard non-optimized model is provided by two contributors. First, the interpolation technique leads to a speed-up linked to the PSFs number reduction. Second, the caching of computationally intense processes enables speed-up scaling with the number of frames.
Proceedings Design, Automation and Test in Europe Conference and Exhibition
In this paper, we present a tool to analyse photonic devices that can be used to realize basic bu... more In this paper, we present a tool to analyse photonic devices that can be used to realize basic building blocks of an optical network-on-chip (ONoC). Co-design between electrical tools and optical tools is possible. The VHDL-AMS language has been used to implement behavioral models of photonic devices. For low-level simulation, a gateway between an optical simulator, based on the finite elements method, and a typical EDA layout editor has been realized.
EURASIP Journal on Wireless Communications and Networking, 2011
This article presents IDEA1, a SystemC-based system-level design and simulation framework for WSN... more This article presents IDEA1, a SystemC-based system-level design and simulation framework for WSNs. It allows the performance evaluation (e.g., packet delivery rate, transmission latency and energy consumption) at high level, but with elaborate models of the hardware and software of sensor nodes. Many hardware components are modeled and the IEEE 802.15.4 standard is implemented. IDEA1 uses a clock-based synchronization mechanism to support simulations with cycle accurate communication and approximate time computation. The simulation results have been validated by a testbed of 9 nodes. The average deviation between the IDEA1 simulations and experimental measurements is 4.6%. The performances of IDEA1 have also been compared with NS-2. To provide a similar result (deviation less than 5%) at the same abstraction level, the simulation of IDEA1 is 2 times faster than NS-2. Moreover, with the hardware and software co-simulation feature, IDEA1 provides more detailed modeling of sensor nodes. Finally, IDEA1 is used to study a real-time industrial application in which a wireless sensor and actuator network is deployed on a vehicle to measure and control vibrations. By the simulation, some preliminary designs based on IEEE 802.15.4 protocols and two different hardware platforms are evaluated.
2011 IEEE Eighth International Conference on Mobile Ad-Hoc and Sensor Systems, 2011
This paper presents IDEA1, a validated SystemC-based simulator for WSNs. It allows the systemleve... more This paper presents IDEA1, a validated SystemC-based simulator for WSNs. It allows the systemlevel performance evaluation (e.g., packet transmission and energy consumption) with elaborate models of sensor nodes. IDEA1 uses a clock-based synchronization mechanism to support simulations with cycle accurate communication and approximate time computation. Its accuracy has been validated by a testbed of 9 nodes. The average deviation between the IDEA1 simulations and experimental measurements is 5.9%. The performances of IDEA1 have also been compared with NS-2, one of the most widely used simulators in WSN research. To provide a similar result (deviation less than 5%) at the same abstraction level, the simulation of IDEA1 is 2 times faster than NS-2. Moreover, with the hardware and software cosimulation feature, IDEA1 provides more detailed modeling of sensor nodes than NS-2.
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop, 2012
ABSTRACT Optical network on chip (ONoC) architectures are emerging as potential contenders to sol... more ABSTRACT Optical network on chip (ONoC) architectures are emerging as potential contenders to solve congestion and latency issues in future computing architectures. This paper describes WADIMOS, an EU funded research project aiming to demonstrate a complex photonic interconnect layer on CMOS. This incorporated multichannel microsources, microdetectors and various advanced wavelength routing functions directly integrated with electronic driver circuits. Design methods and system-level models compatible with an industrial NoC exploration environment were developed to enable exploration of application scenarios for such electro-photonic ICs, in an on-chip optical network context.
In this paper we present the design and implementation of a generic GA-based optimization framewo... more In this paper we present the design and implementation of a generic GA-based optimization framework iMASKO (iNL@MATLAB Genetic Algorithm-based Sensor NetworK Optimizer) to optimize the performance metrics of wireless sensor networks. Due to the global search property of genetic algorithms, the framework is able to automatically and quickly fine tune hundreds of possible solutions for the given task to find the best suitable tradeoff. We test and evaluate the framework by using it to explore a SystemC-based simulation process to tune the configuration of the unslotted CSMA/CA algorithm of IEEE 802.15.4, aiming to discover the most available tradeoff solutions for the required performance metrics. In particular, in the test cases different sensor node platforms are under investigation. A weighted sum based cost function is used to measure the optimization effectiveness and capability of the framework. In the meantime, another experiment is performed to test the framework's optimization characteristic in multi-scenario and multi-objectives conditions.
4th International IEEE North-East Workshop on Circuits and Systems, NEWCAS 2006 - Conference Proceedings, 2006
It is believed that the concept of integrated optical interconnect is a potential technological s... more It is believed that the concept of integrated optical interconnect is a potential technological solution to alleviate some of the ever more pressing issues involved in exchanging data between cores in SoC architectures (inter-line crosstalk, latency, global throughput, connectivity and power consumption). This abstract summarises work carried out in the framework of the EU-funded PICMOS project on the quantitative comparison of optical interconnect to electrical interconnect in the context of on-chip data communication.
This paper presents a new high speed simulation methodology to solve the long simulation time pro... more This paper presents a new high speed simulation methodology to solve the long simulation time problem of CMOS image sensor matrix. Generally, for integrating the pixel matrix in SOC and simulating the system performance, designers try to model the pixel in various modeling languages such as VHDL-AMS, SystemC or Matlab. We introduce a new alternative method based on spice model in cadence design platform to achieve accuracy and reduce simulation time. The simulation results indicate that the pixel output voltage maximum error is at 0.7812% and time consumption reduces from 2.2 days to 13 minutes achieving about 240X speed-up for the 256x256 pixel matrix.
2007 Design, Automation & Test in Europe Conference & Exhibition, 2007
This paper discusses several forms of heterogeneity in systems on chip and systems in package. A ... more This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimation of the maturity of design and modeling techniques with respect to various physical domains. Industry-level MEMS integration, and more prospective microfluidic biochip systems are considered at both technological and EDA levels. Finally, specific flows for signal abstraction heterogeneity in RF SiP and for functional co-verification are discussed.
Emerging Wireless Body Area Networks (WBANs) are receiving increasing interest from researchers a... more Emerging Wireless Body Area Networks (WBANs) are receiving increasing interest from researchers and designers. Specific requirements for small-scale dimensions, low-latency, lightweight and limited power capacity mean that the key challenge in WBANs design is in the adoption of energy-efficient strategies for better system performance, and in the efficient use of high data-rate and ultra-low-power transceivers. This paper presents a high-level energy-aware SystemC-based model and simulation of Nordic's Enhanced ShockBurst (ESB) and ShockBurst (SB) baseband protocol engine. The model includes data from Energy consumption experiments using nRF24L01+ transceiver, enabling detailed exploration of energy conversation strategies. With this model, we show that a high data-rate ESB and SB transmission at 2Mbps can save more than 60% and 80% energy respectively, and it has 3x higher lifetime expectancy than the 250Kbps low data-rate communication with a payload collecting strategy.
11th International Conference on Group IV Photonics (GFP), 2014
This work demonstrates the use of commercial EDA toolsets for the measurement and validation of t... more This work demonstrates the use of commercial EDA toolsets for the measurement and validation of the layout of waveguide interconnects and the integration into a dedicated silicon photonics physical design flow.
Electronic Communication of The European Association of Software Science and Technology, 2009
In the Model-Based Engineering (MBE) paradigm, models are the core elements in the design process... more In the Model-Based Engineering (MBE) paradigm, models are the core elements in the design process of a system from its requirements to the actual implementation of the system. By means of Supervisory Control Theory (SCT), supervisory controllers (supervi- sors) can be synthesized instead of designing them manually. In this paper, a framework based on the Compositional Interchange Format for hybrid systems (CIF) has been developed that integrates the MBE and the SCT paradigms. To illustrate the framework, an industrial-size case study has been performed: synthesis of a supervisory controller for the patient support system of an MRI scanner. In this case study, we address 1) modelling of the components and the control requirements; 2) synthesis of the supervisor; 3) simulation of the synthesized supervisor and a hybrid model of the plant; and 4) real-time, simulation based control of the supervisor and the actual patient support system of the MRI scanner. Complex manufacturing machine...
The paper addresses some of the opportunities and challenges related to test and reliability of t... more The paper addresses some of the opportunities and challenges related to test and reliability of three major emerging computing paradigms; i.e., Quantum Computing, Computing engines based on Deep Neural Networks for AI, and Approximate Computing (AxC). We present a quantum accelerator showing that it can be done even without the presence of very good qubits. Then, we present Dependability for Arti)cial Intelligence (AI) oriented Hardware. Indeed, AI applications shown relevant resilience properties to faults, meaning that the testing strongly depends on the application behavior rather than on the hardware structure. We will cover AI hardware design issues due to manufacturing defects, aging faults, and soft errors. Finally, We present the use of AxC to reduce the cost of hardening a digital circuit without impacting its reliability. In other words how to go beyond usual modular redundancy scheme.
With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile... more With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.
The authors state briefly the possibility of various simulators to handle propagation of electrom... more The authors state briefly the possibility of various simulators to handle propagation of electromagnetic waves along some interconnections, in 3D RF (Radio Frequency) circuits. The studies are first derived in the time domain: a Finite-Difference Time-Domain method is applied, taking spectra via FFTs (Fast Fourier Transform) as post-processors. Electric and magnetic field distributions, pulse propagations along stripline structures or vias are highlighted. The scattering parameters for various cases are extracted and compared. Some original issue of this work is an insight on crosstalk or shielding phenomena between lines.
Proceedings Design, Automation and Test in Europe Conference and Exhibition
For extremely Low-power Logic, three very new and promising techniques will be described. The fir... more For extremely Low-power Logic, three very new and promising techniques will be described. The first are methods on circuit and system level for reduced supply voltages. In large logic blocks, interconnect becomes a main issue, that could be solved by onchip optical interconnect. Nano-devices will also be presented, as a possibility to compute with nearly zero power, and compared to future 10 nanometers transistors.
The 20th Asia and South Pacific Design Automation Conference, 2015
The many cores design research community have shown high interest in optical crossbars on chip fo... more The many cores design research community have shown high interest in optical crossbars on chip for more than a decade. Key properties of optical crossbars, namely a) contention-free data routing b) low-latency communication and c) potential for high bandwidth through the use of WDM, motivate several implementations. These implementations demonstrate very different scalability and power efficiency ability depending on three key design factors: a) the network topology, b) the considered layout and c) the insertion losses induced by the fabrication process. The emerging design technique relying on multi-layer deposited silicon allows reducing optical losses, which may lead to significant reduction of the power consumption. In this paper, multi-layer deposited silicon based crossbars are proposed and compared. The results indicate that the proposed ring-based network exhibits, on average, 22% and 51.4% improvement for worst-case and average losses respectively compared to the most power-efficient related crossbars.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
This work is motivated by the demand of an electronic design automation (EDA) approach for the em... more This work is motivated by the demand of an electronic design automation (EDA) approach for the emerging ecosystem of the photonic integrated circuit (PIC) technology. A reliable physical verification flow cannot be achieved without the adaption of the traditional EDA tools to the photonic design verification needs. We analyze how layout versus schematic (LVS) checking is performed differently for photonic designs, and propose an LVS flow that addresses the particular need of curvilinear feature validation (curved path length and bend curvature extraction). We show that it is possible to reuse and extend the current LVS tools to perform such critical but nontraditional checks, which ensures a more reliable photonic layout implementation in term of functionality and circuit yield. Going forward, we propose possible future studies that can further improve the flows.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
In this paper we propose a methodology to simulate the optical filtering system of a camera modul... more In this paper we propose a methodology to simulate the optical filtering system of a camera module with limited access to proprietary data. The target of the simulation is the virtual prototyping of the overall camera module for a fine tuning of the auto-focus mechanism. For the optical system modeling, the methodology is based on the usage of some point spread functions (PSFs). The use of the full set of PSFs is computationally costly and memory space consuming hence compromising the usability of the optical model in the full system virtual prototyping. To improve the model execution time, PSFs interpolation and free-space propagation techniques are used: they allow reducing the sampling space with minimal impact on the accuracy of the model (sharpness error less than 2%). The total speed-up gain with respect to the standard non-optimized model is provided by two contributors. First, the interpolation technique leads to a speed-up linked to the PSFs number reduction. Second, the caching of computationally intense processes enables speed-up scaling with the number of frames.
Proceedings Design, Automation and Test in Europe Conference and Exhibition
In this paper, we present a tool to analyse photonic devices that can be used to realize basic bu... more In this paper, we present a tool to analyse photonic devices that can be used to realize basic building blocks of an optical network-on-chip (ONoC). Co-design between electrical tools and optical tools is possible. The VHDL-AMS language has been used to implement behavioral models of photonic devices. For low-level simulation, a gateway between an optical simulator, based on the finite elements method, and a typical EDA layout editor has been realized.
EURASIP Journal on Wireless Communications and Networking, 2011
This article presents IDEA1, a SystemC-based system-level design and simulation framework for WSN... more This article presents IDEA1, a SystemC-based system-level design and simulation framework for WSNs. It allows the performance evaluation (e.g., packet delivery rate, transmission latency and energy consumption) at high level, but with elaborate models of the hardware and software of sensor nodes. Many hardware components are modeled and the IEEE 802.15.4 standard is implemented. IDEA1 uses a clock-based synchronization mechanism to support simulations with cycle accurate communication and approximate time computation. The simulation results have been validated by a testbed of 9 nodes. The average deviation between the IDEA1 simulations and experimental measurements is 4.6%. The performances of IDEA1 have also been compared with NS-2. To provide a similar result (deviation less than 5%) at the same abstraction level, the simulation of IDEA1 is 2 times faster than NS-2. Moreover, with the hardware and software co-simulation feature, IDEA1 provides more detailed modeling of sensor nodes. Finally, IDEA1 is used to study a real-time industrial application in which a wireless sensor and actuator network is deployed on a vehicle to measure and control vibrations. By the simulation, some preliminary designs based on IEEE 802.15.4 protocols and two different hardware platforms are evaluated.
2011 IEEE Eighth International Conference on Mobile Ad-Hoc and Sensor Systems, 2011
This paper presents IDEA1, a validated SystemC-based simulator for WSNs. It allows the systemleve... more This paper presents IDEA1, a validated SystemC-based simulator for WSNs. It allows the systemlevel performance evaluation (e.g., packet transmission and energy consumption) with elaborate models of sensor nodes. IDEA1 uses a clock-based synchronization mechanism to support simulations with cycle accurate communication and approximate time computation. Its accuracy has been validated by a testbed of 9 nodes. The average deviation between the IDEA1 simulations and experimental measurements is 5.9%. The performances of IDEA1 have also been compared with NS-2, one of the most widely used simulators in WSN research. To provide a similar result (deviation less than 5%) at the same abstraction level, the simulation of IDEA1 is 2 times faster than NS-2. Moreover, with the hardware and software cosimulation feature, IDEA1 provides more detailed modeling of sensor nodes than NS-2.
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop, 2012
ABSTRACT Optical network on chip (ONoC) architectures are emerging as potential contenders to sol... more ABSTRACT Optical network on chip (ONoC) architectures are emerging as potential contenders to solve congestion and latency issues in future computing architectures. This paper describes WADIMOS, an EU funded research project aiming to demonstrate a complex photonic interconnect layer on CMOS. This incorporated multichannel microsources, microdetectors and various advanced wavelength routing functions directly integrated with electronic driver circuits. Design methods and system-level models compatible with an industrial NoC exploration environment were developed to enable exploration of application scenarios for such electro-photonic ICs, in an on-chip optical network context.
In this paper we present the design and implementation of a generic GA-based optimization framewo... more In this paper we present the design and implementation of a generic GA-based optimization framework iMASKO (iNL@MATLAB Genetic Algorithm-based Sensor NetworK Optimizer) to optimize the performance metrics of wireless sensor networks. Due to the global search property of genetic algorithms, the framework is able to automatically and quickly fine tune hundreds of possible solutions for the given task to find the best suitable tradeoff. We test and evaluate the framework by using it to explore a SystemC-based simulation process to tune the configuration of the unslotted CSMA/CA algorithm of IEEE 802.15.4, aiming to discover the most available tradeoff solutions for the required performance metrics. In particular, in the test cases different sensor node platforms are under investigation. A weighted sum based cost function is used to measure the optimization effectiveness and capability of the framework. In the meantime, another experiment is performed to test the framework's optimization characteristic in multi-scenario and multi-objectives conditions.
4th International IEEE North-East Workshop on Circuits and Systems, NEWCAS 2006 - Conference Proceedings, 2006
It is believed that the concept of integrated optical interconnect is a potential technological s... more It is believed that the concept of integrated optical interconnect is a potential technological solution to alleviate some of the ever more pressing issues involved in exchanging data between cores in SoC architectures (inter-line crosstalk, latency, global throughput, connectivity and power consumption). This abstract summarises work carried out in the framework of the EU-funded PICMOS project on the quantitative comparison of optical interconnect to electrical interconnect in the context of on-chip data communication.
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Papers by Ian O’Connor