ELECRONICS AND COMMUNICATION

A novel low-power reconfigurable time-interleaved (TI) symmetric cross-coupled sigma-delta (ΣΔ) modulator intended for GSM/ Bluetooth/ GPS/ WCDMA/ WLAN /WiMAX multi-standard application has been proposed in this paper. The modulator is based on TI cross-coupled first order ΣΔ paths with enhanced noise shaping characteristics. A new dual-extended (DE) noise shaping technique is introduced in the modulator to achieve power and area efficiency, satisfying desired Quality of Service. The ΣΔ modulator reconfigures its enhanced noise shaping cross-coupled paths and building blocks in order to adapt the performance to the diverse multistandard specifications. The TI cross-coupling technique is adopted as an elegant way to decrease the operating speed or equivalently to increase the conversion bandwidth of ΣΔ modulators. Compared to other alternatives, an improved peak SNR of 93/ 93/ 70/ 67/ 62/ 51 dB is achieved for GSM/ Bluetooth/GPS/WCDMA/WLAN/WiMAX mode with low over-sampling ratio (OSR) and minimum hardware. The simulation results demonstrate the efficiency and feasibility of the proposed modulator and it fulfills the performance requirements of the mobile communication standards mentioned above.

A band pass ΣΔ modulator using three different noise shaping based cross coupling techniques is proposed here. The effective use of time interleaving technique along with noise cross-coupling improves the performance of the modulator. Three variations of the conventional architecture are proposed - simple cross-coupling, extended cross-coupling and dual extended cross-coupling, which enhances effective order of noise shaping for a band pass modulator without significant overhead. By using extended cross-coupling and dual extended cross coupling architectures, the order of NTF is improved and it is evident that the proposed architectures shows a better in-band noise rejection with relaxed circuit specifications.

This paper proposes a watermarking scheme for intellectual property (IP) identification based on testing method in soc design. The core concept is embedding the watermarking generating circuit (WGC) and test circuit (TC) in to the soft IP core at the behavioural design level. Therefore this scheme can successfully survive synthesis, placement and routing and can identify the IP core at various design levels. The IP core does not change after manufactured

With the recent advances in smart phones and their ease of availability to common man, researchers are exploring efficient algorithms for face recognition on mobile devices for entertainment applications. The limited memory and processing power on mobile devices pose significant challenge to the satisfactory of popular face recognition algorithms like LBP, ICA, PCA, Neural Networks etc. In this paper, a novel and efficient algorithm is proposed using Active Pixels which capture the essential local information of the facial image. The brody transform makes the approach more robust to rotational, translational invariance's. The experiments were conducted on standard face recognition databases like FGNET age dataset and color FERET dataset, Texas 3D Face Recognition Database (Texas 3DFRD). The results demonstrated that our approach reduced memory requirement by 80% and the computational time by 70% in comparison with LBP approach while yielding same or even better recognition accuracy.

Accurate spectral decomposition is essential for the analysis and diagnosis of histologically stained tissue sections. In this paper we present the first automated system for performing this decomposition. We compare the performance of our system with ground truth data and report favorable results.

This paper presents an area efficient implementation of a high performance parallel multiplier. Radix-4 Booth multiplier with 3:2 compressors and Radix-8 Booth multiplier with 4:2 compressors are presented here. The design is structured for m × n multiplication where m and n can reach up to 126 bits. Carry Lookahead Adder is used as the final adder to enhance the speed of operation. Finally the performance improvement of the proposed multipliers is validated by implementing a higher order FIR filter. The design entry is done in VHDL and simulated using ModelSim SE 6.4 design suite from Mentor Graphics. It is then synthesized and implemented using Xilinx ISE 9.2i targeted towards Spartan 3 FPGA.

Previous research suggests that perceived risk is an important ingredient in the consumer decision-making process. The purpose of the present study is to investigate what are the perceived barriers to Internet usage and e-marketing by both users and non-users. By understanding these potential obstacles, more efficient marketing strategies will become available that will drive Internet use and e-commerce. A detailed perceived risks map has been developed using a qualitative research paradigm. We suggest a model with the factors affecting the Internet's perceived risk elements. The factors are demographi c traits and usage behavior characteristics. The model is tested against a sample of 465 employed adults.

• RoadRunneR-128-Recently invented lightweight block cipher, specifically designed for 8-bit platforms[1]. • Design and hardware implementation of IP core for RoadRunneR-128 on FPGA. • Evaluation of performance , resource utilization and estimated power consumption of the design on FPGA.