Questions tagged [cpu-pipelines]
The cpu-pipelines tag has no usage guidance.
125 questions
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Static two-issue RISC-V pipeline: how is this sd and blt data hazard handled?
I was following through this example (From the subheading Simple Multiple-Issue Code Scheduling in chapter 4.10 of
Computer Organization and Design RISC-V Edition by
Hennesy, Patterson), an example ...
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How frequently would false dependencies occur without register renaming?
Given an out-of-order processor without register renaming, how frequently would false dependencies occur? I've been trying to find papers that actually measure this, but I have found nothing. AI ...
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MIPS pipelined CPU Read and Write from Registers on First and Second Halves of Clock Cycle
In a pipelined MIPS CPU, writing to the pipeline registers, registers and PC occurs when the in the rising edge of the clock, and reading occurs in the falling edge, according to my understanding.
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I1 writing back to memory, while I2 currently executing on value depended on I1. How is result coherency maintained?
question regarding OOE.
Imagine two instructions
mov %rax, [an_address} // I1
mov [an_address] %rbx // I2
I1 makes it into the execute stage of an intel CPU. And ...
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Minimum number of instructions to execute so performance of one processor is higher
An ARM CortexA77 processor has a 13-stage pipeline and a clock frequency of 2.6 GHz.
An ARM Neoverse E1 processor version has a 10-stage pipeline and a clock frequency of 3.1 GHz.
Both processors use ...
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Issue understanding how control signals are pipelined in a RISC architecture
I'm currently implementing a RISC prozessor in a HDL and realized that I seem to have a somewhat incorrect understanding of how pipeling works for control signals. Here's my general understanding:
...
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44
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Step in RISC-V program on a Pipelined Processor
I struggle to understand a step in the following solution to a RISC-V exercise.
Exercise: a pipelined RISC-V processor with no data forwarding paths executes the following program. For each ...
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139
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Why can't I use data forwarding in this exercise?
as the title says, I am wondering why this exercise doesn't show a data forwarding from the "ex" stage of 2nd instruction to "ex" stage of 3rd instruction.
P.S. the architecture is ...
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Can a branch be pipelined with certainty if the branch condition can be known significantly before the actual branch?
A common issue with CPU performance is that pipelining requires the knowledge of what will come next, and what comes next can only be known once a branch condition is evaluated, so that instructions ...
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43
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Dependency in pipeline
Assume the pipeline is initially empty and the processor is given 8 instructions to execute. However, the 4th instruction is an instruction whose operands depend on the result of the previous ...
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Data hazard in MIPS: SW after ADD
Use the five-stage pipeline with forwarding unit.
add $t1, $t2, $t3
sw $t1, 0($t4)
In the above code, is the data hazard of t1 fixed by forwarding the correct t1 ...
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How efficient is register renaming?
As I understand, all modern CPUs perform register renaming: given a sequence of instructions to interpret, they check which registers these instructions use, detect patterns where a register's ...
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247
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What happens in harvard architecture pipelining if cpu needs to write data and fetch data at the same time?
What happens if Operand Fetch and Write Back happen in same cycle?
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Formal proof for in-balanced pipeline throughput
It is a well known fact, the throughput of a given compute pipeline (say, CPU instruction pipeline) is determined by its "slow" segment.
All the resources I've seen so far, demonstrates this ...
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502
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Split an instruction into more than four sub instructions?
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I am learning about the instructions-set in my computer science course, and I am wondering if it is possible to split an instruction into more than four sub-instructions.
Thank you
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Execution Time in Stage Pipeline
Exam Question:
A five-stage pipeline has stage delays of 150,120,150,160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each.
The total time ...
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Why does it have that amount of stalls
I'm doing an exercise about the MIPS pipeline with the following characteristics:
-Branches and Branch targets are calculated in the E-stage.
-There is forward logic from the output to the input of ...
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Forwarding in pipelined processors can increase throughput by decreasing amount of stalls, but can it in some cases impair performance?
Pipelined processors suffer from stalls due to different kind of hazards and one way of dealing with it is to implement forwarding of different types. For example ALU-ALU forwarding or full forwarding ...
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130
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Superscalar design on SimpleScalar simulation
I've learnt theoretically Computer Architecture at uni.However I can't wrap my head around it in practice. I am using Simple Scalar tool to simulate a benchmark program with configurable computer ...
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147
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MIPS pipeline: MEM stage takes one cycle?
Apparently, each stage of the MIPS processor pipeline takes one CPU cycle. According to this, a memory write can take more than one cycle:
1 cycle to read a register 4 cycles to reach to L1 cache 10 ...
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287
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Why we need CPU registers with pipeline?
I understand how CPUs work in general in RiscV, but things got a little complicated with pipeline and I don't get it why we need registers at all. For example, let's look at:
When the ALU's input was ...
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529
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How can an instruction be fetched every cycle?
From what I understand, in a pipelined CPU, every stage takes 1 cycle. But instructions are fetched from memory which takes up to ~150 cycles. The CPU fetches most instructions from the L1-cache, but ...
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424
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Why does this branch data hazard happen during the instruction decode stage?
Suppose I have the following MIPS code on a CPU with forwarding enabled:
...
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Number of stall cycles when there is only EX/MEM pipeline registers or only MEM/WB pipeline register
I am working on a problem which is related to The processor. The problem is the problem 4.12 in the book whose title is "Computer Organization and Design". The problem has the assumption as ...
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Does higher cpi give better performance?
Does higher cpi give better performance?
Lets say there is a code and we can run it by 3 methods.
1 cpi for single cycle
99 cpi for multi cycle
70 cpi for pipeline
Multi cycle has the highest cpi for ...
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134
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Is pipeline bubbling only used with RAW data hazards?
I am studying computer science at university and we have an exam, which consists of several problems, one of which has to deal with pipelines.
My understanding is that one effective way to solve data ...
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983
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?
I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution as seen in number 5 of some homework assignment solutions. But I ...
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238
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Identifying problem in MIPS pipeline datapath
I'm having trouble identifying a problem in this pipelined datapath. After executing an add instruction, there are 5 subsequent R-type instructions executed. However, we are assuming no data hazard, ...
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426
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Dividing EX stage of a pipeline into EX1 and EX2 stages
There is this problem about pipelining that does not have an answer, and I'm wondering what the answer could be:
In the five stage pipeline with forwarding support to EX, the first operand of ALU ...
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Throughput increase/decrease by how much percent
I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me?
The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350 ...
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Why does taking advantage of locality matter in multithreaded systems?
As we all know, when a given thread/process reaches a memory address it does not have cached, the execution will (for the most part) freeze up until said data is fetched from memory. What I don't ...
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569
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When the stall is actually going to happen?
Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see ...
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How to help compiler do pipelining?
I don't mean compiler flags for pipelining. I would like to program in a way that helps the compiler do optimizations using pipelining. I mean I want to order instructions in C in such a way that GCC (...
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43
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About the connection of pipelined execution and latency
Let's consider we want to calculate a[i]=a[i]*c for a vector the size of N=12 on some random processor.
We do assume that ...
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755
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
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Calculating the pipeline speed up in case we have an infinite amount of stages
I have the following question:
We begin with a computer implemented in single-cycle implementation.
When the stages are split by functionality, the stages do not require
exactly the same amount of ...
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Why cannot Operand forwarding remove all RAW hazards?
I read a statement in the textbook that : Operand Forwarding cannot remove all RAW Hazards in Pipelined Processor but am unable to conceptualize that in my brain. Can you please explain it with an ...
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3k
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How to improve the CPI and Speed up factor in CPU-OS simulator?
I am using the CPU-OS simulator by Besim Mustafa(https://www.merlot.org/merlot/viewMaterial.htm?id=476196) and I am studying Pipeline Stages. I have written a simple program and captured the metrics ...
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How can I get 8 bits output from 4 bit CPU?
I am very new to Computer architecture. I am thinking to add one more output register to this 4 bit CPU as shown below. However, I am not sure should I connect the output register to the current CPU. ...
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Detecting Data and Control Hazards for a mips 5 stage pipeline
I'm practicing data and control dependencies, but having trouble detecting them. For this example, I'm assuming this pipeline is fully bypassed (with forwarding). I think the only data dependency is ...
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216
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MIPS pipeline: choosing between slowing down a stage and adding a new stage
Suppose a new, more complicated, instruction is desired for this
simple pipelined MIPS processor. Suppose, also, it could be
implemented by either (a) adding new logic to the execute stage of the
...
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Neural branch predictors linear, classical predictors exponential, in resources?
Wikipedia states:
The main advantage of the neural predictor is its ability to exploit long histories while requiring only linear resource growth. Classical predictors require exponential resource ...
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How many RAW dependencies are present in these instructions?
What is the number of RAW dependencies in below set of instructions?
I1: R1 = R2 - R3
I2: R2 = R1 + R3
I3: R3 = R1 + R2
I4: R1 = R2 - R2
I can see the following ...
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953
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Deep pipeline - cpu architecture
I was reading and learning about SIMD and AVX2 vector instruction, as I was trying to implement them for better performance.
While reading about vector instruction, I encountered the term deep ...
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How to make single cycle processor pipelined?
I was asked that how can one make a single cycle processor pipelined on a CS course without any specifications regarding the design.
I suppose, that I should answer that what should be changed on ...
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How can instruction fetch and decode pipeline stages run simultaneously in a CPU with dynamic branch prediction?
I have recently been investigating CPU pipelining and branch prediction and have a question about how exactly these fit together.
If, for example, instructions are meant to be fetched in one stage of ...
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Confusion in speed up calculation for pipeline architecture
This is an online question I am trying to solve.
You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, ...
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Calculate Stages in Non-Pipelined Processor
I have tried to attempt a question where I have to find the number of stages for non-pipelined processor(8085) for below program :-
...
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In instructions pipelining, why does register read/write take up only half clock cycle?
While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in ...
