Questions tagged [computer-architecture]
Questions about the organization and design of computer hardware.
1,154 questions
-3
votes
0
answers
43
views
Theory Of Automata [closed]
Each of the following languages is the intersection of two simpler languages. In
each part, construct DFAs for the simpler languages, then combine them using the
construction discussed in footnote 3 (...
- 1
2
votes
1
answer
61
views
Is there such data type for low range float?
For integers, we have unsigned integers to represent positive integers, including zero, and we have signed integers to represent negative and positive. There are always trade-offs between them.
For ...
0
votes
0
answers
9
views
0 address instruction format for subtraction
Suppose we want to subtract (3-2) using the 0 address instruction format.The code will be
push 2
push 3
sub
or
push 3
push 2
sub
And what about other logical instructions(NOT,AND,OR,XOR) , how can we ...
- 131
-2
votes
0
answers
15
views
Find the step values for best and worst hit ratios
The following code snippet is executed on a system that uses a cache with a size of 128 bytes and a block size (1 row width) of 32 bytes. The array holds 2-byte int values.
...
- 1
0
votes
1
answer
26
views
Assembly question ISA
I am studying for a exam in Computer Architecture and one of the exercises says this:
write the assembly code which calculates the equation of D=(A+B)/4+C.The ISA of the processor has the following ...
- 131
1
vote
1
answer
21
views
Is DMA (Direct Memory Access) interrupt maskable?
My textbook states that DMA will interrupt the CPU once a batch of data is swapped to memory. However, it didn't tell me whether the DMA interrupt is maskable. Is it maskable?
- 113
1
vote
0
answers
37
views
Superficial reference on Computer Architecture
If one had to suggest a basic, well-known, comprehensive introductory reference on computer architecture,
it would be reasonable to assume that one would suggest one of the following:
Patterson & ...
- 111
2
votes
1
answer
61
views
Is GPU memory coalescing something the hardware does or the programmer does?
I am learning about memory coalescing in NVIDIA GPUs. I am trying to understand what exactly coalescing is. More specifically, is it something specifically implemented by hardware, or is it just the ...
- 23
0
votes
0
answers
34
views
How is two way set associative cache better than a direct mapped cache?
I'm trying to learn computer architecture now on my own, and while I understand how two way set associative cache and direct mapped (one way) cache works from watching videos, it's not clearly what ...
- 101
0
votes
0
answers
19
views
8x2ram and 16x1ram difference
I want to know the difference between 8x2ram and 16x1ram and the storage capacity.
Is it correct that the total storage capacity is the same as 2^16 bits?
Is it correct that 8x2ram has 8 addresses and ...
- 1
5
votes
1
answer
2k
views
Modern x86-64 architecture diagram?
I’m currently exploring the x86-64 architecture and have downloaded both Intel's SDM (5000 pages) and AMD's Programmer's Manual. To my surprise, I haven’t come across any high-level overview diagrams ...
- 295
0
votes
0
answers
47
views
What exactly is multithreading? What happens in multithreading?
I was watching a lecture video on GPUs in which the lecturer says that in multithreading, registers are reserved for the warps before they are switched. Can someone explain what happens in ...
0
votes
0
answers
22
views
What are the timing signals a CU produces?
Quoting for Wikipedia:
The control unit (CU) is a component of a computer's central processing unit (CPU) that directs the operation of the processor. A CU typically uses a binary decoder to convert ...
- 131
1
vote
0
answers
61
views
Were the Space Shuttle computers truly MISD (Multiple Instruction, Single Data)?
I’m trying to understand whether the Space Shuttle flight control computers, which are sometimes referred to as MISD (Multiple Instruction, Single Data), truly fit this classification.
According to ...
- 11
1
vote
1
answer
40
views
Are WAR and WAW hazards only possible if we have parallel computing
I was reading on WAW and WAR data hazards and I think that these can only happen if we have parallel computing ,in contrast with RAW data hazard which can happen even if we dont have parallel ...
- 131
0
votes
2
answers
51
views
Where is the missing stack in this 8086 CPU?
I found a picture of a 8086 family CPU.Where is the stack?I get it that the base and stack pointer are part of the general registers.
But shouldnt inside the ALU be both registers and a stack since ...
- 131
0
votes
2
answers
93
views
How are bubbles created inside the CPU?
Suppose we have a CPU which uses pipelining.One way for the efficiency to be reduced is if a bubble is created (e.g the cpu cannot fetch or decode a instruction)which delays the instruction execution ...
- 131
2
votes
1
answer
1k
views
Are 8086 family microprocessors accumulator based?
I know that 8086 microprocessor family microprocessors are both register and stack based microprocessors.I have been searching if they were also accumulator based microprocessors but couldnt find ...
- 131
0
votes
0
answers
17
views
Correct method of determining offset when doing multi level page table walking
On this page, I see the following code for determining the address of a page table entry:
...
- 113
1
vote
0
answers
29
views
Does newer CPU includes instruction set for popular hash and crypto algorithms
I mean since the algorithms like SHA256, MD5, AES, RSA are so widely used, so do these kind of popular algorithm get their special instruction set hardwired in newer CPU ?
And if they do, how fast do ...
- 11
-2
votes
8
answers
1k
views
Why do computers use binary numbers in IEEE754 fraction instead of BCD or DPD?
I asked a new question because it more accurately reflects what I asked: about:Why don't decimal-floating-point numbers have CPU level support like float point numbers in usual computers?
I will ...
user173333
0
votes
0
answers
35
views
Is this David Patterson 'Computer Architecture A Quantitative Approach' scheme right?
My guess is that L1 cache tag is also 28 bits as the L1 tag compare adress.
Another question is why the offset is going to CPU?
And the last one What other improvements and errors does this memory ...
0
votes
0
answers
23
views
Is my characterisation of KVM and QEMU accurate?
I usually write essays on topics I am studying to help my understanding. Below are excerpts from my study of Virtualisation. I would like comments from real professionals on their accuracy.
KVM is a ...
1
vote
1
answer
19
views
I1 writing back to memory, while I2 currently executing on value depended on I1. How is result coherency maintained?
question regarding OOE.
Imagine two instructions
mov %rax, [an_address} // I1
mov [an_address] %rbx // I2
I1 makes it into the execute stage of an intel CPU. And ...
- 13
2
votes
2
answers
67
views
Desktop computing: who needs multi-threading, multi-processing; and how much?
I am currently running the KDE on OpenSuSE in a VirtualBox hosted by Windows 11 running on a processor with 14 cores. I gave Linux 4 CPUs to play with. So, I am aware of the need for some amount of ...
1
vote
2
answers
89
views
Why does ISA includes instruction for logical operation?
I'm a junior student in Electronic Engineering.
Recently, I learned about Gödel's incompleteness theorem. One of the concepts related to this theorem is Gödel numbering, which shows that every logical ...
- 11
0
votes
1
answer
28
views
Is there a service provided by the OS, which is NOT accessible by the terminal emulator?
Is there a service provided by the OS, which is NOT accessible by the terminal emulator? If so, how else would the user be accessing it?
(My guess is, there wouldn't be since that would be silly. But ...
- 1
0
votes
1
answer
68
views
Is it possible to completely remove a pre-installed OS from a manufactured computer?
I was told by my professor that when a computer is manufactured, it comes with an OS where the OS is installed in two different parts. The first part is physically "hardwired" (?) into the ...
- 1
1
vote
3
answers
165
views
Basic questions regarding a computer
I'm an Undergraduate CS student. My understanding of a "computer" is that it is simply a machine that can "carry out" a set of instructions. The set of instructions it can ever ...
- 11
1
vote
1
answer
31
views
Floating Point to Integer Conversion (fcvt.*) hardware implementation
In the RISC-V specification, there is support for the conversion between floating point and integer numbers, in particular the fcvt* class of instructions. I'm wondering what the hardware ...
0
votes
2
answers
132
views
Why is ROM read only? And why do SSDs use it?
I was researching about SSDs and ended up going further and reading about how it uses flash technology which from what I gather is pretty much an EEPROM, which (I might be wrong on this) is just an ...
- 1
1
vote
2
answers
115
views
Why is the default page/block size 4 KiB?
Clearly, some empirical study on an older machine helped us choose a 4KiB page size to balance TLB hit rate and fragmentation. Modern hardware and operating systems support this size for backward ...
- 11
0
votes
1
answer
41
views
Is there a delay between two commands to read data from RAM?
Everyone knows that the speed of the CPU is many times faster than the speed of RAM, whereas in this case the processor executes two read or write commands in memory running in a row? As I assume, due ...
- 11
1
vote
1
answer
88
views
Byte addressing and alignment
With byte addressing, the CPU can access a single byte. But how does this access happen during alignment? As I understand it, if a CPU needs to read an unaligned byte, it reads the word starting from ...
- 11
1
vote
1
answer
185
views
MIPS: How can the least 2 significant bits of a 32-bit address specify a byte?
I was reading Computer Architecture Organization and Design by David A. Patterson and John L. Hennessy. Specifically, I was reading chapter 5, section 5.3, Basics of Caches. I read the following ...
0
votes
0
answers
20
views
Daughter-board multiplier
I am writing a program in TI Code Composer Studio assembly-only empty project using the MSP-EXP430FR6989. The assembly-only empty project uses MSP430 Assembler Code Template for use with TI Code ...
0
votes
1
answer
50
views
Are modern ram architectures (DDR4 or SDRAM) Multi-port or Dual-port?
So I recently learned about dual-port and multi-port RAM but I tried doing some research on modern RAM architectures and if they use it but I couldn't find anything on it.
0
votes
0
answers
33
views
Why do two pairs of identical DDR4 RAM not work together?
Several years ago, I tried to get two identical pairs of DDR4 RAM to run together in my computer. I have since bought a set of four, but I've always wondered why the RAM didn't work. Its been long ...
2
votes
1
answer
117
views
Measuring Cache Access Time
I want to make a simple C program in order to measure L1, L2 and L3 latencies of my CPU. I know some info about them:
...
2
votes
1
answer
88
views
How CPU uses wider address bus than register size?
i'm designing a CPU from scratch so i want it to be small. i decided to go with 4 bits registers. but 16 words of memory is a bit too small and i want more so i guess i need wider address bus (ie. 6). ...
- 121
0
votes
0
answers
59
views
Expected hit ratio for a cache
I am trying to understand how to approach the question below which is a coursework question. I understand that each memory request is 32 bits and so there will be 262144 requests. There are 42 blocks ...
- 1
2
votes
1
answer
69
views
Issue understanding how control signals are pipelined in a RISC architecture
I'm currently implementing a RISC prozessor in a HDL and realized that I seem to have a somewhat incorrect understanding of how pipeling works for control signals. Here's my general understanding:
...
- 21
0
votes
1
answer
20
views
The Atlas system word addresses
I'm reading about the Atlas operating system and I came across this:
The Atlas system used a British computer with 48-bit words. Addresses were 24 bits but were encoded in decimal, which allowed 1 ...
- 33
0
votes
0
answers
25
views
What is Representation Invariant?
I was the book "Introduction to Computation and Programming Using Python" and I stumbled upon the concept of representation invariant. What I understood is that the variables (and maybe ...
- 1
2
votes
1
answer
30
views
Memory addresses requested by CPU vs Memory Address Provided to DRAM
So, i just got through studying DRAM architecture. I learned that a row address, column address, bank number etc are provided to the DRAM during a read operation. Based on the address provided, 64 ...
- 21
0
votes
0
answers
10
views
Relation between MTTF (Mean Time to Failure) and FIT (Failure in time) in computer architecture
I have a doubt regarding relation between MTTF (Mean Time to Failure) and FIT (Failure in time). Is it FIT = 1/(MTTF1 + MTTF2 + ...) or FIT = 1/MTTF1 + 1/MTTF2 + ... ?
0
votes
0
answers
26
views
relationship between page table size, patge table entry and pagt table base register alignment
I am trying to understand this question from Prof. Onur Mutlu's assignment solution on virtual memory.
I am reproducing the problem and solution followed by my question:
Problem: A dedicated computer ...
- 1
0
votes
0
answers
17
views
Best solution architecture for: Intelligent chat to retrieve information from specific sources
I am trying to design best solution for a chat application based on LLM model which has set of functions and based on user input can retrieve the information.
I would like to ask you for some ...
- 101
2
votes
1
answer
49
views
Problem with cache and memory from university class
In my university class, I received this homework assignment on computer architecture, but I don't know how to solve it. I already know that the correct answer is 0, but I don't understand why. Could ...
- 21
0
votes
3
answers
191
views
How many operands does the NOP instruction have?
At first I thought it is obvious, since the NOP instruction does not have any operand, we say it is zero-operand instruction. But then looking on the zero-operand ...
- 208