Input-Output Organization

Outline
Peripheral Devices
Input-output Interface
Asynchronous Data Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Input-output Processor
Serial Communication
Peripheral Devices – Input Devices
 Keyboard
 Optical Input Device
 Card reader
 Paper tape reader
 Bar code reader
 Digitizer
 Optical Mark reader
 Magnetic Input Device
 Magnetic Stripe Reader
 Screen Input Device
 Touch Screen
 Light Pen
 Mouse
 Analog Input Device
Peripheral Devices – Output Devices
Card Puncher
 Paper Tape Puncher
CRT
Printer
 Impact, Ink Jet, Laser, Dot Matrix
Plotter
Analog
Voice - Speakers
Input – Output Interfaces
Provides a method for transferring information
between internal storage (Such as Memory and CPU
registers) and external I/O devices
Resolves the differences between the computer and
peripheral devices
 Peripherals – Electromechanical Devices
 CPU or Memory – Electronic devices
Data Transfer Rate
 Peripherals – usually slower
 CPU or Memory – usually faster than peripherals
 Some kinds of synchronization mechanism may be needed
Input – Output Interfaces
Unit of Information
 Peripherals – Byte
 CPU or Memory - Word
Operating Modes
 Peripherals – Autonomous, Synchronous
 CPU or Memory - Synchronous
 I/O Bus
Communication with in a computer via a single
shared bus
I/O Bus Data

Address
processor
Control

Interface Interface Interface Interface

Keyboard
Magnetic Magnetic
and Display Printer
Disk Tape
terminal
Interface Module
Each peripheral has an interface module associated
with it
Interface
 Decodes the device address (device code)
 Decodes the commands (operation)
 Provides signals for the peripheral controller
 Synchronizes the data flow and supervises the transfer rate
between peripheral and CPU or Memory
Typical I/O Instruction

Op-code Device Address Function Code

Command
Connection of I/O Bus to CPU
Processor

Device Function Accumulator Computer

Op-code
Address Code Register I/O Control

Sense Lines
Data Lines I/O
Bus
Function Code Lines
Device Address Lines
 Connection of I/O Bus to One Interface

Data Lines Peripheral

Register

Device Buffer Register

address Output
Peripheral
I/O AD=1101
Interface Device
Bus Logic and
Controller
Function code Command
decoder

Sense lines Status

Register
Types of Commands
Control Command
 Activates the peripheral and inform it what to do
Status Command
 Test various status conditions in the interface or the
peripherals
Data-output Command
 Output
Data-input Command
 Input
I/O Bus and Memory Bus: Functions
 Memory Bus
 Is for information transfer between CPU and the main memory
 I/O Bus
 Is for information transfer between CPU and I/O devices through their
I/O interface
 Physical Organizations
 Many computers uses a common single bus system for both memory
and I/O interface units
 2 – Way bus:
 Use one common bus but separate control lines for each function

 Use one common bus with common control lines for both

functions
 Some computer systems use two separate buses, one to communicate
with memory and the other with I/O Interface
I/O Bus
Communication between CPU and all interface units
is via a common I/O bus
An interface connected to a peripheral device may
have a number of data registers, a control register,
and a status register
A command is passed to the peripheral by sending to
the appropriate interface register
Function code and sense lines are not needed
 Transfer of data, control and status information is always
via the common I/O Bus
Isolated I/O (I/O Mapped I/O)
Separate I/O read/write control lines in addition to
memory read/write control lines
Separate (isolated) memory and I/O address spaces
Distinct input and output instructions
 IN and OUT Instructions
Memory Mapped I/O
A single set of read/write control lines
 No distinction between memory and I/O transfer
Memory and I/O addresses share the common
address space
 Reduces memory address range available
No specific input or output instruction
 The same memory reference instructions can be used for
I/O transfers
Considerable flexibility in handling I/O operations
 All instruction directly access memory location and can
manipulate
 Programmed I/O Interface

Port A I/O Data

Bidirectional
Register
Bus Buffers
Data Bus
Port B I/O Data
Chip Select Register
CS
Register Select
RS1
Timing Control Control
Register Select
RS0 and Register
I/O Read Control
RD
I/O Write Status Status
WR
Register

To CPU To I/O device

Programmed I/O Interface
CS RS1 RS0 Register Selected
0 X X None – data bus in High impedence
1 0 0 Port A Register
1 0 1 Port B Register
1 1 0 Control Register
1 1 1 Status Register
Programmable Interface
Information in each port can be assigned a meaning
depending on the mode of operation of the I/O
device
 Port A = Data; Port B = Command; Port C = Status
CPU initializes (loads) each port by transferring a byte
to the Control Register
 Allows CPU can define the mode of operation of each port
 Programmable Port
 By changing the bits in the control register, it is possible

to change the interface characteristics

Data Transfer
The data transfer between the CPU and the
peripherals can be two ways
Synchronous
 All devices derive the timing information from common
clock line
Asynchronous
 No common clock
Asynchronous Data Transfer
 Asynchronous data transfer between two independent
units requires that control signals to be transmitted
between the communicating units
 To indicate the time at which data is being transmitted
Two Asynchronous Data Transfer Methods
Strobe Pulse:
 A strobe pulse is supplied by one unit to indicate the other
unit when the transfer has to occur
Handshaking:
 A control signal is accompanied with each data being
transmitted to indicate the presence of data
 The receiving unit responds with another control signal to
acknowledge receipt of the data
 Strobe Control
Employs a single control line for each transfer
The strobe may be activated by either the source or
the destination unit

Source Initiated Strobe for Data Transfer

Data Bus
Source Destination
Unit Strobe Unit

Timing Diagram
Data Valid data

Strobe
 Strobe Control
Destination-initiated Strobe for Data Transfer

Data Bus
Source Destination
Unit Strobe Unit

Timing Diagram

Data Valid data

Strobe
Handshaking Data Transfer
Strobe Methods
 Source Initiated:
 The source unit that initiates the transfer has no way of

knowing whether the destination unit has actually

received data
 Destination Initiated:
 The destination unit that initiates the transfer no way of

knowing whether the source has actually placed the

data on the bus
To solve this problem, the HANDSHAKE method
introduces a second control signal to provide a reply
to the unit that initiates the transfer
 Source Initiated Transfer - Handshake
Data Bus

Source Data Valid Destination

Unit Data accepted Unit

Timing Diagram
Data bus Valid data

Data Valid

Data Accepted
Handshaking: Sequence of Events
 Allows arbitrary delays from one state to the next
 Permits each unit to respond at its own data transfer rate
 The rate of transfer is determined by the slower unit

Place data on bus;

Enable data valid
Accept data from bus;
Enable data accepted

Disable data valid;

Invalidate data on bus
Disable data accepted;
Ready to accept data
(Initial state)
 Destination Initiated Transfer - Handshake
Data Bus

Source Data Valid Destination

Unit Ready for Data Unit

Timing Diagram
Ready for data

Data Valid

Data Bus Valid data

Destination Initiated Transfer - Handshake
 Handshaking provides a high degree of flexibility and
reliability because the successful completion of a data transfer
relies on active participation by both units
 If one unit is faulty, data transfer will not be completed
 Can be detected by means of a timeout mechanism

Destination Unit
Source Unit
Ready to accepted data;
Place data on bus; Enable ready for data
Enable data Valid

Accept data from bus;

Disable data valid; Disable ready for data
Invalidate data on bus;
Final State
Data Transfer Types
Four different types of data transfers
Asynchronous Serial Transfer
Synchronous Serial Transfer
Asynchronous Parallel Transfer
Synchronous Parallel Transfer
Asynchronous Serial Transfer
Employs special bits which are inserted at both ends
of the character code
Each character consists of three parts
 Start bits
 Data bits and
 Stop bits

1 1 0 0 0 1 0 1
Stop
Character bits
bit
(at least 1 bit)
Start bit (1 bit)
Asynchronous Serial Transfer
A character can be detected by the receiver from the
knowledge of 4 rules
 When data are not being sent, the line is kept in the 1-
state
 The initiation of a character transmission is detected by a
Start Bit, which is always a ‘0’
 The character bits always follow the Start Bit
 After the last character, a Stop Bit is detected when the
line returns to the 1-state for at least 1 bit time.
The receiver knows in advance the transfer rate of
the bits and the number of information bits to expect
 UART
 UART: Universal asynchronous receiver-transmitter
 A typical asynchronous communication interface available as
an IC
Transmit
Transmitter Shift Data
Bidirectional Register Register
Data Bus Bus
Buffers Transmitter
Internal Bus Control Tx Control Clock
Register & Clock

Receiver
Chip Select
CS Status Rx Control Clock
Register Select Register & Clock
RS Timing
I/O Read And Receive
RD Control
I/O Write Receiver Shift Data
WR Register Register
UART
CS RS Operation Register Selected
0 X X None: Data bus in high-impedence
1 0 WR Transmitter Register
1 1 WR Control Register
1 0 RD Receiver Register
1 1 RD Status Register

 Transmitter Register:
 Accepts a data byte (from CPU) through the data bus
 Transferred to a shift register for serial transmission
 Receiver:
 Receives serial information into another shift register
 Complete data byte is sent to the receiver register
UART
Status Register Bits:
 Used for I/O flags and for recording errors
Control Register Bits:
 Define baud rate, no. of bits in each character, whether to
generate and check parity, and no. of stop bits.
FIFO (First-In-First-Out) Buffer:
 Input data and output data at two different rates
 Output data are always in the same order in which the
data entered the buffer
 Useful in some applications when data is transferred
asynchronously
Data Transfer Modes between CPU & Peripherals

Three different data transfer modes between the

central computer (CPU or Memory) and peripherals
Program Controlled I/O
Interrupt Initiated I/O
Direct Memory Access (DMA)
Programmed Controlled I/O

Interface
Data Bus I/O Bus

Address Bus Data Register

Data Valid
I/O
CPU
I/O Read Device
Data Accepted
Status
I/O Write F
Register

Programmed Controlled I/O – Input Device to CPU

 Programmed Controlled I/O
Read Status Register
Check flag bit

Polling or
Status check
=0
Flag

=1
Read data Register
Transfer data to Memory
 Polling or Status Checking
 Continuous CPU involvement No Operation
 CPU slowed down to I/O speed Complete
 Simple
 Least hardware Yes
Continue with
Program
Interrupt Initiated I/O
 Polling takes valuable CPU time
 Open communication only when some data has to be passed
 Interrupt
 I/O interface, instead of the CPU, monitors the I/O device
 When the interface determines that the I/O device is ready
for data transfer
 it generates an interrupt request to the CPU
 Upon detecting an interrupt,
 CPU stops momentarily the task it is doing,
 branches to the services routine to process the data transfer, and
 then returns to the task it was performing
DMA (Direct Memory Access)
Large blocks of data transferred at a high speed to or
from high speed devices
 Magnetic drums, disks, tapes, etc.,
DMA Controller
 Interface that provides I/O transfer of data directly to and
from the memory and the I/O device
CPU initializes the DMA controller by sending a
memory address and the number of words to be
transferred
Actual transfer of data is done directly between the
device and memory through DMA controller
 Freeing CPU for other tasks
Interrupts
Interrupt Request Line
 Interrupt-request signal
 Interrupt-acknowledge signal
Interrupt Service Routine
 Similar to subroutine
 May have no relationship to program being executed at
time of interrupt
 Program info must be saved

 Interrupt latency
Handling Interrupts
Many situations where the processor should ignore
interrupt requests
 Interrupt-disable
 Interrupt-enable
Typical scenario
 Device raises interrupt request
 Processor interrupts program being executed
 Processor disables interrupts and acknowledges interrupt
 Interrupt-service routine executed
 Interrupts enabled and program execution resumed
Interrupt from N Devices
An equivalent circuit for an open-drain bus used to
implement a common interrupt-request line.

Vdd
Processor
R
I NTR
INTR

INTR1 INTR2 INTR n

Handling Multiple Devices
How can the processor recognize the device
requesting an interrupt?
How can the processor obtain the starting address of
the appropriate interrupt-service routine?
Should a device be allowed to interrupt the
processor while another interrupt is being serviced?
How should two or more simultaneous interrupt
requests be handled?
Interrupt Priority
 Multi-level priority organization
 During execution of interrupt-service routine
 Disable interrupts from devices at the same level priority
or lower
 Continue to accept interrupt requests from higher priority

devices
 Privileged instructions executed in supervisor mode

 Controlling device requests

 Interrupt-enable

 EN, DEN
Interrupt Priority
Implementation of interrupt priority using individual
interrupt-request and acknowledge lines
Processor

INTR2 INTRp
INTR1
Device 1 Device 2 Device p
INTA1 INTA2 INTAp

Priority Arbitration Circuit

Interrupt Priority
Polled interrupts
 Priority determined by the order in which processor polls
the devices (polls their status registers)
Vectored interrupts
 Priority determined by the order in which processor tells
device to put its code on the address lines (order of
connection in the chain)
Priority Interrupt
Determines which interrupt is to be served first when
two or more requests are made simultaneously
Also determines which interrupts are permitted to
interrupt the computer while another is being
serviced
Higher priority interrupts can make requests while
servicing a lower priority interrupt
Priority Interrupt by Software (Polling)
Priority is established by the order of polling the
devices (interrupt sources)
Flexible since it is established by software
Low cost since it needs a very little hardware
Very slow
Priority Interrupt by Hardware
Require a priority interrupt manager which accepts
all the interrupt requests to determine the highest
priority request
Fast since identification of the highest priority
interrupt request is identified by the hardware
Fast since each interrupt source has its own interrupt
vector to access directly to its own service routine
Daisy Chain – Hardware Priority Interrupt
Processor Data Bus

VAD 1 VAD 2 VAD 3

Device 1 Device 2 Device 3
To Next
PI PO PI PO PI PO Device

Interrupt Request
INT
CPU
Interrupt Acknowledge
INTACK

 Serial hardware priority function

 Interrupt request line – single common line
 Interrupt acknowledge line – Daisy Chain
Daisy Chain – Hardware Priority Interrupt
Interrupt Request from any device (>=1)
 CPU responds by INTACK  1
 Any device receives signal (INTACK) 1 at PI puts the VAD
(vector address) on the bus to get the service
Among interrupt requesting devices the only device
which is physically closest to CPU gets INTACK = 1
 And its blocks INTACK to propagate to the next device
 One Stage of Daisy Chain
One stage of the daisy chain priority arrangement
VAD
Priority In
PI Enable
Vector Address

Interrupt Priority Out

PO
Request S Q
From device
R PI RF PO Enable
Delay 0 0 0 0
0 1 0 0
1 0 1 0
Interrupt 1 1 0 1
Request to CPU
 Parallel Priority Interrupt
Interrupt Register Bus Buffer
Disk I0 Y
0
X
Printer 1 I1 0
Priority 0 VAD
Reader 2 to CPU
I2 Encoder
0
Keyboard 3 0
I3
0
0
IEN IST
0
Mask Enable
Register
1

2 Interrupt
To CPU
3 INTACK from CPU
Parallel Priority Interrupt
IEN: Set or Clear by instructions ION or IOF
IST: Represents an unmasked interrupt has occurred
(IEN. IST). INTACK enables tri-state Bus Buffer to load
VAD generated by the priority logic
Interrupt Register:
 Each bit is associated with an interrupt request from
different interrupt source – different priority level
 Each bit can be cleared by a program instruction
Mask Register:
 Mask register is associated with interrupt register
 Each bit can be set or cleared by an instruction
Interrupt Priority Encoder
 Determines the highest priority interrupt when more than
one interrupts take place

Priority Encoder Truth Table

INPUTS OUTPUTS
Boolean Function
I0 I1 I2 I3 X Y IST
1 X X X 0 0 1
X = I’0 I’1
0 1 X X 0 1 1
0 0 1 X 1 0 1 Y = I’0 I1 + I’0 I’2
0 0 0 1 1 1 1 IST = I0 + I1 + I2 + I3
0 0 0 0 x x 0
Interrupt Cycle
At the end of each instruction cycle
 CPU checks IEN and IST
 If IEN. IST = 1, CPU  Interrupt Cycle

 SP  SP – 1 // Decrement Stack Pointer

 M[SP]  PC // Push PC into stack
 INTACK  1 //Enable Interrupt Acknowledge
 PC  VAD // Transfer vector address to PC
 IEN  0 // Disable further interrupts
 Go to Fetch // To execute the first instruction
in the interrupt service routine
 Interrupt Service Routine
Address Memory I/O Service Programs
0 JMP DISK 7
DISK Program to Service
Magnetic disk
1 JMP PTR
3 2 JMP RDR
VAD = PTR Program to Service
00000011 3 JMP KBD
8 Line Printer
Main Program
Program to Service
KBD 1 749 Current Instr. RDR
Character Reader
Interrupt 750
4
Program to Service
KBD
11 Stack Keyboard
DISK 5 255
2 Interrupt 256
6
256
750
9
10
 Interrupt Service Routine
 Initial and Final operations:
 Each interrupt service routine must have an initial and final set of
operations for controlling the registers in the hardware interrupt system.

Initial Sequence (k: highest Final Sequence (k: Served

priority level identified) interrupt priority level)
[1] Mast R(i)  0, i =< k [1] IEN  0
[2] IST  0 [2] Restore CPU registers
[3] Save contents of CPU [3] Interrupt R(k)  0
registers
[4] IEN  1 [4] Mask R(i)  1, i = < k
[5] Go to Interrupt Service [5] Restore return address
Routine IEN  1
Direct Memory Access (DMA)
 Polling or interrupt driven I/O incurs considerable overhead
 Multiple program instructions
 Saving program state
 Incrementing memory addresses
 Keeping track of word count
 Transfer large amounts of data at high speed without
continuous intervention by the processor
 Special control circuit required in the I/O device interface,
called a DMA controller
 DMA controller keeps track of memory locations, transfers
directly to memory (via the bus) independent of the
processor
DMA Controller
Part of the I/O device interface
 DMA Channels
Performs functions that would normally be carried
out by the processor
 Provides memory address
 Bus signals that control transfer
 Keeps track of number of transfers
Under control of the processor
Direct Memory Access (DMA)
OS responds to a program’s system call for Disk Read,
for example
OS puts the program in the “blocked” or “waiting” or
“asleep” state
Initiates the Disk Read
Starts execution of another program
When Read is completed, DMA controller sends an
interrupt
 Registers in a DMA interface
31 30 1 0

Status and Control

IRQ Done
IE R/W

Starting Address

Word Count
 Registers in a DMA interface
31 30 1 0

Status and Control 1 1 0

IRQ Done
IE R/W

Starting Address 42000

Word Count 1200

Use of DMA controllers in a computer system

Main
Processor
Memory

System Bus

Disk/DMA DMA
Printer Keyboard
Controller Controller

Network
DISK DISK Interface
DMA
Processor and DMA controller(s) must “interweave”
memory accesses
DMA controllers have higher priority for obvious
reason, i.e., higher speed devices need higher
priority
DMA
If DMA gets a cycle at a time, then
 CPU gets a memory cycle (uses bus)
processor
 CPU gets a memory cycle (uses bus) gets most
 CPU gets a memory cycle (uses bus) cycles
 CPU gets a memory cycle (uses bus)
“cycle
 DMA gets a memory cycle (uses bus) stealing”
 CPU gets a memory cycle (uses bus)
 CPU gets a memory cycle (uses bus)
 CPU gets a memory cycle (uses bus)
DMA
Or

 CPU gets a memory cycle (uses bus)

 CPU gets a memory cycle (uses bus)
 DMA gets a memory cycle (uses bus)
 DMA gets a memory cycle (uses bus)
 DMA gets a memory cycle (uses bus)
 DMA gets a memory cycle (uses bus)
. “burst
. mode”

. to transfer a
block of
 DMA gets a memory cycle (uses bus) data without
interruption
 CPU gets a memory cycle (uses bus)
Sharing the Bus
Bus master: the device currently allowed to transfer
data on the bus (CPU or DMA)
Bus arbitration: choosing the next bus master
Bus busy: BBSY set by current bus master to show
that the line is in use
Bus request: BR set when device wants to become
bus master
 When it gets BG (bus granted), waits for BBSY to become
inactive, then assumes mastership of the bus and sets
BBSY
Bus Arbitration
Determination of the order in which requests for the
bus are serviced
 Fixed priority – each device has a priority rating
 Rotating priority – devices are assigned a rotating priority
value
 Central arbitration – arbiter circuit determines
 Distributed arbitration – all devices share in the
determination
 Centralized arbitration
BBSY

BR

Processor

DMA
DMA
Controller
BG1 Controller 1 BG2 2

imple arrangement for bus arbitration using a daisy c

 Centralized arbitration
DMA device 2 makes bus request ( BR)
Time

BR

BG1

BG2

B BSY

Bus
master
Processor DMA controller 2 Processor

Sequence of signals during transfer of bus mastership for the devices

 Centralized arbitration
BR

BG1

BG2

B BSY

Bus
master
Processor DMA controller 2 Processor

Processor responds with Bus Granted ( BG),

signal daisy-chained through device 1
Sequence of signals during transfer of bus
mastership for the devices
 Centralized Arbitration
BR

BG1

BG2

B BS Y

Bus
master
Processor DMA controller 2 Processor

Processor releases bus, sets BBSY

Sequence of signals during transfer of bus mastership for the devices

 Centralized Arbitration
DMA device 2 removes bus request ( BR)
Time

BR

BG1

BG2

B BS Y

Bus
master
Processor DMA controller 2 Processor

Sequence of signals during transfer of bus mastership for the devices

 Centralized Arbitration

DMA device 2 assumes bus mastership sets BBSY

Time

BR
Processor turns off
BG signals
BG1

BG2

B BS Y

Bus
master
Processor DMA controller 2 Processor
Sequence of signals during transfer of bus mastership for the devices
 Centralized Arbitration
DMA device 2 completes transfer, releases bus mastership Time

BR

BG1

BG2

B BS Y

Bus
master
Processor DMA controller 2 Processor

Processor resumes bus mastership

Sequence of signals during transfer of bus mastership for the devices
 Distributed arbitration
V cc open collector ARB
lines
A RB 3
A RB 2
A RB 1
A RB 0
Start-Arbitration

O.C.

puts its ID “sees” this

on the ARB value on the
lines ARB lines
0 1 0 1 0 1 1 1
Interface circuit
for device A
Distributed arbitration
A transmits 0101 its ID OR’ed by theARB
lines
B transmits 0110 “
Both “see” 0111

Where device sees difference between itself and ARB

lines, it changes all its bits from there “down” to zero
Thus, A changes to 0100, lines change to 0110, and B
wins
More reliable--doesn’t depend on any one device
Highest number (device ID) = highest priority
 Direct Memory Access
 Block of data transfer from high speed device
 Drum, Disk, Tape
 DMA Controller
 Interface which allows I/O transfer directly between Memory and
Device
 Freeing CPU for other tasks
 CPU initializes DMA controller by sending memory address
and the block size (number of words)

ABU Address Bus

Bus Request BR High
S
DBU Data Bus impedance
CPU S (disabled)
Bus granted BG RD Read
When BG is
W Write Enabled
R
 Block Diagram of DMA Controller
Address
Bus

Data Bus
Data Bus Address Bus
Buffers Buffers

DMA
DS

Internal Bus
Select Address Register
Registe
r Select RS
Read RD Word Count Register
Write WR
Control
Bus Request BR Logic Control Register
Bus Grant BG
Interrupt Interrupt
DMA Request
To I/O Device
DMA Acknowledge
DMA I/O Operation
Starting an I/O
 CPU executes instruction to
 Load Memory Address Register

 Load Word Counter

 Load Function (Read or Write) to be performed

 Issue a GO command

Upon receiving a GO command DMA performs I/O

operation as follows independently from CPU
DMA I/O Operation Contd.,
Input
1. Input Device  R (Read Control Signal)
2. Buffer (DMA Controller)  Input Byte; and assemble the
byte into a word until word is full
3. M  Memory address, W (Write Control Signal)
4. Address Reg.  Address Reg. + 1; WC (Word Counter) 
WC – 1
5. If WC = 0, then interrupt to acknowledge done else go to
Step 1
DMA I/O Operation Contd.,
Output
1. M  M Address, R
M Address R  M Address R + 1, WC  WC – 1
2. Disassemble the word
3. Buffer  One byte;
Output Device  W, for all disassembled bytes
4. If WC = 0, then interrupt to acknowledge done, else go
to step 1.
DMA Vs CPU Memory Access
While DMA I/O takes place, CPU is also executing
instructions
 DMA controller and CPU both access Memory
 Memory Access Conflict

Memory Bus Controller

 Coordinating the activities of all devices requesting
memory access
 Priority System
 Memory access by CPU and DMA controller are
interwoven, with the top priority given to DMA controller
 Cycle Stealing
Cycle Steal Mode Data Transfer
CPU is usually much faster than I/O (DMA), thus CPU
uses the most of the memory cycles
DMA controller steals the memory cycles from CPU
For those stolen cycles, CPU remain idle
For those slow CPU,
 DMA controller may steal most of the memory cycles
which may cause CPU remain idle long time
DMA Transfer
Interrupt
BG
CPU RAM
BR
RD WR Addr Data RD WR Addr Data

Data Bus
Address Bus

Address
Select

RD WR Addr Data DMA Ack.

DS
RS I/O
DMA
BR Controller DMA Request Peripheral
device
BG
Interrupt
Input/ Output Processor Channel
Processor with direct memory access capability that
communicates with I/O devices
Channel access memory by cycle stealing
Channel can execute a channel program
 Stored in the main memory
 Consists of Channel Command Word (CCW)
 Each CCW specifies the parameters needed by the channel
to control the I/O device and perform data transfer
operation
CPU initiates the channel by executing an channel I/O
class instruction and once initiated, channel operates
independent of the CPU
Input/ Output Processor Channel

Central
Processing Unit
(CPU)
Memory Bus
Peripheral Devices
Memory PD PD PD PD
Unit
Input-Output
Processor
(IOP) I/O Bus
Channel/CPU Communication
CPU Operations IOP Operations
Send instruction
Transfer status word to
to test IOP. path
memory
If status OK, then
send start I/O Access memory for IOP
instruction to IOP program

CPU Continues with Conduct I/O transfer

another program using DMA; prepare
status report

Request IOP Status I/O transfer completed

interrupt CPU
Check status word Transfer status word to
for correct transfer memory location

Continue
Computer System With Different Interface
Standards

Processor Main
memory

Processor bus
Bridge
PCI bus

Additional SCSI Ethernet USB ISA

memory controller interface controller interf
ace
SCSI bus
IDE
Video disk
Disk CDROM
controller controller

Disk 1 Disk CDROM Keyboard Game

2
System Buses
Bridge: Connects buses with different characteristic
 items on PCI bus appear as though on the system bus
PCI: Peripheral Component Interconnect
 Processor independent
SCSI: Small Computer System Interface
 SCSI controller uses DMA approach
USB: Universal Serial Bus
ISA: Industry Standard Architecture
EISA: 32 bit version of ISA
IDE: Integrated Device Electronics
PCI Bus in a Computer

Host

Main
PCI bridge
memory

PCI b us

Ethernet
Disk Printer interf ace
USB Interface
Need for high transfer rates
Need devices at some distance
High rate  wide bus?
 Problem over distance because of skew
Serial transmission
 Low cost and flexible
 No skew, so high rates OK, distance OK
USB Interface
Hubs have multiple ports
Devices connect to a port
Hubs connect to a port
“Tree structure”
Universal Serial Bus tree structure

Host Computer
Root
Hub

Hub Hub

Hub I/O I/O I/O I/O

device device device device

I/O I/O
device device
USB Interface
Message from host copied to all hubs, to all ports, to
all devices
Only the addressed device responds
Message from device only goes “upstream”--up the
tree
Makes possible a large number of devices through a
few ports at the root hub.
High speed, long distances possible
Split bus operation

Host computer
HS- High speed
Root
F / LS- Full/Lo
w speed Hub
HS H
S
Hub A
Hub B
Message for D
HS F / LS
goes high speed
to A, low speed to Hub A can
D operate in split
Device Device
C D traffic mode,
alternately
sending HS
messages to C
while sending
parts of LS
message to D
USB
Data is transmitted in packets of one or more bytes
First field is always a PID (packet id)
 A 4 bit ID plus the complement for verification
 Therefore, 16 different packet types
Control packets such as ACK are PID only
Token packets used for control
Data packets
USB Packet Format

PID0 PID1 PID2 PID3 PID0 PID1 PID2 PID3

(a) Packet identifier field

8 bits 7 bits 4 bits 5 bits

PID ADDR ENDP CRC16

(b) Token packet, IN or OUT

8 bits 0 to 8192 bits 16 bits

PID DATA CRC16

(c) Data packet

USB Packet Format
ADDR: The address, a 7 bit device address (address
is local to the USB tree)
ENDP: The endpoint, the location within the device
(status register, data register, etc.)
Data packet follows a token packet containing the
address and endpoint of the device.
Packet IDs contain bit that alternates between 0 and
1 to guard against lost packets
An output transfer
Host Hub I/O Device
Token
Data 0

ACK
Time Token
Data0

ACK
Token
Data1

ACK
Token
Data1

ACK
USB
Software (in host computer) sends packets to devices
(hubs just forward them)
Host software periodically polls each hub
 New device when connected has address 0
 If a new device has been added, host collects info about
the device from the memory of the device and assigns it a
7 bit address
Locations within the device (registers) are identified
by a 4 bit endpoint address
Reference
Chapter 4: Computer Organization by Carl
Hamacher, Zvonko Vranesic and Safwat Zaky, 5
edition, McGraw Hill Publications.
Chapter 11: Computer Systems Architecture by M
Morris Mano, 3 edition, Pearson Publications.
Thank You!!