Lecture2 MOS Rev

Chapter 5
LECTURE 2 MOSFET’S
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

Introduction
 IN THIS CHAPTER WE WILL LEARN

 The physical structure of the MOS transistor and how
it works.
 How the voltage between two terminals of the
transistor control the current that flows through the
third terminal, and the equations that describe these
current-voltage characteristics.
 How the transistor can be used to make an amplifier,
and how it can be used as a switch in digital circuits.
Basic MOSFET current-voltage
characteristics

Introduction
 IN THIS CHAPTER WE WILL LEARN

 How to obtain linear amplification from the
fundamentally nonlinear MOS transistor.
 The three basic ways for connecting a MOSFET to
construct amplifiers with different properties.
 Practical circuits for MOS-transistor amplifiers that can
be constructed using discrete components.

Introduction
 We have studied two-terminal semi-conductor devices (e.g.

diode).
 However, now we turn our attention to three-terminal devices.
 They are more useful because they present multitude of
applications, e.g:
 signal amplification, digital logic, memory, etc…

Introduction
 Q: What, in simplest terms, is the desired

operation of a three-terminal device?
 A: Employ voltage between two
terminals to control current flowing
in to the third.

note: MOSFET is more widely used in
implementation of modern electronic
Introduction devices
 Q:
MOSFET
What are
technology
two major types of three-terminal semiconductor devices?
 It
metal-oxide-semiconductor
allows placement of approximately
field-effect
2 billion
transistor
transistors
(MOSFET)on a single IC
 bipolar
 backbone
junction
of transistor
very large(BJT)
scale integration (VLSI)
 Q:
 Why
It is considered
are MOSFET’s
preferable
more widely
to BJTused?
technology for many applications.
 size (smaller)
 ease of manufacture
 lesser power utilization

Current-Voltage
Characteristics
 Figure 5.11. shows an n-

channel enhancement
MOSFET.
 There are four terminals:
 drain (D), gate (G), body
(B), and source (S).
 Although, it is assumed that
body and source are
connected.
Figure 5.11 (a): Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with
an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n
channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect
Microelectronic Circuits by Adel S. Sedra andof the body
Kenneth C. Smithon device operation is unimportant.
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Current-Voltage
Characteristics
 Although MOSFET is symmetrical

device, one often designates
terminals as source and drain.
 Q: How does one make this the potential at drain (vD) is
designation? always positive with respect to
 A: By polarity of voltage applied. source (vS)
 Arrowheads designate “normal”
direction of current flow
 Note that, in part (b), we
designate current as DS.
 No need to place arrow with B.
Figure 5.11 (a): Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with
an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n
channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect
Microelectronic Circuits by Adel S. Sedra andof the body
Kenneth C. Smithon device operation is unimportant.
(0195323033)
Animation Video:
MOS Structure and
Operation

two n-type doped
Device Structure and regions (drain, source)
Operation
layer of SiO2 separates
source and drain
metal, placed on top of

SiO2, forms gate
electrode
one p-type doped region

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view, (b) cross-
section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the thickness of the oxide
layer
Microelectronic Circuits by Adel S. Sedra and Kenneth (tox)(0195323033)
C. Smith is in the range of 1 to 10nm.
Operation with Zero
Gate Voltage
 With zero voltage applied to gate, two back-to-back diodes exist in

series between drain and source.
 “They” prevent current conduction from drain to source when a
voltage vDS is applied.
 yielding very high resistance (1012ohms)

Figure 5.1: Physical structure…
Creating a Channel for
Current Flow
 Q: What happens if (1) source and drain are grounded and (2) positive voltage
is applied to gate? Refer to figure to right.
 step #1: vGS is applied to the gate terminal, causing a positive build up of
positive charge along metal electrode.
 step #2: This “build up” causes free holes to be repelled from region of p-
type substrate under gate.
Figure 5.2: The enhancement-type NMOS transistor

with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
Oxford University Publishing beneath the gate
Q: What happens if (1) source
and drain are grounded and (2)
positive voltage is applied to
gate? Refer to figure to right.
 step #3: This “migration” results in the uncovering of negative

bound charges, originally neutralized by the free holes
 step #4: The positive gate voltage also attracts electrons from the
n+ source and drain regions into the channel.

Q: What happens if (1) source this induced channel is
and drain are grounded and (2) also known as an
positive voltage is applied to inversion layer
gate? Refer to figure to right.
 step #5: Once a sufficient number of “these” electrons

accumulate, an n-region is created…
 …connecting the source and drain regions
 step #6: This provides path for current flow between D and S.

Vtn is used for n-type
Creating a Channel for MOSFET, Vtp is used for
Current Flow p-channel
 threshold
effective /voltage
overdrive
(Vt)voltage
– is the–minimum
is the difference
value ofbetween
vGS required
vGS applied
to formand
a Vt.
conducting channel between drain and source
 typically between 0.3 and 0.6Vdc
 conductance of channel is proportional to VOV, which should
(eq5.1) vOV vGS between
be positive  Vt
 field-effect – when positive vGS is applied, an electric field develops
the gate electrode and induced n-channel – the conductivity of this channel is
 affected by the strength
oxide capacitance (Cox) –ofis field
the capacitance of the parallel plate capacitor per
 SiO
unit gate area acts
2 layer (F/mas
2
) dielectric
 ox is permittivity of SiO2 3.45E 11F / m 

tox is thickness
  of SiO
 2 layer   
 ox
(eq5.3) C ox  in F / m2
tox
Creating a Channel for
Current Flow
 Q: What is main requirement for n-channel Q:to How

form?can one express the
magnitude
 A: The voltage across the “oxide” layer must exceedofVelectron
t.
charge
 For example, when vDS = 0… contained in the channel?
 A: See below…
 the voltage at every point along channel is zero
W and L represent width and length of channel respectively
 the voltage across the oxide layer is uniform and  equal
   to  v GS    
(eq5.2) Q C ox WL vOV in C
 Q: What is effect of vOV on n-

channel?
 A: As vOV grows, so does the
depth of the n-channel as well
as its conductivity.
Applying a
Small vDS
 Q: For small values of vDS, how does one calculate iDS (aka. iD)? A:
Equation (5.7)…
 Q: What is the origin of this equation?
 A: Current is defined in terms of charge per unit
length of n-channel as well as electron drift velocity.
¿𝜇 𝑛 represents mobility of electrons at surface of the
¿ n − channel in 𝑚2 /𝑉𝑠
⏞
(eq 5.7)𝑖 =(⏟
𝐶 𝑊𝑣 )𝐷
𝜇 𝑣
⏟ 𝐿
in 𝐴 𝑜𝑥 𝑂𝑉 (
¿charge per unit
𝑛 𝐷𝑆
)
¿length of ¿ electron
Oxford University Publishing ¿𝑛 −channel ¿ drift velocity
¿ in 𝐶 /𝑚 ¿ in 𝑚/ 𝑠
Applying
a Small vDS
 Q: How does one calculate charge per unit length of n-channel

(Q/uL)?
 A: For small values of vDS, one can still assume that
voltage between gate and n-channel is constant
(along its length) – and equal to vGS.
 A: Therefore, effective voltage between gate and n-
channel remains equal to vOV.
 A: Therefore, (5.2) from two slides back applies.

Applying a
Small vDS
 Q: How does one calculate action: divide both sides by L

      
charge per unit length of n- (eq5.2) Q C ox WL vOV in C
channel (Q/uL)? Q
 A: Use (5.2) to calculate (eq5.4) C oxWvOV in C / m
L
charge per unit L of channel.
 Q: How does one calculate
vDS
electron drift velocity? (eq5.5) E  in V / m
L
 A: Note that vDS establishes an
(eq5.6) e-drift velocity 
electric field E across length
of n-channel, this may V m2 m
 n E in 
calculate e-drift velocity. m Vs s
Applying a
Small vDS
 Q: How does one calculate action: divide both sides by L

      
charge per unit length of n- (eq5.2) Q C ox WL vOV in C
channel (Q/uL)? Q
Note
 A:that these two
Use (5.2) to calculate (eq5.4) C oxWvOV in C / m
values mayperbeunit
employed L
charge L of channel.
 toQ:define current
How does in
one calculate
vDS
amperes (aka.velocity?
electron drift C/s). (eq5.5) E  in V / m
L
 A: Note that vDS establishes an
(eq5.6) e-drift velocity 
electric field E across length
of n-channel, this may V m2 m
 n E in 
calculate e-drift velocity. m Vs s
Applying a
Small vDS
 Q: What is observed from equation (5.7)?

 A: For small values of vDS, the n-channel acts like a
variable resistance whose value is controlled by vOV.
 W 
(eq5.7) iD  nC ox  vOV  vDS in A
 L 
vDS 1
(eq5.8a) rDS   in 
iD W 
nCox    vOV

 L 
process
transconductance aspect
parameter
ratio
Applying a Note that this vOV represents
the depth of the n-channel -
Small vDS what if it is not assumed to
be constant? How does this
equation change?
Note
Q: What do we
that this note
is one from equation (5.7)?
VERY
 A: For small
IMPORTANT equationvalues
in of vDS, the n-channel acts like a
Chapter 5.
variable resistance whose value is controlled by vOV.
 W 
(eq5.7) iD  nC ox  vOV  vDS in A
 L 
vDS 1
(eq5.8a) rDS   in 
iD W 
nCox    vOV

 L 
process
transconductance aspect
parameter
ratio
Applying a Small vDS
 Q: What three factors is rDS dependent on?

 A: process transconductance parameter for NMOS
(mnCox) – which is determined by the manufacturing
process
 A: aspect ratio (W/L) – which is dependent on size
requirements / allocations
 A: overdrive voltage (vOV) – which is applied by the
user

The p-Channel
MOSFET
 Figure 5.9(a) shows cross-

sectional view of a p-channel
enhancement-type MOSFET.
 structure is similar but
“opposite” to n-channel
 complementary devices – two
devices such as the p-channel
and n-channel MOSFET’s.
Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor
shown in Figure 5.1(b), except that all semiconductor regions are reversed in polarity. (b) A negative
voltage vGS of magnitude greater than |Vtp| induces a p-channel, and a negative vDS causes a current iD to
flow
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith from source to drain.
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5.1.7. The p-Channel
MOSFET
 Q: What are main differences

between n-channel and p-channel?
 A: Negative (not positive)
voltage applied to gate “closes”
the channel
 allowing path for current flow
 A: Threshold voltage (previously
represented as Vt) is
represented as Vtp
 |vGS| > |Vtp| to close channel
Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor
shown in Figure 5.1(b), except that all semiconductor regions are reversed in polarity. (b) A negative
voltage vGS of magnitude greater than |Vtp| induces a p-channel, and a negative vDS causes a current iD to
flow
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith from source to drain.
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Example 5.1: NMOS
MOSFET
 Example 5.1. Problem Statement: Consider an NMOS

process technology for which Lmin = 0.4mm, tox = 8nm, mn =
450cm2/Vs, Vt = 0.7V.
 Q(a): Find Cox and k’n.
 Q(b): For a MOSFET with W/L = 8mm/0.8mm, find the values

of vOV, vGS and vDS required to cause the device to operate as a
1000ohm resistor with dc current ID = 100mA.

Example 5.1: NMOS
MOSFET

Operation as vDS is
Increased
 Q: What happens to iD when vDS increases beyond “small values”?

 A: The relationship between them ceases to be linear.
 Q: How can this non-linearity be explained?
 step #1: Assume that vGS is held constant at value greater than
Vt.
 step #2: Also assume that vDS is applied and appears as voltage
drop across n-channel.
 step #3: Note that voltage decreases from vGS at the source end
of channel to vGD at drain end, where…
 vGD = vGS – vDS
vOV vov- vDS
Average voltage across

the channel = Vov + (Vov-
vDS)/2 = Vov- 1/2vDS
Figure 5.5: Operation of the e-NMOS transistor as vDS is increased.

Q: How can this non-
linearity be explained?
action: replace
 vOV with vOV  12 vDS 
      
W
 step #4: Define iDS (eq5.7) iD  nC ox  vOV  12 vDS  vDS
 L 
in terms of vDS and  
vOV.  W
   n C ox  v OV  2 v DS v DS
1
if vDS  vOV
iD is dependent on the L

(eq5.7) iD  W
apparent vOV (not vDS    n C ox  v OV  2 v DS vDS
1
otherwise
     L      
inherently) which does not  if vDS vOV then vDS vOV
change after vDS > vOV  W

   n C ox   v OV  2 v DS v DS
1
if vDS  vOV
(eq5.14) iD  L in A
 1 W

 nC ox  vO2 V otherwise
2 L
triode vs. saturation region
saturation occurs
once vDS > vOV
 W
 triode:   n C ox  v OV  2 v DS v DS
1
if vDS  vOV
L
(eq5.14) iD  in A
 saturation: 1 nC ox W vO2 V otherwise
 Publishing 2
Microelectronic Circuits by Adel S.Sedra and Kenneth C. Smith (0195323033)
Oxford University
L
Operation for vDS >
pinch-off does not mean
vOV blockage of current
 Q: What happens if vDS > vOV?

 A: MOSFET enters
saturation region. Any
further increase in vDS has
no effect on iD. A pinch-off
will be produced at the
drain end channel where
the depth is reduced to 0.
 Further increasing vDS
(beyond vOV) has no effect
on theOxford channel shape and
University Publishing
i remains constant.
Example 5.2: NMOS
MOSFET
 Example 5.2. Problem Statement: Consider an NMOS

process technology for which Lmin = 0.4mm, tox = 8nm, mn =
450cm2/Vs, Vt = 0.7V.
 Q(a): Find Cox and k’n.
 Q(b): For a MOSFET with W/L = 8mm/0.8mm, calculate the
values of vOV, vGS, and vDSmin needed to operate the transistor
in the saturation region with dc current ID = 100mA.

Quick Recap!
 The equation used n represents mobility of electrons at surface of the

n-channel in m2 / Vs
              
to define iD depends  nvDS 
(eq5.7) iD C oxWvOV  in A
on relationship btw       L 
charge per unit   
vDS and vOV. length of
n -channel
electron
drift velocity
 vDS << vOV in C / m in m2 / Vs
W
 vDS < vOV (eq5.14) iD nC ox  vOV  12 vDS vDS in A
L
 vDS => vOV 1 W 2
(eq5.17) iD  nC ox  vOV in A
 vDS >> vOV 2 L
1 W 2
(eq5.23) i   n been

This Dhas notC ox  vOV 1  vyet!
covered DS  in A
2 L
The iD-vDS
Characteristics
 Table 5.1. provides a

compilation of the conditions
and formulas for operation of
NMOS transistor in three
regions.
 cutoff
 triode
 saturation

The iD-vGS
Characteristic
 Q: When MOSFET’s are employed to design amplifier, in what range will they be
operated?
 A: saturation
 In saturation, the drain current (iD) is…
 dependent on vGS
 independent of vDS
 In effect, it becomes a voltage-controlled current source.
 This is key for amplification.
Figure 5.13: The iD – vDS characteristics

for an enhancement-type NMOS
Oxford University Publishing transistor
DC Analysis of MOS Transistors

Example 5.2: NMOS
Transistor
 Example 5.2. Problem Statement: Consider an NMOS transistor

fabricated in an 0.18-mm process with L = 0.18mm and W = 2mm.
The process technology is specified to have Cox = 8.6fF/mm2, mn =
450cm2/Vs, and Vtn = 0.5V.
 Q(a): Find VGS and VDS that result in the MOSFET operating at the
edge of saturation with ID = 100mA.
 Q(b): If VGS is kept constant, find VDS that results in ID = 50mA.
 Q(c): To investigate the use of the MOSFET as a linear amplifier, let
it be operating in saturation with VDS = 0.3V. Find the change in iD
resulting from vGS changing from 0.7V by +0.01V and -0.01V.
Example 5.2: NMOS
Transistor

Example 5.2

5.3. MOSFET Circuits at
DC
 We move on to discuss how

MOSFET’s behave in dc
DC
circuits.
 We will neglect the effects of
channel length modulation
(assuming l = 0).
 We will work in terms of
overdrive voltage (vOV), which
reduces need to distinguish
between PMOS and NMOS.

Example 5.3: NMOS
Transistor
 Problem Statement: Design

the circuit of Figure 5.21, that
is, determine the values of RD
and RS – so that the transistor
operates at ID = 0.4mA and VD =
+0.5V. The NMOS transistor
has Vt = 0.7V, mnCox = 100mA/V2,
L = 1mm, and W = 32mm.
Neglect the channel-length
modulation effect (i. e. assume
that l = 0). Figure 5.21: Circuit for Example
5.3.
Example 5.3: NMOS
Transistor

Example 5.3: NMOS
Transistor

Example 5.5: MOSFET
 Problem Statement:
Design the circuit in Figure
5.23 to establish a drain
voltage of 0.1V. What is
the effective resistance
between drain and source
at this operating point?
Let Vtn = 1V and k’n(W/L) =
1mA/V2. Figure 5.23: Circuit for Example
5.5.
Example 5.5: MOSFET

Example 5.5: MOSFET

Example 5.6: MOSFET
 Problem Statement: Analyze the circuit shown in Figure 5.24(a) to

determine the voltages at all nodes and the current through all
branches. Let Vtn = 1V and k’n(W/L) = 1mA/V2. Neglect the
channel-length modulation effect (i.e. assume l = 0).
Figure 5.24: (a) Circuit for
circuit with some of the

analysis details shown.
Example 5.6. (b) The

Example 5.6: MOSFET

Example 5.6: MOSFET

Characteristics of the p-
channel MOSFET
 Characteristics of the p-channel MOSFET are similar to the n-

channel, however with many signs reversed.
 Please review section 5.2.5 from the text, with focus on table 5.2.

Example 5.7: PMOS
Transistor
 Problem Statement: Design the circuit

of Figure 5.25 so that transistor
operates in saturation with ID = 0.5mA
and VD = +3V. Let the enhancement-
type PMOS transistor have Vtp = -1V
and k’p(W/L) = 1mA/V2. Assume l = 0.
 Q: What is the largest value that RD
can have while maintaining saturation-
region operation?
Figure 5.25: Circuit for
Example 5.7.
Example 5.7: PMOS
Transistor

AC Analysis of MOS Transistors

 Q: What is one problem with (5.21)?
The iD-vGS  A: It is nonlinear w/ respect to
Characteristic vOV … however, this is not of
concern now.
 In effect, it becomes a voltage-controlled current source.

 This is key for amplification.
 Refer to (5.21).
2
vOV
   
1 W  2
(eq5.21) iD  kn   vGS  Vtn 
  2  L     
this relationship provides
basis for application of
MOSFET as amplifier
Figure 5.14: The iD-vGS characteristic of an NMOS transistor operating in the saturation region. The iD-vOV
characteristic canOxford be obtained by simply re-labeling the horizontal axis, that is, shifting the origin to the point
University Publishing
vGS = Vtn.
The iD-vGS
Characteristic
 The view of transistor as CVCS is exemplified in figure 5.15.

 This circuit is known as the large-signal equivalent circuit.
 Current source is ideal.
 Infinite output resistance represents independent, in saturation, of iD from
vDS..
 This occurs if λ = 0, where λ is the channel length modulation (will discuss in
a later section)
Figure 5.15: Large-signal equivalent-circuit model

of an n-channel MOSFET operating in the
saturation
note that, in this circuit, iD is
completely independent of
vDS (because no shunt Oxford University Publishing
resistor exists)
5.5. Small-Signal input voltage to
be amplified output voltage
Operation and
Models dc bias
voltage
 Linear amplification may be obtained from MOSFET via…
 Operation in saturation region
 Utilization of small-input
 This section will explore small-signal operation in detail
 Note the conceptual amplifier circuit to right
Figure 5.34: Conceptual circuit utilized

to study the operation of the MOSFET
as a small-signal amplifier.
5.5.1. The DC Bias
Point
 Q: How is dc bias current

ID defined?
only applies in saturation where VDS VOV
         
1 2 1
(eq5.40) ID  kn VGS  Vt   knVOV
2
2 2
(eq5.41) VDS VDD  RD ID
Figure 5.34: Conceptual circuit utilized

5.5.2. The Signal
Current in the Drain(eq5.42) v V  v GS GS gs
Terminal  

   action:
  state(5.17)  
2
 
 Q: What is effect of vgs on 1 
(eq5.17) iD  kn VGS  vgs  Vt 
iD? 2     
  GS    
v
 step #1: Define vGS as in vOV

action: expand the squared
(5.42). term via VGS  Vt and vgs
             
2
 step #2: Define iD, 1  VGS  Vt    
(eq5.43) iD  kn  
separate terms as 2    2 VGS  Vt vgs  vgs 
2
          
function of VGS and vgs VGS vgs  Vt 
     action:
  simp
 lify    
1 2
Note that this differs from previous iD  kn  GS
V  Vt  
(eq5.43) 2
analyses - because of attempt to 1 2
isolate the Oxfordeffect of v C. Smith
University Publishing from VGS.   kn VGS  Vt vgs  knvgs
Microelectronic Circuits by Adel S. Sedra and Kennethgs (0195323033) 2
Note that to minimize nonlinear
Q: What is effect of distortion, vgs should be kept small.
vgs on iD?
½knvgs2 << kn(VGS-Vt)vgs
vgs << 2(VGS-Vt)
 step #3: Classify terms. vgs << 2vOV
 dc bias current (ID).
 linear gain – is desirable.
 nonlinear distortion – is undesirable, because rep.
distortion.
1 2 1 2
(eq5.43) iD  kn VGS  Vt   kn VGS  Vt v gs  k nv gs
2            2 

linear
dc bias current ID  gain nonlinear
term distortion
term
Q: What is effect of
vgs on iD?
 step #4: Adapt (5.43) for small-signal condition.

 If vgs << 2vOV , neglect distortion.
1 2 1 2
(eq5.43) iD  kn VGS  Vt   kn VGS  Vt v gs  knv gs
2            2 

linear
dc bias current ID  gain nonlinear
term distortion
term
vgs
(eq5.47) MOSFET transconductance gm  kn VGS  Vt 
id
Small-Signal Note that this resistor (ro)
takes on value 10kOhm to
Equivalent Models 1MOhm and represents
channel-length modulation.
Figure 5.37: Small-signal models for the MOSFET: (a) neglecting the dependence of
iD on vDS in saturation (the channel-length modulation effect) and (b) including the
Microelectronic Circuits by Adel S. Sedra andeffect
Kenneth C.of
Smithchannel
(0195323033) length modulation
The Voltage Gain
 Q: How is voltage gain

(Av) defined?
 step #1: Define vDS for
circuit of Figure 5.34
using KVL.
action: apply
small-signal
condition
    
vDS VDD  RD iD VDD  RD ID  id 
 action:
  regroup
  terms
 action:
  simplify
vDS VDD  RD ID  RD id VDS  RD id Figure 5.34: Conceptual circuit utilized
     to study the operation of the MOSFET
dc component vds
VDS  by Adel S. Sedra and Kenneth C. Smith (0195323033)
Microelectronic Circuits
Q: How is voltage
gain (Av) defined?
 step #2: Isolate vds action:

 isolate
 vds
component of vDS. (eq5.50) vds  RD id
 step #3: Solve for gain action: insert (5.47)
  
(Av). (eq5.50) vds  RD gmvgs 
  
( 5.47)

 action:
  solve for gain
vds
Figure 5.34: Conceptual circuit utilized (eq5.51) Av   gm RD
v gs
as aCircuits
Microelectronic small-signal amplifier.
by Adel S. Sedra and Kenneth C. Smith (0195323033)
5.5.3. The Voltage
Gain
 Output signal is shifted from

input by 180O.
 Input signal vgs << 2(VGS – Vt).
 Operation should remain in
MOSFET saturation region
 vDS > vGS – Vt (legroom)
 vDS < VDD (headroom)
Figure 5.36: Total instantaneous

voltage vGS and vDS for the circuit in
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) Figure 5.34.
5.5.6. The
Transconductance gm
 Observations from (5.47) vgs

 gm is proportional to mn, Cox, (eq5.47) gm  kn VGS  Vt 
id
ratio W/L, dc component VOV. action: make some
substitutions
 MOSFET with short / wide      
W
channel provides maximum (eq5.47) gm kn VGS  Vt 
gain. L
kn
 Gain may be increased via VGS, action: simplify
  
but not without reducing W
allowable swing of vgs. (eq5.55) gm  kn VOV
L

5.5.6: The 1 W 2
(eq5.40) ID  kn VOV
Transconductance gm 2 L
action: solve
(5.40) for VOV
      
2ID
(eq5.40) VOV 
kn W / L
 Observations from (5.47) 
 gm is proportional to W
(eq5.55) gm kn VOV
square root of dc bias L
current (ID) action: substitute for
VOV as defined above
     
 For given ID, gm is
W 2ID
proportional to (W/L)1/2 (eq5.56) gm kn
L knW / L
 action:
  simplify
 
(eq5.56) gm  2kn W / L ID
5.5.6: The
Transconductance gm
 In summary, there are

three relationships for
determining gm: W
 (5.55), (5.56), and (eq5.55) gm kn VOV
L
(5.57) (eq5.56) gm  2kn W / L ID
 These relationships are
2ID
dependent on three (eq5.57) gm 
VOV
design parameters:
 W/L, VOV, ID
Example 5.10: MOSFET
Amplifier
 Example 5.10 Problem Statement: Figure 5.39(a) shows a discrete

common-source MOSFET amplifier utilizing a drain-to-gate
resistance RG for biasing purposes. Such a biasing arrangement
will be studied in Section 5.7. The input signal vI is coupled to the
gate via a large capacitor, and the output signal at the drain is
coupled to the load resistance RL via another large capacitor. The
transistor has Vt = 1.5V, k’n(W/L) = 0.25mA/V2, and VA = 50V.
Assume the coupling capacitors to be sufficiently large so as to act
as short circuits at the signal-frequencies of interest.
 Q: We wish to analyze this amplifier circuit to determine its (a)
small-signal voltage gain, its (b) input resistance, and the largest
allowableby Adel
Microelectronic Circuits input signal.
S. Sedra and Kenneth C. Smith (0195323033)
note: capacitors block dc
signals completely, but
have no effect on small-
signal
Figure 5.39: Example 5.10 amplifier circuit.

DC Analysis

DC Analysis

AC Analysis

AC Analysis

AC Analysis

AC Analysis

AC Analysis

Finite Output
Resistance in
Saturation
 In previous section, we assume (in saturation) iD is independent of

vDS.
 Therefore, a change DvDS causes no change in iD.
 This implies that the incremental resistance ro is
infinite.
 It is based on the idealization that, once the n-channel
is pinched off, changes in vDS will have no effect on iD.
 The problem is that, in practice, this is not completely
true.
Finite Output
Resistance in
Saturation
 Q: What effect will increased vDS have on

n-channel once pinch-off has occurred?
 A: Increasing vDS beyond vDSsat causes
the channel pinch-off point to move
slightly away from the drain.
 Increasing vDS will increase the
electric field that will sweep the
electrons to the side of the drain.
 A: This reduces the effective channel
length by ΔL. The length of the n-
channel will decrease.
 Known as channel length
modulation.

Finite Output
Resistance in
Saturation
 Q: How do we account for “this

effect” in iD?
 A: Refer to (5.23).
   valid
 when
 vDS vOV  
1 W 2
(eq5.17) iD  nC ox  vOV in A
2 L
1 W 2
(eq5.23) iD  nC ox  vOV 1  v DS  in A
  2    L        
valid when vDS vOV
 A: Addition of finite output

Figure 5.18: Large-Signal Equivalent Model of the
resistance (ro). n-channel MOSFET in saturation, incorporating the
output resistance ro. The output resistance
models the linear dependence of iD on vDS and is
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) given by (5.23)
Finite Output
Resistance in
Saturation  i 
(eq5.24) ro  D 
1
 vDS  vGS constant

 
 Q: How is ro defined?       (5.23)
     
 step #1: Note that ro is the iD  1 W 2 
(eq5.23)     C
n ox  v OV 1   v 
DS 
vDS vDS  2 L
1/slope of iD-vDS 
 
characteristic.
      (5.23)
     
 step #2: Define relationship iD  1 W 2 
between iD and vDS using
(eq5.23)    n ox 
 C v OV 1   v DS  
vDS vDS  2 L 
(5.23).  
 step #3: Take derivative of (eq5.23)
iD 1 W 2
 nC ox  vOV 
this function. vDS 2 L
 step #4: Use above to define  
ro. 1
1 W 2 
(eq5.25) ro  nC ox  vOV 
2 L  vGS constant
1 VA
(eq5.24) ro  
Oxford University Publishing  iD iD
Finite Output
Resistance in
Saturation
 Q: What is l?
 A: A device parameter with the units of V -1, the value of which depends on
manufacturer’s design and manufacturing process.
 much larger for newer tech’s
 Figure 5.17 demonstrates the effect of channel length modulation on vDS-iD
curves
 In short, we can draw a straight line between VA and saturation.
Figure 5.17: Effect of vDS on iD in the
saturation region. The MOSFET
parameter VA depends on the process
technology and, for a given process, is
proportional to the channel length L.
More Observations
 Model (b) is more

accurate than model (a)
less accurate, b/c does not consider
 ro = VA / ID channel length modulation
      
vds
 Small signal parameters (eq5.51) Av   gmRD
vgs
(gm, ro) both depend on dc
vds
bias point (eq5.54) Av   gm RD || ro 
vgs
 If channel-length         
more accurate, b/c does consider
modulation is considered, channel length modulation
(5.51) becomes (5.54).

Summary
 The enhancement-type MOSFET is current the modt widely used

semiconductor device. It is the basis of CMOS technology, which
is the most popular IC fabrication technology at this time. CMOS
provides both n-channel (NMOS) and p-channel (PMOS)
transistors, which increases design flexibility. The minimum
MOSFET channel length achievable with a given CMOS process is
used to characterize the process
 The overdrive voltage |VOV| = |VGS| - |Vt| is the key quantity that
governs the operation of the MOSFET. For amplifier applications,
the MOSFET must operate in the saturation region.

Summary
 In saturation, iD shows some linear dependence on vDS as a result

of the change in channel length. This channel-length modulation
phenomenon becomes more pronounced as L decreases. It is
modeled by ascribing an output resistance ro = |VA|/ID to the
MOSFET model. Although the effect of ro on the operation of
discrete-circuit MOS amplifiers is small, that is not the case in IC
amplifiers.
 The essence of the use of MOSFET as an amplifier is that in
saturation vGS controls iD in the manner of a voltage-controller
current source. When the device is dc biased in the saturation
region, a small-signal input (vgs) may be amplified linearly.

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Chapter 5

Oxford University Publishing

Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

 IN THIS CHAPTER WE WILL LEARN

Oxford University Publishing

 IN THIS CHAPTER WE WILL LEARN

Oxford University Publishing

 We have studied two-terminal semi-conductor devices (e.g.

Oxford University Publishing

 Q: What, in simplest terms, is the desired

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Oxford University Publishing

 Figure 5.11. shows an n-

 Although MOSFET is symmetrical

Oxford University Publishing

Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

metal, placed on top of

one p-type doped region

 With zero voltage applied to gate, two back-to-back diodes exist in

Oxford University Publishing

Figure 5.2: The enhancement-type NMOS transistor

 step #3: This “migration” results in the uncovering of negative

Figure 5.2: The enhancement-type NMOS transistor

 step #5: Once a sufficient number of “these” electrons

Figure 5.2: The enhancement-type NMOS transistor

 ox is permittivity of SiO2 3.45E 11F / m 

 Q: What is main requirement for n-channel Q:to How

 Q: What is effect of vOV on n-

 Q: How does one calculate charge per unit length of n-channel

Oxford University Publishing

 Q: How does one calculate action: divide both sides by L

 Q: How does one calculate action: divide both sides by L

 Q: What is observed from equation (5.7)?

 Q: What three factors is rDS dependent on?

Oxford University Publishing

 Figure 5.9(a) shows cross-

 Q: What are main differences

 Example 5.1. Problem Statement: Consider an NMOS

 Q(a): Find Cox and k’n.

 Q(b): For a MOSFET with W/L = 8mm/0.8mm, find the values

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Oxford University Publishing

 Q: What happens to iD when vDS increases beyond “small values”?

Average voltage across

Figure 5.5: Operation of the e-NMOS transistor as vDS is increased.

change after vDS > vOV  W

 Q: What happens if vDS > vOV?

 Example 5.2. Problem Statement: Consider an NMOS

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 The equation used n represents mobility of electrons at surface of the

 Table 5.1. provides a

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Figure 5.13: The iD – vDS characteristics

Oxford University Publishing

Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)

 Example 5.2. Problem Statement: Consider an NMOS transistor

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 We move on to discuss how

Oxford University Publishing